mirror of
https://github.com/ApfelTeeSaft/reactos.git
synced 2026-09-01 12:23:29 +00:00
- Share some more inline functions between the kernel and freeldr
- Use __ltr instead of Ke386SetTr - refactor KiInitializeTss - Update some Mm conatnts - Halfplement KeFlushEntireTb - Clean the mapping of page 0 in KiSystemStartup, as long as we don't clean mappings in freeldr - Fix a serious bug in KiPageFault, where ebp was used instead of rbp, resulting in recursive page faults as soon as usermode mappings were cleared - Refactor MmArmInitSystem and related. Pahse 0 initialisation completes here now. we fail later in freelist setup code, which is not 64 bit safe. svn path=/branches/ros-amd64-bringup/; revision=44144
This commit is contained in:
Timo Kreuzer
@@ -58,28 +58,6 @@ typedef struct _PAGE_DIRECTORY_AMD64
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HARDWARE_PTE Pde[512];
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} PAGE_DIRECTORY_AMD64, *PPAGE_DIRECTORY_AMD64;
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PKGDTENTRY64
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FORCEINLINE
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KiGetGdtEntry(PVOID pGdt, USHORT Index)
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{
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return (PKGDTENTRY64)((ULONG64)pGdt + (Index & ~RPL_MASK));
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}
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VOID
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FORCEINLINE
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KiInitGdtEntry(PKGDTENTRY64 Entry, ULONG64 Base, ULONG Limit, UCHAR Type, UCHAR Dpl)
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{
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Entry->Bits.Type = Type;
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Entry->Bits.Present = 1;
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Entry->Bits.Dpl = Dpl;
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Entry->BaseLow = (USHORT)(Base & 0xFFFF);
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Entry->Bytes.BaseMiddle = (UCHAR)(Base >> 16);
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Entry->Bytes.BaseHigh = (UCHAR)(Base >> 24);
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Entry->BaseUpper = (ULONG)(Base >> 32);
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Entry->LimitLow = (USHORT)(Limit & 0xFFFF);
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Entry->Bits.LimitHigh = (ULONG)((Limit >> 16) & 0xf);
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Entry->MustBeZero = 0;
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}
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VOID FrLdrSetupGdtIdt();
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@@ -354,8 +354,8 @@ WinLdrSetProcessorContext(PVOID GdtIdt, IN ULONG64 Pcr, IN ULONG64 Tss)
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Ke386SetGs(KGDT_64_DATA | RPL_MASK); // 0x2b
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Ke386SetSs(KGDT_64_R0_SS); // 0x18
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// Load TSR
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Ke386SetTr(KGDT_TSS);
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/* Load TSR */
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__ltr(KGDT_TSS);
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DPRINTM(DPRINT_WINDOWS, "leave WinLdrSetProcessorContext\n");
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}
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@@ -9,6 +9,57 @@
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#define KeSetCurrentIrql(x) __writecr8(x)
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PKGDTENTRY64
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FORCEINLINE
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KiGetGdtEntry(PVOID pGdt, USHORT Selector)
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{
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return (PKGDTENTRY64)((ULONG64)pGdt + (Selector & ~RPL_MASK));
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}
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PVOID
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FORCEINLINE
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KiGetGdtDescriptorBase(PKGDTENTRY Entry)
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{
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return (PVOID)((ULONG64)Entry->BaseLow |
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(ULONG64)Entry->Bytes.BaseMiddle << 16 |
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(ULONG64)Entry->Bytes.BaseHigh << 24 |
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(ULONG64)Entry->BaseUpper << 32);
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}
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VOID
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FORCEINLINE
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KiSetGdtDescriptorBase(PKGDTENTRY Entry, ULONG64 Base)
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{
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Entry->BaseLow = Base & 0xffff;
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Entry->Bits.BaseMiddle = (Base >> 16) & 0xff;
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Entry->Bits.BaseHigh = (Base >> 24) & 0xff;
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Entry->BaseUpper = Base >> 32;
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}
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PVOID
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FORCEINLINE
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KiSetGdtDescriptorLimit(PKGDTENTRY Entry, ULONG Limit)
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{
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Entry->LimitLow = Limit & 0xffff;
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Entry->Bits.LimitHigh = Limit >> 16;
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}
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VOID
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FORCEINLINE
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KiInitGdtEntry(PKGDTENTRY64 Entry, ULONG64 Base, ULONG Size, UCHAR Type, UCHAR Dpl)
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{
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KiSetGdtDescriptorBase(Entry, Base);
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KiSetGdtDescriptorLimit(Entry, Size - 1);
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Entry->Bits.Type = Type;
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Entry->Bits.Dpl = Dpl;
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Entry->Bits.Present = 1;
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Entry->Bits.System = 0;
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Entry->Bits.LongMode = 0;
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Entry->Bits.DefaultBig = 0;
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Entry->Bits.Granularity = 0;
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Entry->MustBeZero = 0;
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}
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#if defined(__GNUC__)
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static __inline__ __attribute__((always_inline)) void __lgdt(void *Source)
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@@ -41,9 +92,9 @@ static __inline__ __attribute__((always_inline)) void __stmxcsr(unsigned long *D
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__asm__ __volatile__("stmxcsr %0" : : "m"(*Destination) : "memory");
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}
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static __inline__ __attribute__((always_inline)) void __ltr(unsigned short *Source)
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static __inline__ __attribute__((always_inline)) void __ltr(unsigned short Source)
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{
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__asm__ __volatile__("ltr %0" : : "m"(*Source));
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__asm__ __volatile__("ltr %0" : : "rm"(Source));
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}
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static __inline__ __attribute__((always_inline)) void __str(unsigned short *Destination)
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@@ -51,25 +102,6 @@ static __inline__ __attribute__((always_inline)) void __str(unsigned short *Dest
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__asm__ __volatile__("str %0" : : "m"(*Destination) : "memory");
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}
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#define Ke386GetLocalDescriptorTable(X) \
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__asm__("sldt %0\n\t" \
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: /* no outputs */ \
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: "m" (X));
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#define Ke386SetLocalDescriptorTable(X) \
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__asm__("lldt %w0\n\t" \
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: /* no outputs */ \
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: "q" (X));
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#define Ke386SetTr(X) __asm__ __volatile__("ltr %%ax" : :"a" (X));
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#define Ke386GetTr(X) \
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__asm__("str %0\n\t" \
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: /* no outputs */ \
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: "m" (X));
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#define Ke386SaveFlags(x) __asm__ __volatile__("pushfq ; popq %0":"=rm" (x): /* no input */)
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#define Ke386RestoreFlags(x) __asm__ __volatile__("pushq %0 ; popfq": /* no output */ :"irm" (x):"memory")
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#define _Ke386GetSeg(N) ({ \
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unsigned int __d; \
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@@ -46,6 +46,8 @@
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#define X86_MSR_CSTAR 0xC0000083
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#define X86_MSR_SFMASK 0xC0000084
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#define AMD64_TSS 9
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#ifndef __ASM__
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#include "intrin_i.h"
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@@ -118,21 +120,10 @@ KeInvalidateTlbEntry(IN PVOID Address)
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}
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struct _KPCR;
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VOID
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KiInitializeGdt(struct _KPCR* Pcr);
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VOID
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Ki386ApplicationProcessorInitializeTSS(VOID);
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// Hack
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VOID KiRosPrepareForSystemStartup(ULONG, PROS_LOADER_PARAMETER_BLOCK);
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VOID
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FASTCALL
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Ki386InitializeTss(
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IN PKTSS Tss,
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IN PVOID GdtBase,
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IN UINT64 Stack
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);
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KiInitializeTss(IN PKTSS Tss, IN UINT64 Stack);
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VOID KiDivideErrorFault();
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VOID KiDebugTrapOrFault();
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@@ -5,11 +5,24 @@
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#ifndef __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H
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#define __NTOSKRNL_INCLUDE_INTERNAL_AMD64_MM_H
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/* Helper macros */
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#define PAGE_MASK(x) ((x)&(~0xfff))
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#define PAE_PAGE_MASK(x) ((x)&(~0xfffLL))
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#define HYPER_SPACE 0xFFFFF70000000000ULL
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#define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL
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/* Memory layout base addresses */
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#define HYPER_SPACE 0xFFFFF70000000000ULL
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#define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL
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#define MI_SESSION_VIEW_END (PVOID)0xFFFFF97FFF000000ULL
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#define MI_SESSION_SPACE_END (PVOID)0xFFFFF98000000000ULL
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#define MI_PAGED_POOL_START (PVOID)0xFFFFFA8000000000ULL
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#define MI_NON_PAGED_SYSTEM_START_MIN 0xFFFFFAA000000000ULL
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#define MI_NONPAGED_POOL_END (PVOID)0xFFFFFAE000000000ULL
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#define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
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PULONG64
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FORCEINLINE
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@@ -87,8 +100,8 @@ MiAddressToPte(PVOID Address)
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#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19*1024*1024) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32*1024*1024) >> PAGE_SHIFT)
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#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * 1024 * 1024)
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#define MI_MAX_NONPAGED_POOL_SIZE (128 * 1024 * 1024)
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#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_MAX_FREE_PAGE_LISTS 4
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#define MI_MIN_INIT_PAGED_POOLSIZE (32 * 1024 * 1024)
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@@ -104,9 +117,6 @@ MiAddressToPte(PVOID Address)
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#define MI_SYSTEM_VIEW_SIZE (16 * 1024 * 1024)
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#define MI_PAGED_POOL_START (PVOID)0xFFFFFA8000000000ULL
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#define MI_NONPAGED_POOL_END (PVOID)0xFFFFFAE000000000ULL
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#define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
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#define MM_HIGHEST_VAD_ADDRESS \
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(PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
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@@ -46,6 +46,9 @@ BOOLEAN KiSMTProcessorsPresent;
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KIRQL KiOldIrql;
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ULONG KiFreezeFlag;
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/* Flush data */
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volatile LONG KiTbFlushTimeStamp;
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/* CPU Signatures */
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static const CHAR CmpIntelID[] = "GenuineIntel";
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static const CHAR CmpAmdID[] = "AuthenticAMD";
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@@ -90,7 +93,7 @@ KiSetProcessorType(VOID)
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KeGetCurrentPrcb()->CpuID = 0;
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/* Save EFlags */
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Ke386SaveFlags(EFlags);
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EFlags = __readeflags();
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/* Do CPUID 1 now */
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__cpuid(Reg, 1);
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@@ -115,7 +118,7 @@ KiSetProcessorType(VOID)
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KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
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/* Restore EFLAGS */
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Ke386RestoreFlags(EFlags);
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__writeeflags(EFlags);
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}
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ULONG
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@@ -389,35 +392,19 @@ KiGetCacheInformation(VOID)
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VOID
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FASTCALL
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Ki386InitializeTss(IN PKTSS64 Tss,
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IN PVOID GdtBase,
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IN UINT64 Stack)
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KiInitializeTss(IN PKTSS64 Tss,
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IN UINT64 Stack)
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{
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PKGDTENTRY64 TssEntry;
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/* Initialize the TSS descriptor entry */
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TssEntry = (PVOID)((ULONG64)GdtBase + KGDT_TSS);
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TssEntry->Bits.Type = 9;//AMD64_TSS;
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TssEntry->Bits.Dpl = 0;
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TssEntry->Bits.Present = 1;
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TssEntry->Bits.System = 0;
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TssEntry->Bits.LongMode = 0;
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TssEntry->Bits.DefaultBig = 0;
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TssEntry->Bits.Granularity = 0;
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TssEntry->MustBeZero = 0;
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/* Get pointer to the GDT entry */
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TssEntry = KiGetGdtEntry(KeGetPcr()->GdtBase, KGDT_TSS);
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/* Descriptor base is the TSS address */
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TssEntry->BaseLow = (ULONG64)Tss & 0xffff;
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TssEntry->Bits.BaseMiddle = ((ULONG64)Tss >> 16) & 0xff;
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TssEntry->Bits.BaseHigh = ((ULONG64)Tss >> 24) & 0xff;
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TssEntry->BaseUpper = (ULONG64)Tss >> 32;
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/* Set the limit */
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TssEntry->LimitLow = sizeof(KTSS64) -1;
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TssEntry->Bits.LimitHigh = 0;
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/* Initialize the GDT entry */
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KiInitGdtEntry(TssEntry, (ULONG64)Tss, sizeof(KTSS64), AMD64_TSS, 0);
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/* Zero out the TSS */
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RtlZeroMemory(Tss, sizeof(KTSS));
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RtlZeroMemory(Tss, sizeof(KTSS64));
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/* FIXME: I/O Map? */
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Tss->IoMapBase = 0x68;
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@@ -435,8 +422,7 @@ Ki386InitializeTss(IN PKTSS64 Tss,
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Tss->Ist[3] = (ULONG64)KiDoubleFaultStack;
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/* Load the task register */
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Ke386SetTr(KGDT_TSS);
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__ltr(KGDT_TSS);
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}
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VOID
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@@ -535,7 +521,19 @@ NTAPI
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KeFlushEntireTb(IN BOOLEAN Invalid,
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IN BOOLEAN AllProcessors)
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{
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UNIMPLEMENTED;
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KIRQL OldIrql;
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// FIXME: halfplemented
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/* Raise the IRQL for the TB Flush */
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OldIrql = KeRaiseIrqlToSynchLevel();
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/* Flush the TB for the Current CPU, and update the flush stamp */
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KeFlushCurrentTb();
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/* Update the flush stamp and return to original IRQL */
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InterlockedExchangeAdd(&KiTbFlushTimeStamp, 1);
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KeLowerIrql(OldIrql);
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}
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KAFFINITY
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@@ -337,7 +337,7 @@ KiInitializePcr(IN PKIPCR Pcr,
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IN PVOID DpcStack)
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{
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KDESCRIPTOR GdtDescriptor = {{0},0,0}, IdtDescriptor = {{0},0,0};
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KGDTENTRY64 TssSelector;
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PKGDTENTRY64 TssEntry;
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USHORT Tr = 0;
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/* Zero out the PCR */
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@@ -375,19 +375,16 @@ KiInitializePcr(IN PKIPCR Pcr,
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Pcr->IdtBase = (PKIDTENTRY)IdtDescriptor.Base;
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/* Get TSS Selector */
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Ke386GetTr(Tr); // <- FIXME: this is ugly!
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if (Tr != KGDT_TSS) Tr = KGDT_TSS; // FIXME: HACKHACK
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__str(&Tr);
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ASSERT(Tr == KGDT_TSS);
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/* Get TSS Selector, mask it and get its GDT Entry */
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TssSelector = *(PKGDTENTRY)((ULONG_PTR)Pcr->GdtBase + (Tr & ~RPL_MASK));
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/* Get TSS Entry */
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TssEntry = KiGetGdtEntry(Pcr->GdtBase, Tr);
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/* Get the KTSS itself */
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Pcr->TssBase = (PKTSS)(ULONG_PTR)(TssSelector.BaseLow |
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TssSelector.Bytes.BaseMiddle << 16 |
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TssSelector.Bytes.BaseHigh << 24 |
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(ULONG64)TssSelector.BaseUpper << 32);
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Pcr->TssBase = KiGetGdtDescriptorBase(TssEntry);
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Pcr->Prcb.RspBase = Pcr->TssBase->Rsp0;
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Pcr->Prcb.RspBase = Pcr->TssBase->Rsp0; // FIXME
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/* Set DPC Stack */
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Pcr->Prcb.DpcStack = DpcStack;
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@@ -403,7 +400,7 @@ KiInitializePcr(IN PKIPCR Pcr,
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Pcr->Prcb.CurrentThread = IdleThread;
|
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/* Start us out at PASSIVE_LEVEL */
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// Pcr->Irql = PASSIVE_LEVEL;
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Pcr->Irql = PASSIVE_LEVEL;
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KeSetCurrentIrql(PASSIVE_LEVEL);
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}
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@@ -627,6 +624,9 @@ KiSystemStartup(IN ULONG_PTR Dummy,
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FrLdrDbgPrint = ((PLOADER_PARAMETER_BLOCK)Dummy)->u.I386.CommonDataArea;
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FrLdrDbgPrint("Hello from KiSystemStartup!!!\n");
|
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/* HACK, because freeldr maps page 0 */
|
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MiAddressToPte((PVOID)0)->u.Hard.Valid = 0;
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KiSystemStartupReal((PLOADER_PARAMETER_BLOCK)Dummy);
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// KiRosPrepareForSystemStartup(Dummy, LoaderBlock);
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@@ -699,7 +699,7 @@ KiSystemStartupReal(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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if (Cpu == 0)
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{
|
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/* Setup the TSS descriptors and entries */
|
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Ki386InitializeTss(Pcr->TssBase, Pcr->GdtBase, InitialStack);
|
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KiInitializeTss(Pcr->TssBase, InitialStack);
|
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/* Setup the IDT */
|
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KeInitExceptions();
|
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@@ -711,7 +711,7 @@ KiSystemStartupReal(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
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KdInitSystem(0, KeLoaderBlock);
|
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|
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/* Check for break-in */
|
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// if (KdPollBreakIn()) DbgBreakPointWithStatus(1);
|
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if (KdPollBreakIn()) DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C);
|
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/* Hack! Wait for the debugger! */
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while (!KdPollBreakIn());
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@@ -728,7 +728,7 @@ KiSystemStartupReal(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
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// DPRINT1("Gdt = %p, Idt = %p, Pcr = %p, Tss = %p\n", Gdt, Idt, Pcr, Tss);
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DbgBreakPointWithStatus(0);
|
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DbgBreakPointWithStatus(DBG_STATUS_CONTROL_C);
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/* Initialize the Processor with HAL */
|
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HalInitializeProcessor(Cpu, KeLoaderBlock);
|
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@@ -19,7 +19,7 @@ _MsgUnimplemented:
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.asciz "WARNING: %s at %s:%d is UNIMPLEMENTED!\n"
|
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|
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_MsgPageFault:
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.ascii "Page fault 0x%x at %p!\n\0"
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.ascii "Page fault! Code = 0x%x, RIP = %p, FaultingAddress = %p\n\0"
|
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_MsgGeneralProtFault:
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.ascii "General protection fault at %p!\n\0"
|
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@@ -333,9 +333,9 @@ KiDebugTrapOrFaultKMode:
|
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|
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ENTER_TRAP_FRAME (0x28), TRAPFLAG_ALL
|
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lea rcx, _MsgBreakpointTrap[rip]
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mov rdx, rbp
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call _FrLdrDbgPrint[rip]
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// lea rcx, _MsgBreakpointTrap[rip]
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// mov rdx, rsp
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// call _FrLdrDbgPrint[rip]
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||||
/* Dispatch the exception */
|
||||
mov ecx, STATUS_BREAKPOINT
|
||||
@@ -495,23 +495,25 @@ KiDebugTrapOrFaultKMode:
|
||||
.pushframe 1
|
||||
/* We have an error code */
|
||||
|
||||
// lea rcx, _MsgPageFault[rip]
|
||||
// mov rdx, [rsp]
|
||||
// mov r8, [rsp+8]
|
||||
// mov r9, rsp
|
||||
// call _FrLdrDbgPrint[rip]
|
||||
|
||||
ENTER_TRAP_FRAME (0x28), TRAPFLAG_ALL
|
||||
|
||||
#if 0
|
||||
lea rcx, _MsgPageFault[rip]
|
||||
mov rdx, [rbp + KTRAP_FRAME_ErrorCode]
|
||||
mov r8, [rbp + KTRAP_FRAME_Rip]
|
||||
mov r9, [rbp + KTRAP_FRAME_FaultAddress]
|
||||
call _FrLdrDbgPrint[rip]
|
||||
#endif
|
||||
|
||||
/* Save page fault address */
|
||||
mov rdx, cr2
|
||||
mov [rbp + KTRAP_FRAME_FaultAddress], rdx
|
||||
|
||||
/* Call page fault handler */
|
||||
mov ecx, [ebp + KTRAP_FRAME_ErrorCode] // StoreInstruction
|
||||
mov ecx, [rbp + KTRAP_FRAME_ErrorCode] // StoreInstruction
|
||||
and ecx, 1
|
||||
// rdx == Address
|
||||
mov r8b, [ebp + KTRAP_FRAME_SegCs] // Mode
|
||||
mov r8b, [rbp + KTRAP_FRAME_SegCs] // Mode
|
||||
and r8b, 1
|
||||
mov r9, rbp // TrapInformation
|
||||
// call _MmAccessFault
|
||||
@@ -524,7 +526,7 @@ KiDebugTrapOrFaultKMode:
|
||||
jge PageFaultReturn
|
||||
|
||||
/* Set parameter 1 to error code */
|
||||
mov r9d, [ebp + KTRAP_FRAME_ErrorCode]
|
||||
mov r9d, [rbp + KTRAP_FRAME_ErrorCode]
|
||||
|
||||
/* Set parameter2 to faulting address */
|
||||
mov r10, cr2 // Param2 = faulting address
|
||||
|
||||
+251
-166
@@ -15,9 +15,7 @@
|
||||
|
||||
#include "../ARM3/miarm.h"
|
||||
|
||||
#define MI_SESSION_SPACE_END (PVOID)0xFFFFF98000000000ULL
|
||||
#define MI_SESSION_VIEW_END 0xFFFFF97FFF000000ULL
|
||||
#define MI_NON_PAGED_SYSTEM_START_MIN 0x0FFFFFAA000000000ULL
|
||||
extern PMMPTE MmDebugPte;
|
||||
|
||||
/* GLOBALS *****************************************************************/
|
||||
|
||||
@@ -65,10 +63,11 @@ PVOID MmPagedPoolEnd;
|
||||
ULONG64 MmBootImageSize;
|
||||
PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
|
||||
RTL_BITMAP MiPfnBitMap;
|
||||
ULONG MmNumberOfPhysicalPages, MmHighestPhysicalPage, MmLowestPhysicalPage = -1;
|
||||
ULONG MmNumberOfPhysicalPages, MmHighestPhysicalPage, MmLowestPhysicalPage = -1; // FIXME: ULONG64
|
||||
ULONG64 MmNumberOfSystemPtes;
|
||||
PMMPTE MmSystemPagePtes;
|
||||
ULONG64 MxPfnAllocation;
|
||||
ULONG64 MxPfnSizeInBytes;
|
||||
|
||||
PVOID MmSystemCacheStart;
|
||||
PVOID MmSystemCacheEnd;
|
||||
@@ -83,24 +82,59 @@ MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
|
||||
PFN_NUMBER MxFreePageBase;
|
||||
ULONG64 MxFreePageCount = 0;
|
||||
|
||||
ULONG
|
||||
NoDbgPrint(const char *Format, ...)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
MxSetupFreePageList(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
||||
MiEvaluateMemoryDescriptors(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
||||
{
|
||||
PMEMORY_ALLOCATION_DESCRIPTOR MdBlock;
|
||||
PLIST_ENTRY ListEntry;
|
||||
PFN_NUMBER LastPage;
|
||||
|
||||
/* Loop the memory descriptors */
|
||||
for (ListEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
|
||||
ListEntry != &LoaderBlock->MemoryDescriptorListHead;
|
||||
ListEntry = ListEntry->Flink)
|
||||
{
|
||||
/* Get the memory block */
|
||||
/* Get the memory descriptor */
|
||||
MdBlock = CONTAINING_RECORD(ListEntry,
|
||||
MEMORY_ALLOCATION_DESCRIPTOR,
|
||||
ListEntry);
|
||||
|
||||
/* Check if this is free memory */
|
||||
/* Skip pages that are not part of the PFN database */
|
||||
if ((MdBlock->MemoryType == LoaderFirmwarePermanent) ||
|
||||
(MdBlock->MemoryType == LoaderBBTMemory) ||
|
||||
(MdBlock->MemoryType == LoaderHALCachedMemory) ||
|
||||
(MdBlock->MemoryType == LoaderSpecialMemory) ||
|
||||
(MdBlock->MemoryType == LoaderBad))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Add this to the total of pages */
|
||||
MmNumberOfPhysicalPages += MdBlock->PageCount;
|
||||
|
||||
/* Check if this is the new lowest page */
|
||||
if (MdBlock->BasePage < MmLowestPhysicalPage)
|
||||
{
|
||||
/* Update the lowest page */
|
||||
MmLowestPhysicalPage = MdBlock->BasePage;
|
||||
}
|
||||
|
||||
/* Check if this is the new highest page */
|
||||
LastPage = MdBlock->BasePage + MdBlock->PageCount - 1;
|
||||
if (LastPage > MmHighestPhysicalPage)
|
||||
{
|
||||
/* Update the highest page */
|
||||
MmHighestPhysicalPage = LastPage;
|
||||
}
|
||||
|
||||
/* Check if this is currently free memory */
|
||||
if ((MdBlock->MemoryType == LoaderFree) ||
|
||||
(MdBlock->MemoryType == LoaderLoadedProgram) ||
|
||||
(MdBlock->MemoryType == LoaderFirmwareTemporary) ||
|
||||
@@ -142,14 +176,17 @@ MxGetNextPage(IN PFN_NUMBER PageCount)
|
||||
return Pfn;
|
||||
}
|
||||
|
||||
VOID
|
||||
MxMapPage(PVOID Address)
|
||||
PMMPTE
|
||||
NTAPI
|
||||
MxGetPte(PVOID Address)
|
||||
{
|
||||
PMMPTE Pte;
|
||||
MMPTE TmpPte;
|
||||
|
||||
/* Setup template pte */
|
||||
TmpPte.u.Long = 0;
|
||||
TmpPte.u.Hard.Valid = 1;
|
||||
TmpPte.u.Flush.Valid = 1;
|
||||
TmpPte.u.Flush.Write = 1;
|
||||
|
||||
/* Get a pointer to the PXE */
|
||||
Pte = MiAddressToPxe(Address);
|
||||
@@ -180,163 +217,41 @@ MxMapPage(PVOID Address)
|
||||
|
||||
/* Get a pointer to the PTE */
|
||||
Pte = MiAddressToPte(Address);
|
||||
if (!Pte->u.Hard.Valid)
|
||||
{
|
||||
/* It's not valid, map it! */
|
||||
TmpPte.u.Hard.PageFrameNumber = MxGetNextPage(1);
|
||||
*Pte = TmpPte;
|
||||
}
|
||||
return Pte;
|
||||
}
|
||||
|
||||
VOID
|
||||
MxMapPageRange(PVOID Address, ULONG64 PageCount)
|
||||
{
|
||||
ULONG64 i;
|
||||
MMPTE TmpPte, *Pte;
|
||||
|
||||
for (i = 0; i < PageCount; i++)
|
||||
/* Setup template pte */
|
||||
TmpPte.u.Long = 0;
|
||||
TmpPte.u.Flush.Valid = 1;
|
||||
TmpPte.u.Flush.Write = 1;
|
||||
|
||||
while (PageCount--)
|
||||
{
|
||||
MxMapPage(Address);
|
||||
/* Get the PTE for that page */
|
||||
Pte = MxGetPte(Address);
|
||||
ASSERT(Pte->u.Hard.Valid == 0);
|
||||
|
||||
/* Map a physical page */
|
||||
TmpPte.u.Hard.PageFrameNumber = MxGetNextPage(1);
|
||||
*Pte = TmpPte;
|
||||
|
||||
/* Goto next page */
|
||||
Address = (PVOID)((ULONG64)Address + PAGE_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
MiArmIninializeMemoryLayout(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
||||
MiArmConfigureMemorySizes(IN PLOADER_PARAMETER_BLOCK LoaderBloc)
|
||||
{
|
||||
/* Get the size of the boot loader's image allocations */
|
||||
MmBootImageSize = KeLoaderBlock->Extension->LoaderPagesSpanned;
|
||||
MmBootImageSize *= PAGE_SIZE;
|
||||
MmBootImageSize = (MmBootImageSize + (4 * 1024 * 1024) - 1) & ~((4 * 1024 * 1024) - 1);
|
||||
ASSERT((MmBootImageSize % (4 * 1024 * 1024)) == 0);
|
||||
|
||||
MiSessionSpaceEnd = (PVOID)MI_SESSION_SPACE_END;
|
||||
|
||||
/* This is where we will load Win32k.sys and the video driver */
|
||||
MiSessionImageEnd = MiSessionSpaceEnd;
|
||||
MiSessionImageStart = (PVOID)((ULONG_PTR)MiSessionImageEnd -
|
||||
MmSessionImageSize);
|
||||
|
||||
/* The view starts right below the session working set (itself below
|
||||
* the image area) */
|
||||
MiSessionViewEnd = (PVOID)MI_SESSION_VIEW_END;
|
||||
MiSessionViewStart = (PVOID)((ULONG_PTR)MiSessionViewStart -
|
||||
MmSessionViewSize);
|
||||
|
||||
/* Session pool follows */
|
||||
MiSessionPoolEnd = MiSessionViewStart;
|
||||
MiSessionPoolStart = (PVOID)((ULONG_PTR)MiSessionPoolEnd -
|
||||
MmSessionPoolSize);
|
||||
|
||||
/* And it all begins here */
|
||||
MmSessionBase = MiSessionPoolStart;
|
||||
|
||||
// Sanity check that our math is correct
|
||||
//ASSERT((ULONG_PTR)MmSessionBase + MmSessionSize == PTE_BASE);
|
||||
|
||||
/* System view space ends at session space, so now that we know where
|
||||
* this is, we can compute the base address of system view space itself. */
|
||||
MiSystemViewStart = (PVOID)((ULONG_PTR)MmSessionBase -
|
||||
MmSystemViewSize);
|
||||
|
||||
/* Use the default */
|
||||
MmNumberOfSystemPtes = 22000;
|
||||
|
||||
/* FIXME: should start below paged pool */
|
||||
MmPfnDatabase = (PVOID)0xFFFFFD5FC0000000ULL;
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
MiArmInitializePageTable()
|
||||
{
|
||||
ULONG64 PageFrameOffset;
|
||||
PMMPTE StartPte, EndPte;
|
||||
|
||||
/* Set CR3 for the system process */
|
||||
PageFrameOffset = ((PMMPTE)PXE_BASE)->u.Hard.PageFrameNumber << PAGE_SHIFT;
|
||||
PsGetCurrentProcess()->Pcb.DirectoryTableBase[0] = PageFrameOffset;
|
||||
|
||||
/* Clear user mode mappings in PML4 */
|
||||
StartPte = MiAddressToPxe(0);
|
||||
EndPte = MiAddressToPxe(MmSystemRangeStart);
|
||||
RtlZeroMemory(StartPte, (EndPte - StartPte) * sizeof(MMPTE));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
MiArmEvaluateMemoryDescriptors(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
||||
{
|
||||
PMEMORY_ALLOCATION_DESCRIPTOR MdBlock;
|
||||
PLIST_ENTRY ListEntry;
|
||||
PFN_NUMBER BasePage, LastPage, PageCount;
|
||||
|
||||
/* Loop the memory descriptors */
|
||||
for (ListEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
|
||||
ListEntry != &LoaderBlock->MemoryDescriptorListHead;
|
||||
ListEntry = ListEntry->Flink)
|
||||
{
|
||||
/* Get the descriptor */
|
||||
MdBlock = CONTAINING_RECORD(ListEntry,
|
||||
MEMORY_ALLOCATION_DESCRIPTOR,
|
||||
ListEntry);
|
||||
|
||||
/* Skip pages that are not part of the PFN database */
|
||||
if ((MdBlock->MemoryType == LoaderFirmwarePermanent) ||
|
||||
(MdBlock->MemoryType == LoaderBBTMemory) ||
|
||||
(MdBlock->MemoryType == LoaderHALCachedMemory) || // ???
|
||||
(MdBlock->MemoryType == LoaderSpecialMemory))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Check if BURNMEM was used */
|
||||
if (MdBlock->MemoryType != LoaderBad)
|
||||
{
|
||||
/* Count this in the total of pages */
|
||||
MmNumberOfPhysicalPages += MdBlock->PageCount;
|
||||
}
|
||||
|
||||
BasePage = MdBlock->BasePage;
|
||||
LastPage = MdBlock->BasePage + MdBlock->PageCount - 1;
|
||||
|
||||
/* Check if this is the new lowest page */
|
||||
if (BasePage < MmLowestPhysicalPage)
|
||||
{
|
||||
/* Update the lowest page */
|
||||
MmLowestPhysicalPage = BasePage;
|
||||
}
|
||||
|
||||
/* Check if this is the new highest page */
|
||||
if (LastPage > MmHighestPhysicalPage)
|
||||
{
|
||||
/* Update the highest page */
|
||||
MmHighestPhysicalPage = LastPage;
|
||||
}
|
||||
DPRINT1("BasePage = %ld, LastPage = %ld\n", BasePage, LastPage);
|
||||
__debugbreak();
|
||||
/* Map pages for the PFN database */
|
||||
PageCount = PAGE_ROUND_UP(MdBlock->PageCount * sizeof(MMPFN)) / PAGE_SIZE;
|
||||
MxMapPageRange(&MmPfnDatabase[BasePage], PageCount);
|
||||
|
||||
/* Zero out the pages */
|
||||
RtlZeroMemory(&MmPfnDatabase[BasePage], PageCount * PAGE_SIZE);
|
||||
}
|
||||
|
||||
/* Calculate the number of bytes, and then convert to pages */
|
||||
MxPfnAllocation = (MmHighestPhysicalPage + 1) * sizeof(MMPFN);
|
||||
MxPfnAllocation >>= PAGE_SHIFT;
|
||||
MxPfnAllocation++;
|
||||
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
MiArmPrepareNonPagedPool()
|
||||
{
|
||||
PFN_NUMBER PageCount;
|
||||
MmBootImageSize = KeLoaderBlock->Extension->LoaderPagesSpanned * PAGE_SIZE;
|
||||
MmBootImageSize = ROUND_UP(MmBootImageSize, 4 * 1024 * 1024);
|
||||
|
||||
/* Check if this is a machine with less than 256MB of RAM, and no overide */
|
||||
if ((MmNumberOfPhysicalPages <= MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING) &&
|
||||
@@ -396,15 +311,174 @@ MiArmPrepareNonPagedPool()
|
||||
MmMaximumNonPagedPoolInBytes = MI_MAX_NONPAGED_POOL_SIZE;
|
||||
}
|
||||
|
||||
// MmSessionImageSize
|
||||
}
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
MiArmInitializeMemoryLayout(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
||||
{
|
||||
/* Set up session space */
|
||||
MiSessionSpaceEnd = (PVOID)MI_SESSION_SPACE_END;
|
||||
|
||||
/* This is where we will load Win32k.sys and the video driver */
|
||||
MiSessionImageEnd = MiSessionSpaceEnd;
|
||||
MiSessionImageStart = (PVOID)((ULONG_PTR)MiSessionImageEnd -
|
||||
MmSessionImageSize);
|
||||
|
||||
/* The view starts right below the session working set (itself below
|
||||
* the image area) */
|
||||
MiSessionViewEnd = MI_SESSION_VIEW_END;
|
||||
MiSessionViewStart = (PVOID)((ULONG_PTR)MiSessionViewStart -
|
||||
MmSessionViewSize);
|
||||
|
||||
/* Session pool follows */
|
||||
MiSessionPoolEnd = MiSessionViewStart;
|
||||
MiSessionPoolStart = (PVOID)((ULONG_PTR)MiSessionPoolEnd -
|
||||
MmSessionPoolSize);
|
||||
|
||||
/* And it all begins here */
|
||||
MmSessionBase = MiSessionPoolStart;
|
||||
|
||||
/* System view space ends at session space, so now that we know where
|
||||
* this is, we can compute the base address of system view space itself. */
|
||||
MiSystemViewStart = (PVOID)((ULONG_PTR)MmSessionBase -
|
||||
MmSystemViewSize);
|
||||
|
||||
/* Use the default */
|
||||
MmNumberOfSystemPtes = 22000;
|
||||
|
||||
ASSERT(MiSessionViewEnd <= MiSessionImageStart);
|
||||
ASSERT(MmSessionBase <= MiSessionPoolStart);
|
||||
}
|
||||
|
||||
VOID
|
||||
MiArmInitializePageTable()
|
||||
{
|
||||
ULONG64 PageFrameOffset;
|
||||
PMMPTE Pte, StartPte, EndPte;
|
||||
|
||||
/* Get current directory base */
|
||||
PageFrameOffset = ((PMMPTE)PXE_SELFMAP)->u.Hard.PageFrameNumber << PAGE_SHIFT;
|
||||
ASSERT(PageFrameOffset == __readcr3());
|
||||
|
||||
/* Set directory base for the system process */
|
||||
PsGetCurrentProcess()->Pcb.DirectoryTableBase[0] = PageFrameOffset;
|
||||
|
||||
/* HACK: don't use freeldr debug pront anymore */
|
||||
FrLdrDbgPrint = NoDbgPrint;
|
||||
|
||||
#if 1
|
||||
/* Clear user mode mappings in PML4 */
|
||||
StartPte = MiAddressToPxe(0);
|
||||
EndPte = MiAddressToPxe(MmHighestUserAddress);
|
||||
|
||||
for (Pte = StartPte; Pte <= EndPte; Pte++)
|
||||
{
|
||||
/* Zero the pte */
|
||||
Pte->u.Long = 0;
|
||||
}
|
||||
#else
|
||||
/* Clear user mode mappings in PML4 */
|
||||
StartPte = MiAddressToPte(0);
|
||||
EndPte = MiAddressToPte((PVOID)0xa00000);
|
||||
|
||||
for (Pte = StartPte; Pte < EndPte; Pte++)
|
||||
{
|
||||
/* Zero the pte */
|
||||
//Pte->u.Long = 0;
|
||||
}
|
||||
|
||||
/* Flush the TLB */
|
||||
KeFlushCurrentTb();
|
||||
|
||||
// MiAddressToPde(0)->u.Long = 0;
|
||||
// MiAddressToPde((PVOID)0x200000)->u.Long = 0;
|
||||
// MiAddressToPde((PVOID)0x400000)->u.Long = 0;
|
||||
// MiAddressToPde((PVOID)0x600000)->u.Long = 0;
|
||||
// MiAddressToPde((PVOID)0x800000)->u.Long = 0;
|
||||
|
||||
// MiAddressToPpe->u.Long = 0;
|
||||
|
||||
#endif
|
||||
|
||||
/* Flush the TLB */
|
||||
KeFlushCurrentTb();
|
||||
|
||||
/* Setup debug mapping pte */
|
||||
MmDebugPte = MxGetPte(MI_DEBUG_MAPPING);
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
MiArmPreparePfnDatabse(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
|
||||
{
|
||||
PMEMORY_ALLOCATION_DESCRIPTOR MdBlock;
|
||||
PLIST_ENTRY ListEntry;
|
||||
PFN_COUNT PageCount;
|
||||
PVOID PageBase;
|
||||
|
||||
/* The PFN database is at the start of the non paged region */
|
||||
MmPfnDatabase = (PVOID)((ULONG64)MmNonPagedPoolEnd - MmMaximumNonPagedPoolInBytes);
|
||||
|
||||
/* Loop the memory descriptors */
|
||||
for (ListEntry = LoaderBlock->MemoryDescriptorListHead.Flink;
|
||||
ListEntry != &LoaderBlock->MemoryDescriptorListHead;
|
||||
ListEntry = ListEntry->Flink)
|
||||
{
|
||||
/* Get the memory descriptor */
|
||||
MdBlock = CONTAINING_RECORD(ListEntry,
|
||||
MEMORY_ALLOCATION_DESCRIPTOR,
|
||||
ListEntry);
|
||||
|
||||
/* Skip pages that are not part of the PFN database */
|
||||
if ((MdBlock->MemoryType == LoaderFirmwarePermanent) ||
|
||||
(MdBlock->MemoryType == LoaderBBTMemory) ||
|
||||
(MdBlock->MemoryType == LoaderHALCachedMemory) ||
|
||||
(MdBlock->MemoryType == LoaderSpecialMemory) ||
|
||||
(MdBlock->MemoryType != LoaderBad))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Map pages for the PFN database */
|
||||
PageCount = ROUND_TO_PAGES(MdBlock->PageCount * sizeof(MMPFN)) / PAGE_SIZE;
|
||||
PageBase = PAGE_ALIGN(&MmPfnDatabase[MdBlock->BasePage]);
|
||||
MxMapPageRange(PageBase, PageCount);
|
||||
|
||||
/* Zero out the pages */
|
||||
RtlZeroMemory(PageBase, PageCount * PAGE_SIZE);
|
||||
}
|
||||
|
||||
/* Calculate the number of bytes, and then convert to pages */
|
||||
MxPfnSizeInBytes = ROUND_TO_PAGES(MmHighestPhysicalPage + 1) * sizeof(MMPFN);
|
||||
MxPfnAllocation = MxPfnSizeInBytes >> PAGE_SHIFT;
|
||||
|
||||
/* Reduce maximum pool size */
|
||||
MmMaximumNonPagedPoolInBytes -= MxPfnSizeInBytes;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
NTAPI
|
||||
MiArmPrepareNonPagedPool()
|
||||
{
|
||||
PFN_NUMBER PageCount;
|
||||
PVOID Address;
|
||||
|
||||
/* Non paged pool comes after the PFN database */
|
||||
MmNonPagedPoolStart = (PVOID)((ULONG64)MmPfnDatabase +
|
||||
MxPfnSizeInBytes);
|
||||
ASSERT((ULONG64)MmNonPagedPoolEnd == (ULONG64)MmNonPagedPoolStart +
|
||||
MmMaximumNonPagedPoolInBytes);
|
||||
|
||||
/* Calculate the nonpaged pool expansion start region */
|
||||
MmNonPagedPoolExpansionStart = (PVOID)((ULONG_PTR)MmNonPagedPoolEnd -
|
||||
MmMaximumNonPagedPoolInBytes +
|
||||
MmSizeOfNonPagedPoolInBytes);
|
||||
MmNonPagedPoolExpansionStart = (PVOID)PAGE_ALIGN(MmNonPagedPoolExpansionStart);
|
||||
|
||||
DPRINT("NP Pool has been tuned to: %d bytes and %d bytes\n",
|
||||
MmSizeOfNonPagedPoolInBytes, MmMaximumNonPagedPoolInBytes);
|
||||
|
||||
/* Now calculate the nonpaged system VA region, which includes the
|
||||
* nonpaged pool expansion (above) and the system PTEs. Note that it is
|
||||
* then aligned to a PDE boundary (4MB). */
|
||||
@@ -427,15 +501,21 @@ MiArmPrepareNonPagedPool()
|
||||
ASSERT(MmNumberOfSystemPtes > 1000);
|
||||
}
|
||||
|
||||
/* Non paged pool comes after the PFN database */
|
||||
MmNonPagedPoolStart = (PVOID)((ULONG_PTR)MmPfnDatabase +
|
||||
(MxPfnAllocation << PAGE_SHIFT));
|
||||
|
||||
/* Map the nonpaged pool */
|
||||
PageCount = (MmSizeOfNonPagedPoolInBytes + PAGE_SIZE - 1) / PAGE_SIZE;
|
||||
MxMapPageRange(MmNonPagedPoolStart, PageCount);
|
||||
|
||||
/* Sanity check: make sure we have properly defined the system PTE space */
|
||||
/* Create PTEs for the paged pool extension */
|
||||
for (Address = MmNonPagedPoolExpansionStart;
|
||||
Address < MmNonPagedPoolEnd;
|
||||
Address = (PVOID)((ULONG64)Address + PAGE_SIZE))
|
||||
{
|
||||
/* Create PXE, PPE, PDE and set PTE to 0*/
|
||||
MxGetPte(Address)->u.Long = 0;
|
||||
}
|
||||
|
||||
//DPRINT1("MmNonPagedPoolStart = %p, Pte=%p \n", MmNonPagedPoolStart, MiAddressToPte(MmNonPagedPoolStart));
|
||||
/* Sanity check */
|
||||
ASSERT(MiAddressToPte(MmNonPagedSystemStart) <
|
||||
MiAddressToPte(MmNonPagedPoolExpansionStart));
|
||||
|
||||
@@ -448,18 +528,22 @@ MmArmInitSystem(IN ULONG Phase,
|
||||
{
|
||||
if (Phase == 0)
|
||||
{
|
||||
/* Get a continuous range of physical pages */
|
||||
MxSetupFreePageList(LoaderBlock);
|
||||
/* Parse memory descriptors */
|
||||
MiEvaluateMemoryDescriptors(LoaderBlock);
|
||||
|
||||
/* Configure the memory sizes */
|
||||
MiArmConfigureMemorySizes(LoaderBlock);
|
||||
|
||||
/* Initialize the memory layout */
|
||||
MiArmIninializeMemoryLayout(LoaderBlock);
|
||||
MiArmInitializeMemoryLayout(LoaderBlock);
|
||||
|
||||
/* Loop descriptors and prepare PFN database */
|
||||
MiArmEvaluateMemoryDescriptors(LoaderBlock);
|
||||
/* Prepare PFN database mappings */
|
||||
MiArmPreparePfnDatabse(LoaderBlock);
|
||||
|
||||
/* Initialize some mappings */
|
||||
MiArmInitializePageTable();
|
||||
|
||||
/* Configure size of the non paged pool */
|
||||
/* Prepare paged pool mappings */
|
||||
MiArmPrepareNonPagedPool();
|
||||
|
||||
/* Initialize the ARM3 nonpaged pool */
|
||||
@@ -476,6 +560,7 @@ MmArmInitSystem(IN ULONG Phase,
|
||||
/* The PFN database was created, restore the free descriptor */
|
||||
*MxFreeDescriptor = MxOldFreeDescriptor;
|
||||
|
||||
ASSERT(FALSE);
|
||||
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user