mirror of
https://github.com/ApfelTeeSaft/reactos.git
synced 2026-08-29 19:26:33 +00:00
- Implement ARM3 page fault handling.
- Paged pool PTEs are demand zero PTEs while the memory hasn't been accessed -- this is the only type of fault supported. - Because paged pool PDEs are also demand-paged, added code to handle demand paging of PDEs as well. - Also, because paged pool is non-resident, but can be accessed from any process, we need a mechanism to sync up the kernel's page directory with the per-process one, on demand. This is done at startup, but other processes may have paged in paged pool that another process knows nothing about when he faults. - Similar to the hack ReactOS Mm uses, but done properly. - This is what that shadow system page directory is finally being used for. - Assert if we get a user-mode fault, a transition fault, or a soft fault, since these shouldn't happen. - Disable APCs while dispatching faults, and pseudo-use the working set lock. - Assert if we get write errors on read-only pages, since we don't use those in ARM3 yet. - Assert if we have a paged out PTE, this shouldn't happen yet. - Enable test to see if we can touch a paged pool allocation. svn path=/trunk/; revision=43507
This commit is contained in:
ReactOS Portable Systems Group
@@ -0,0 +1,391 @@
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/*
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* PROJECT: ReactOS Kernel
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* LICENSE: BSD - See COPYING.ARM in the top level directory
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* FILE: ntoskrnl/mm/ARM3/pagfault.c
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* PURPOSE: ARM Memory Manager Page Fault Handling
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* PROGRAMMERS: ReactOS Portable Systems Group
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*/
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/* INCLUDES *******************************************************************/
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#include <ntoskrnl.h>
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#define NDEBUG
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#include <debug.h>
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#line 15 "ARM³::PAGFAULT"
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#define MODULE_INVOLVED_IN_ARM3
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#include "../ARM3/miarm.h"
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/* GLOBALS ********************************************************************/
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/* PRIVATE FUNCTIONS **********************************************************/
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NTSTATUS
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FASTCALL
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MiCheckPdeForPagedPool(IN PVOID Address)
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{
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PMMPTE PointerPde;
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NTSTATUS Status = STATUS_SUCCESS;
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//
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// Check if this is a fault while trying to access the page table itself
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//
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if ((Address >= (PVOID)MiAddressToPte(MmSystemRangeStart)) &&
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(Address < (PVOID)PTE_TOP))
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{
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//
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// Send a hint to the page fault handler that this is only a valid fault
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// if we already detected this was access within the page table range
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//
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PointerPde = MiAddressToPte(Address);
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Status = STATUS_WAIT_1;
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}
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else if (Address < MmSystemRangeStart)
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{
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//
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// This is totally illegal
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//
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return STATUS_ACCESS_VIOLATION;
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}
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else
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{
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//
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// Get the PDE for the address
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//
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PointerPde = MiAddressToPde(Address);
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}
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//
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// Check if it's not valid
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//
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if (PointerPde->u.Hard.Valid == 0)
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{
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//
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// Copy it from our double-mapped system page directory
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//
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InterlockedExchangePte(PointerPde,
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MmSystemPagePtes[((ULONG_PTR)PointerPde &
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(PAGE_SIZE - 1)) /
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sizeof(MMPTE)].u.Long);
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}
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//
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// Return status
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//
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return Status;
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}
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NTSTATUS
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NTAPI
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MiResolveDemandZeroFault(IN PVOID Address,
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IN PMMPTE PointerPte,
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IN PEPROCESS Process,
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IN KIRQL OldIrql)
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{
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PFN_NUMBER PageFrameNumber;
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MMPTE TempPte;
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DPRINT("ARM3 Demand Zero Page Fault Handler for address: %p in process: %p\n",
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Address,
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Process);
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//
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// Lock the PFN database
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//
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OldIrql = KeAcquireQueuedSpinLock(LockQueuePfnLock);
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ASSERT(PointerPte->u.Hard.Valid == 0);
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//
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// Get a page
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//
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PageFrameNumber = MmAllocPage(MC_PPOOL, 0);
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DPRINT("New pool page: %lx\n", PageFrameNumber);
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//
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// Release PFN lock
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//
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KeReleaseQueuedSpinLock(LockQueuePfnLock, OldIrql);
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//
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// Increment demand zero faults
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//
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InterlockedIncrement(&KeGetCurrentPrcb()->MmDemandZeroCount);
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//
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// Build the PTE
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//
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TempPte = HyperTemplatePte;
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TempPte.u.Hard.PageFrameNumber = PageFrameNumber;
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*PointerPte = TempPte;
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ASSERT(PointerPte->u.Hard.Valid == 1);
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//
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// It's all good now
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//
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DPRINT("Paged pool page has now been paged in\n");
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return STATUS_PAGE_FAULT_DEMAND_ZERO;
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}
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NTSTATUS
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NTAPI
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MiDispatchFault(IN BOOLEAN StoreInstruction,
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IN PVOID Address,
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IN PMMPTE PointerPte,
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IN PMMPTE PrototypePte,
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IN BOOLEAN Recursive,
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IN PEPROCESS Process,
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IN PVOID TrapInformation,
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IN PVOID Vad)
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{
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MMPTE TempPte;
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KIRQL OldIrql;
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NTSTATUS Status;
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DPRINT("ARM3 Page Fault Dispatcher for address: %p in process: %p\n",
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Address,
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Process);
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//
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// Make sure APCs are off and we're not at dispatch
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//
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OldIrql = KeGetCurrentIrql ();
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ASSERT(OldIrql <= APC_LEVEL);
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ASSERT(KeAreAllApcsDisabled () == TRUE);
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//
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// Grab a copy of the PTE
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//
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TempPte = *PointerPte;
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//
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// The PTE must be invalid, but not totally blank
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//
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ASSERT(TempPte.u.Hard.Valid == 0);
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ASSERT(TempPte.u.Long != 0);
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//
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// No prototype, transition or page file software PTEs in ARM3 yet
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//
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ASSERT(TempPte.u.Soft.Prototype == 0);
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ASSERT(TempPte.u.Soft.Transition == 0);
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ASSERT(TempPte.u.Soft.PageFileHigh == 0);
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//
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// If we got this far, the PTE can only be a demand zero PTE, which is what
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// we want. Go handle it!
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//
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Status = MiResolveDemandZeroFault(Address,
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PointerPte,
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Process,
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-1);
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if (NT_SUCCESS(Status))
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{
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//
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// Make sure we're returning in a sane state and pass the status down
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//
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ASSERT(OldIrql == KeGetCurrentIrql ());
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ASSERT(KeGetCurrentIrql() <= APC_LEVEL);
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return Status;
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}
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//
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// Generate an access fault
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//
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return STATUS_ACCESS_VIOLATION;
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}
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NTSTATUS
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NTAPI
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MmArmAccessFault(IN BOOLEAN StoreInstruction,
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IN PVOID Address,
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IN KPROCESSOR_MODE Mode,
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IN PVOID TrapInformation)
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{
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KIRQL OldIrql = KeGetCurrentIrql(), LockIrql;
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PMMPTE PointerPde, PointerPte;
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MMPTE TempPte;
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PETHREAD CurrentThread;
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NTSTATUS Status;
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DPRINT("ARM3 FAULT AT: %p\n", Address);
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//
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// Get the PTE and PDE
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//
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PointerPte = MiAddressToPte(Address);
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PointerPde = MiAddressToPde(Address);
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//
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// Check for dispatch-level snafu
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//
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if (OldIrql > APC_LEVEL)
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{
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//
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// There are some special cases where this is okay, but not in ARM3 yet
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//
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DbgPrint("MM:***PAGE FAULT AT IRQL > 1 Va %p, IRQL %lx\n",
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Address,
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OldIrql);
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ASSERT(OldIrql <= APC_LEVEL);
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}
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//
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// Check for kernel fault
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//
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if (Address >= MmSystemRangeStart)
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{
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//
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// What are you even DOING here?
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//
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if (Mode == UserMode) return STATUS_ACCESS_VIOLATION;
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//
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// Is the PDE valid?
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//
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if (!PointerPde->u.Hard.Valid == 0)
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{
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//
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// Debug spew (eww!)
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//
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DPRINT("Invalid PDE\n");
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//
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// Handle mapping in "Special" PDE directoreis
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//
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MiCheckPdeForPagedPool(Address);
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//
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// Now we SHOULD be good
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//
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if (PointerPde->u.Hard.Valid == 0)
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{
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//
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// FIXFIX: Do the S-LIST hack
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//
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//
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// Kill the system
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//
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KeBugCheckEx(PAGE_FAULT_IN_NONPAGED_AREA,
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(ULONG_PTR)Address,
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StoreInstruction,
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(ULONG_PTR)TrapInformation,
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2);
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}
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}
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//
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// The PDE is valid, so read the PTE
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//
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TempPte = *PointerPte;
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if (TempPte.u.Hard.Valid == 1)
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{
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//
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// Only two things can go wrong here:
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// Executing NX page (we couldn't care less)
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// Writing to a read-only page (the stuff ARM3 works with is write,
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// so again, moot point).
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//
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if (StoreInstruction)
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{
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DPRINT1("Should NEVER happen on ARM3!!!\n");
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return STATUS_ACCESS_VIOLATION;
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}
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//
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// Otherwise, the PDE was probably invalid, and all is good now
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//
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return STATUS_SUCCESS;
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}
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//
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// Check for a fault on the page table or hyperspace itself
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// FIXME: Use MmHyperSpaceEnd
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//
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if ((Address >= (PVOID)PTE_BASE) && (Address <= (PVOID)0xC0800000))
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{
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//
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// This might happen...not sure yet
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//
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DPRINT1("FAULT ON PAGE TABLES!\n");
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return STATUS_ACCESS_VIOLATION;
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}
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//
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// Now we must raise to APC_LEVEL and mark the thread as owner
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// We don't actually implement a working set pushlock, so this is only
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// for internal consistency (and blocking APCs)
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//
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KeRaiseIrql(APC_LEVEL, &LockIrql);
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CurrentThread = PsGetCurrentThread();
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KeEnterGuardedRegion();
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ASSERT((CurrentThread->OwnsSystemWorkingSetExclusive == 0) &&
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(CurrentThread->OwnsSystemWorkingSetShared == 0));
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CurrentThread->OwnsSystemWorkingSetExclusive = 1;
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//
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// Re-read PTE now that the IRQL has been raised
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//
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TempPte = *PointerPte;
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if (TempPte.u.Hard.Valid == 1)
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{
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//
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// Only two things can go wrong here:
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// Executing NX page (we couldn't care less)
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// Writing to a read-only page (the stuff ARM3 works with is write,
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// so again, moot point.
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//
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if (StoreInstruction)
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{
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DPRINT1("Should NEVER happen on ARM3!!!\n");
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return STATUS_ACCESS_VIOLATION;
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}
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//
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// Otherwise, the PDE was probably invalid, and all is good now
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//
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return STATUS_SUCCESS;
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}
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//
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// We don't implement prototype PTEs
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//
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ASSERT(TempPte.u.Soft.Prototype == 0);
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//
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// We don't implement transition PTEs
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//
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ASSERT(TempPte.u.Soft.Transition == 0);
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//
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// Now do the real fault handling
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//
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Status = MiDispatchFault(StoreInstruction,
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Address,
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PointerPte,
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NULL,
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FALSE,
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NULL,
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TrapInformation,
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NULL);
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//
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// Re-enable APCs
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//
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ASSERT(KeAreAllApcsDisabled() == TRUE);
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CurrentThread->OwnsSystemWorkingSetExclusive = 0;
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KeLeaveGuardedRegion();
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KeLowerIrql(LockIrql);
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//
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// We are done!
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//
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DPRINT("Fault resolved with status: %lx\n", Status);
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return Status;
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}
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//
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// DIE DIE DIE
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//
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DPRINT1("WARNING: USER MODE FAULT IN ARM3???\n");
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return STATUS_ACCESS_VIOLATION;
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}
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/* EOF */
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@@ -283,9 +283,7 @@ MmAccessFault(IN BOOLEAN StoreInstruction,
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//
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// Hand it off to more competent hands...
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//
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UNIMPLEMENTED;
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KeBugCheckEx(MEMORY_AREA_OWNED_BY_ARM3, Mode, (ULONG_PTR)Address, 0, 0);
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//return MmArmAccessFault(StoreInstruction, Address, Mode, TrapInformation);
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return MmArmAccessFault(StoreInstruction, Address, Mode, TrapInformation);
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}
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/* Keep same old ReactOS Behaviour */
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@@ -403,12 +403,12 @@ MmInitSystem(IN ULONG Phase,
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// STEP 3: Allocate a page and touch it.
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// We should get an ARM3 page fault and it should handle the fault
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//
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if (0) // NOT YET IMPLEMENTED
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if (1)
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{
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PULONG Test;
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Test = MiAllocatePoolPages(PagedPool, PAGE_SIZE);
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DPRINT1("Value: %lx", *Test);
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ASSERT(*Test == 0);
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MiFreePoolPages(Test);
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}
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@@ -392,6 +392,7 @@
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<file>mdlsup.c</file>
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<file>mmsup.c</file>
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<file>ncache.c</file>
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<file>pagfault.c</file>
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<file>pool.c</file>
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<file>procsup.c</file>
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<file>syspte.c</file>
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