mirror of
https://github.com/ApfelTeeSaft/reactos.git
synced 2026-09-01 12:23:29 +00:00
- add BAUDRATE=115000 to boot command line
- Improve the code in wlmemory.c, no real functional change svn path=/branches/ros-amd64-bringup/; revision=44205
This commit is contained in:
@@ -50,7 +50,7 @@ Cabinet=reactos.cab
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[SetupData]
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DefaultPath = \ReactOS
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OsLoadOptions = "/NOGUIBOOT /NODEBUG"
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DbgOsLoadOptions = "/NOGUIBOOT /DEBUGPORT=COM2"
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DbgOsLoadOptions = "/NOGUIBOOT /DEBUGPORT=COM2 /BAUDRATE=115200"
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;OsLoadOptions = "/NOGUIBOOT /DEBUGPORT=SCREEN"
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;OsLoadOptions = "/NOGUIBOOT /DEBUGPORT=BOCHS"
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@@ -15,23 +15,13 @@
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//extern ULONG LoaderPagesSpanned;
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#define HYPER_SPACE_ENTRY 0x300
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// This is needed only for SetProcessorContext routine
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#pragma pack(2)
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typedef struct
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{
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USHORT Limit;
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ULONG Base;
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} GDTIDT;
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#pragma pack(4)
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#define HYPER_SPACE_ENTRY 0x1EE
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/* GLOBALS ***************************************************************/
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//PHARDWARE_PTE PDE;
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PHARDWARE_PTE PxeBase;
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//PHARDWARE_PTE HalPageTable;
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PPAGE_DIRECTORY_AMD64 pPML4;
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/* FUNCTIONS **************************************************************/
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@@ -44,8 +34,8 @@ MempAllocatePageTables()
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DPRINTM(DPRINT_WINDOWS,">>> MempAllocatePageTables\n");
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/* Allocate a page for the PML4 */
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pPML4 = MmAllocateMemoryWithType(PAGE_SIZE, LoaderMemoryData);
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if (!pPML4)
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PxeBase = MmAllocateMemoryWithType(PAGE_SIZE, LoaderMemoryData);
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if (!PxeBase)
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{
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DPRINTM(DPRINT_WINDOWS,"failed to allocate PML4\n");
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return FALSE;
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@@ -54,14 +44,14 @@ MempAllocatePageTables()
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// FIXME: Physical PTEs = FirmwareTemporary ?
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/* Zero the PML4 */
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RtlZeroMemory(pPML4, PAGE_SIZE);
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RtlZeroMemory(PxeBase, PAGE_SIZE);
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/* The page tables are located at 0xfffff68000000000
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* We create a recursive self mapping through all 4 levels at
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* virtual address 0xfffff6fb7dbedf68 */
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pPML4->Pde[VAtoPXI(PXE_BASE)].Valid = 1;
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pPML4->Pde[VAtoPXI(PXE_BASE)].Write = 1;
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pPML4->Pde[VAtoPXI(PXE_BASE)].PageFrameNumber = PtrToPfn(pPML4);
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PxeBase[VAtoPXI(PXE_BASE)].Valid = 1;
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PxeBase[VAtoPXI(PXE_BASE)].Write = 1;
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PxeBase[VAtoPXI(PXE_BASE)].PageFrameNumber = PtrToPfn(PxeBase);
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// FIXME: map PDE's for hals memory mapping
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@@ -70,57 +60,57 @@ MempAllocatePageTables()
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return TRUE;
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}
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PPAGE_DIRECTORY_AMD64
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MempGetOrCreatePageDir(PPAGE_DIRECTORY_AMD64 pDir, ULONG Index)
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PHARDWARE_PTE
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MempGetOrCreatePageDir(PHARDWARE_PTE PdeBase, ULONG Index)
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{
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PPAGE_DIRECTORY_AMD64 pSubDir;
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PHARDWARE_PTE SubDir;
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if (!pDir)
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if (!PdeBase)
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return NULL;
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if (!pDir->Pde[Index].Valid)
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if (!PdeBase[Index].Valid)
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{
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pSubDir = MmAllocateMemoryWithType(PAGE_SIZE, LoaderMemoryData);
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if (!pSubDir)
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SubDir = MmAllocateMemoryWithType(PAGE_SIZE, LoaderMemoryData);
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if (!SubDir)
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return NULL;
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RtlZeroMemory(pSubDir, PAGE_SIZE);
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pDir->Pde[Index].PageFrameNumber = PtrToPfn(pSubDir);
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pDir->Pde[Index].Valid = 1;
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pDir->Pde[Index].Write = 1;
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RtlZeroMemory(SubDir, PAGE_SIZE);
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PdeBase[Index].PageFrameNumber = PtrToPfn(SubDir);
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PdeBase[Index].Valid = 1;
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PdeBase[Index].Write = 1;
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}
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else
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{
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pSubDir = (PPAGE_DIRECTORY_AMD64)((ULONGLONG)(pDir->Pde[Index].PageFrameNumber) * PAGE_SIZE);
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SubDir = (PVOID)((ULONG64)(PdeBase[Index].PageFrameNumber) * PAGE_SIZE);
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}
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return pSubDir;
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return SubDir;
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}
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BOOLEAN
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MempMapSinglePage(ULONG64 VirtualAddress, ULONG64 PhysicalAddress)
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{
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PPAGE_DIRECTORY_AMD64 pDir3, pDir2, pDir1;
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PHARDWARE_PTE PpeBase, PdeBase, PteBase;
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ULONG Index;
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pDir3 = MempGetOrCreatePageDir(pPML4, VAtoPXI(VirtualAddress));
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pDir2 = MempGetOrCreatePageDir(pDir3, VAtoPPI(VirtualAddress));
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pDir1 = MempGetOrCreatePageDir(pDir2, VAtoPDI(VirtualAddress));
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PpeBase = MempGetOrCreatePageDir(PxeBase, VAtoPXI(VirtualAddress));
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PdeBase = MempGetOrCreatePageDir(PpeBase, VAtoPPI(VirtualAddress));
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PteBase = MempGetOrCreatePageDir(PdeBase, VAtoPDI(VirtualAddress));
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if (!pDir1)
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if (!PteBase)
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{
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DPRINTM(DPRINT_WINDOWS,"!!!No Dir %p, %p, %p, %p\n", pPML4, pDir3, pDir2, pDir1);
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DPRINTM(DPRINT_WINDOWS,"!!!No Dir %p, %p, %p, %p\n", PxeBase, PpeBase, PdeBase, PteBase);
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return FALSE;
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}
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Index = VAtoPTI(VirtualAddress);
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if (pDir1->Pde[Index].Valid)
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if (PteBase[Index].Valid)
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{
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DPRINTM(DPRINT_WINDOWS,"!!!Already mapped %ld\n", Index);
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return FALSE;
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}
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pDir1->Pde[Index].Valid = 1;
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pDir1->Pde[Index].Write = 1;
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pDir1->Pde[Index].PageFrameNumber = PhysicalAddress / PAGE_SIZE;
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PteBase[Index].Valid = 1;
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PteBase[Index].Write = 1;
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PteBase[Index].PageFrameNumber = PhysicalAddress / PAGE_SIZE;
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return TRUE;
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}
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@@ -128,34 +118,33 @@ MempMapSinglePage(ULONG64 VirtualAddress, ULONG64 PhysicalAddress)
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BOOLEAN
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MempIsPageMapped(PVOID VirtualAddress)
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{
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PPAGE_DIRECTORY_AMD64 pDir;
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PHARDWARE_PTE PpeBase, PdeBase, PteBase;
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ULONG Index;
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pDir = pPML4;
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Index = VAtoPXI(VirtualAddress);
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if (!pDir->Pde[Index].Valid)
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if (!PxeBase[Index].Valid)
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return FALSE;
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pDir = (PPAGE_DIRECTORY_AMD64)((ULONG64)(pDir->Pde[Index].PageFrameNumber) * PAGE_SIZE);
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PpeBase = (PVOID)((ULONG64)(PxeBase[Index].PageFrameNumber) * PAGE_SIZE);
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Index = VAtoPPI(VirtualAddress);
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if (!pDir->Pde[Index].Valid)
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if (!PpeBase[Index].Valid)
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return FALSE;
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pDir = (PPAGE_DIRECTORY_AMD64)((ULONG64)(pDir->Pde[Index].PageFrameNumber) * PAGE_SIZE);
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PdeBase = (PVOID)((ULONG64)(PpeBase[Index].PageFrameNumber) * PAGE_SIZE);
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Index = VAtoPDI(VirtualAddress);
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if (!pDir->Pde[Index].Valid)
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if (!PdeBase[Index].Valid)
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return FALSE;
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pDir = (PPAGE_DIRECTORY_AMD64)((ULONG64)(pDir->Pde[Index].PageFrameNumber) * PAGE_SIZE);
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PteBase = (PVOID)((ULONG64)(PdeBase[Index].PageFrameNumber) * PAGE_SIZE);
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Index = VAtoPTI(VirtualAddress);
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if (!pDir->Pde[Index].Valid)
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if (!PteBase[Index].Valid)
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return FALSE;
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return TRUE;
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}
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ULONG
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MempMapRangeOfPages(ULONGLONG VirtualAddress, ULONGLONG PhysicalAddress, ULONG cPages)
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MempMapRangeOfPages(ULONG64 VirtualAddress, ULONG64 PhysicalAddress, ULONG cPages)
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{
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ULONG i;
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@@ -333,10 +322,10 @@ WinLdrSetProcessorContext(PVOID GdtIdt, IN ULONG64 Pcr, IN ULONG64 Tss)
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__writeeflags(0);
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/* Set the new PML4 */
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__writecr3((ULONGLONG)pPML4);
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__writecr3((ULONG64)PxeBase);
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/* Get kernel mode address of gdt / idt */
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GdtIdt = (PVOID)((LONG64)GdtIdt + KSEG0_BASE);
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GdtIdt = (PVOID)((ULONG64)GdtIdt + KSEG0_BASE);
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/* Create gdt entries and load gdtr */
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WinLdrSetupGdt(GdtIdt, Tss);
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