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We now have the ARM defines/structures in stubs.c in FreeLDR in more appropriate kernel headers. This is just cleanup work.

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svn path=/trunk/; revision=32310
This commit is contained in:
ReactOS Portable Systems Group
2008-02-12 04:15:53 +00:00
parent 40ecc5259a
commit 41af47163d
5 changed files with 241 additions and 219 deletions
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reactos/boot/freeldr/freeldr/arch/arm/stubs.c
+7 -209
View File
@@ -9,184 +9,12 @@
/* INCLUDES *******************************************************************/
#include <freeldr.h>
#include <internal/arm/ke.h>
#include <internal/arm/mm.h>
#include <internal/arm/intrin_i.h>
/* GLOBALS ********************************************************************/
typedef union _ARM_PTE
{
union
{
struct
{
ULONG Type:2;
ULONG Unused:30;
} Fault;
struct
{
ULONG Type:2;
ULONG Reserved:3;
ULONG Domain:4;
ULONG Ignored:1;
ULONG BaseAddress:22;
} Coarse;
struct
{
ULONG Type:2;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Reserved:1;
ULONG Domain:4;
ULONG Ignored:1;
ULONG Access:2;
ULONG Ignored1:8;
ULONG BaseAddress:12;
} Section;
struct
{
ULONG Type:2;
ULONG Reserved:3;
ULONG Domain:4;
ULONG Ignored:3;
ULONG BaseAddress:20;
} Fine;
} L1;
union
{
struct
{
ULONG Type:2;
ULONG Unused:30;
} Fault;
struct
{
ULONG Type:2;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Access0:2;
ULONG Access1:2;
ULONG Access2:2;
ULONG Access3:2;
ULONG Ignored:4;
ULONG BaseAddress:16;
} Large;
struct
{
ULONG Type:2;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Access0:2;
ULONG Access1:2;
ULONG Access2:2;
ULONG Access3:2;
ULONG BaseAddress:20;
} Small;
struct
{
ULONG Type:2;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Access0:2;
ULONG Ignored:4;
ULONG BaseAddress:22;
} Tiny;
} L2;
ULONG AsUlong;
} ARM_PTE, *PARM_PTE;
typedef struct _ARM_TRANSLATION_TABLE
{
ARM_PTE Pte[4096];
} ARM_TRANSLATION_TABLE, *PARM_TRANSLATION_TABLE;
typedef union _ARM_TTB_REGISTER
{
struct
{
ULONG Reserved:14;
ULONG BaseAddress:18;
};
ULONG AsUlong;
} ARM_TTB_REGISTER;
typedef enum _ARM_L1_PTE_TYPE
{
FaultPte,
CoarsePte,
SectionPte,
FinePte
} ARM_L1_PTE_TYPE;
typedef enum _ARM_PTE_ACCESS
{
FaultAccess,
SupervisorAccess,
SharedAccess,
UserAccess
} ARM_PTE_ACCESS;
typedef enum _ARM_DOMAIN
{
FaultDomain,
ClientDomain,
InvalidDomain,
ManagerDomain
} ARM_DOMAIN;
typedef union _ARM_DOMAIN_REGISTER
{
struct
{
ULONG Domain0:2;
ULONG Domain1:2;
ULONG Domain2:2;
ULONG Domain3:2;
ULONG Domain4:2;
ULONG Domain5:2;
ULONG Domain6:2;
ULONG Domain7:2;
ULONG Domain8:2;
ULONG Domain9:2;
ULONG Domain10:2;
ULONG Domain11:2;
ULONG Domain12:2;
ULONG Domain13:2;
ULONG Domain14:2;
ULONG Domain15:2;
};
ULONG AsUlong;
} ARM_DOMAIN_REGISTER;
typedef union _ARM_CONTROL_REGISTER
{
struct
{
ULONG MmuEnabled:1;
ULONG AlignmentFaultsEnabled:1;
ULONG DCacheEnabled:1;
ULONG Sbo:3;
ULONG BigEndianEnabled:1;
ULONG System:1;
ULONG Rom:1;
ULONG Sbz:2;
ULONG ICacheEnabled:1;
ULONG HighVectors:1;
ULONG RoundRobinReplacementEnabled:1;
ULONG Armv4Compat:1;
ULONG Sbo1:1;
ULONG Sbz1:1;
ULONG Sbo2:1;
ULONG Reserved:14;
};
ULONG AsUlong;
} ARM_CONTROL_REGISTER, *PARM_CONTROL_REGISTER;
typedef enum _ARM_DOMAINS
{
Domain0
} ARM_DOMAINS;
#define TTB_SHIFT 20
ULONG PageDirectoryStart, PageDirectoryEnd;
LOADER_PARAMETER_BLOCK ArmLoaderBlock;
LOADER_PARAMETER_EXTENSION ArmExtension;
@@ -220,36 +48,6 @@ ArmDiskGetCacheableBlockCount(IN ULONG DriveNumber)
return FALSE;
}
ARM_CONTROL_REGISTER
FORCEINLINE
ArmControlRegisterGet(VOID)
{
ARM_CONTROL_REGISTER Value;
__asm__ __volatile__ ("mrc p15, 0, %0, c1, c0, 0" : "=r"(Value.AsUlong) : : "cc");
return Value;
}
VOID
FORCEINLINE
ArmControlRegisterSet(IN ARM_CONTROL_REGISTER ControlRegister)
{
__asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ControlRegister.AsUlong) : "cc");
}
VOID
FORCEINLINE
ArmMmuTtbSet(IN ARM_TTB_REGISTER Ttb)
{
__asm__ __volatile__ ("mcr p15, 0, %0, c2, c0, 0" : : "r"(Ttb.AsUlong) : "cc");
}
VOID
FORCEINLINE
ArmMmuDomainRegisterSet(IN ARM_DOMAIN_REGISTER DomainRegister)
{
__asm__ __volatile__ ("mcr p15, 0, %0, c3, c0, 0" : : "r"(DomainRegister.AsUlong) : "cc");
}
VOID
ArmSetupPageDirectory(VOID)
{
@@ -272,14 +70,14 @@ ArmSetupPageDirectory(VOID)
//
TtbRegister.AsUlong = (ULONG)TranslationTable;
ASSERT(TtbRegister.Reserved == 0);
ArmMmuTtbSet(TtbRegister);
KeArmTranslationTableRegisterSet(TtbRegister);
//
// Use Domain 0, enforce AP bits (client)
//
DomainRegister.AsUlong = 0;
DomainRegister.Domain0 = ClientDomain;
ArmMmuDomainRegisterSet(DomainRegister);
KeArmDomainRegisterSet(DomainRegister);
//
// Set Fault PTEs everywhere
@@ -327,11 +125,11 @@ ArmSetupPagingAndJump(IN ULONG Magic)
//
// Enable MMU, DCache and ICache
//
ControlRegister = ArmControlRegisterGet();
ControlRegister = KeArmControlRegisterGet();
ControlRegister.MmuEnabled = TRUE;
ControlRegister.ICacheEnabled = TRUE;
ControlRegister.DCacheEnabled = TRUE;
ArmControlRegisterSet(ControlRegister);
KeArmControlRegisterSet(ControlRegister);
//
// Jump to Kernel
reactos/ntoskrnl/include/internal/arm/intrin_i.h
+35 -8
View File
@@ -1,18 +1,45 @@
#ifndef _INTRIN_INTERNAL_
#define _INTRIN_INTERNAL_
static __inline__ __attribute__((always_inline)) void KeArchHaltProcessor(void)
FORCEINLINE
VOID
KeArmHaltProcessor(void)
{
//
// Enter Wait-For-Interrupt Mode
//
__asm__ __volatile__
(
"mov r1, #0;"
"mcr p15, 0, r1, c7, c0, 4;"
);
__asm__ __volatile__ ("mcr p15, 0, %0, c7, c0, 4" : : "r"(0) : "cc");
}
#endif
FORCEINLINE
ARM_CONTROL_REGISTER
KeArmControlRegisterGet(VOID)
{
ARM_CONTROL_REGISTER Value;
__asm__ __volatile__ ("mrc p15, 0, %0, c1, c0, 0" : "=r"(Value.AsUlong) : : "cc");
return Value;
}
/* EOF */
FORCEINLINE
VOID
KeArmControlRegisterSet(IN ARM_CONTROL_REGISTER ControlRegister)
{
__asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ControlRegister.AsUlong) : "cc");
}
FORCEINLINE
VOID
KeArmTranslationTableRegisterSet(IN ARM_TTB_REGISTER Ttb)
{
__asm__ __volatile__ ("mcr p15, 0, %0, c2, c0, 0" : : "r"(Ttb.AsUlong) : "cc");
}
FORCEINLINE
VOID
KeArmDomainRegisterSet(IN ARM_DOMAIN_REGISTER DomainRegister)
{
__asm__ __volatile__ ("mcr p15, 0, %0, c3, c0, 0" : : "r"(DomainRegister.AsUlong) : "cc");
}
#define KeArchHaltProcessor KeArmHaltProcessor
#endif
reactos/ntoskrnl/include/internal/arm/ke.h
+79 -1
View File
@@ -5,6 +5,84 @@
#pragma GCC system_header
#endif
typedef union _ARM_TTB_REGISTER
{
struct
{
ULONG Reserved:14;
ULONG BaseAddress:18;
};
ULONG AsUlong;
} ARM_TTB_REGISTER;
typedef union _ARM_DOMAIN_REGISTER
{
struct
{
ULONG Domain0:2;
ULONG Domain1:2;
ULONG Domain2:2;
ULONG Domain3:2;
ULONG Domain4:2;
ULONG Domain5:2;
ULONG Domain6:2;
ULONG Domain7:2;
ULONG Domain8:2;
ULONG Domain9:2;
ULONG Domain10:2;
ULONG Domain11:2;
ULONG Domain12:2;
ULONG Domain13:2;
ULONG Domain14:2;
ULONG Domain15:2;
};
ULONG AsUlong;
} ARM_DOMAIN_REGISTER;
typedef union _ARM_CONTROL_REGISTER
{
struct
{
ULONG MmuEnabled:1;
ULONG AlignmentFaultsEnabled:1;
ULONG DCacheEnabled:1;
ULONG Sbo:3;
ULONG BigEndianEnabled:1;
ULONG System:1;
ULONG Rom:1;
ULONG Sbz:2;
ULONG ICacheEnabled:1;
ULONG HighVectors:1;
ULONG RoundRobinReplacementEnabled:1;
ULONG Armv4Compat:1;
ULONG Sbo1:1;
ULONG Sbz1:1;
ULONG Sbo2:1;
ULONG Reserved:14;
};
ULONG AsUlong;
} ARM_CONTROL_REGISTER, *PARM_CONTROL_REGISTER;
typedef enum _ARM_DOMAINS
{
Domain0,
Domain1,
Domain2,
Domain3,
Domain4,
Domain5,
Domain6,
Domain7,
Domain8,
Domain9,
Domain10,
Domain11,
Domain12,
Domain13,
Domain14,
Domain15
} ARM_DOMAINS;
VOID
NTAPI
KeArmInitThreadWithContext(
@@ -17,4 +95,4 @@ KeArmInitThreadWithContext(
#define KeArchInitThreadWithContext KeArmInitThreadWithContext
#endif
#endif
reactos/ntoskrnl/include/internal/arm/mm.h
+119
View File
@@ -1 +1,120 @@
#ifndef __NTOSKRNL_INCLUDE_INTERNAL_ARM_MM_H
#define __NTOSKRNL_INCLUDE_INTERNAL_ARM_MM_H
#if __GNUC__ >=3
#pragma GCC system_header
#endif
#define TTB_SHIFT 20
typedef union _ARM_PTE
{
union
{
struct
{
ULONG Type:2;
ULONG Unused:30;
} Fault;
struct
{
ULONG Type:2;
ULONG Reserved:3;
ULONG Domain:4;
ULONG Ignored:1;
ULONG BaseAddress:22;
} Coarse;
struct
{
ULONG Type:2;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Reserved:1;
ULONG Domain:4;
ULONG Ignored:1;
ULONG Access:2;
ULONG Ignored1:8;
ULONG BaseAddress:12;
} Section;
struct
{
ULONG Type:2;
ULONG Reserved:3;
ULONG Domain:4;
ULONG Ignored:3;
ULONG BaseAddress:20;
} Fine;
} L1;
union
{
struct
{
ULONG Type:2;
ULONG Unused:30;
} Fault;
struct
{
ULONG Type:2;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Access0:2;
ULONG Access1:2;
ULONG Access2:2;
ULONG Access3:2;
ULONG Ignored:4;
ULONG BaseAddress:16;
} Large;
struct
{
ULONG Type:2;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Access0:2;
ULONG Access1:2;
ULONG Access2:2;
ULONG Access3:2;
ULONG BaseAddress:20;
} Small;
struct
{
ULONG Type:2;
ULONG Buffered:1;
ULONG Cached:1;
ULONG Access0:2;
ULONG Ignored:4;
ULONG BaseAddress:22;
} Tiny;
} L2;
ULONG AsUlong;
} ARM_PTE, *PARM_PTE;
typedef struct _ARM_TRANSLATION_TABLE
{
ARM_PTE Pte[4096];
} ARM_TRANSLATION_TABLE, *PARM_TRANSLATION_TABLE;
typedef enum _ARM_L1_PTE_TYPE
{
FaultPte,
CoarsePte,
SectionPte,
FinePte
} ARM_L1_PTE_TYPE;
typedef enum _ARM_PTE_ACCESS
{
FaultAccess,
SupervisorAccess,
SharedAccess,
UserAccess
} ARM_PTE_ACCESS;
typedef enum _ARM_DOMAIN
{
FaultDomain,
ClientDomain,
InvalidDomain,
ManagerDomain
} ARM_DOMAIN;
#endif
reactos/ntoskrnl/include/internal/ntoskrnl.h
+1 -1
View File
@@ -22,7 +22,6 @@
#undef PsGetCurrentProcess
#define PsGetCurrentProcess _PsGetCurrentProcess
#include "arch/intrin_i.h"
#include "ke.h"
#include "i386/mm.h"
#include "i386/fpu.h"
@@ -54,6 +53,7 @@
#include "inbv.h"
#include "vdm.h"
#include "hal.h"
#include "arch/intrin_i.h"
//
// We are very lazy on ARM -- we just import intrinsics