mirror of
https://github.com/ApfelTeeSaft/reactos.git
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[RTL8139]
- Fix receive stalling if more than 10 packets are in the receive window - Tune configuration to use larger DMA transfers and begin DMA earlier svn path=/trunk/; revision=59429
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@@ -78,7 +78,6 @@ MiniportHandleInterrupt (
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)
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{
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PRTL_ADAPTER adapter = (PRTL_ADAPTER)MiniportAdapterContext;
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ULONG i;
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ULONG txStatus;
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UCHAR command;
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PPACKET_HEADER nicHeader;
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@@ -146,7 +145,7 @@ MiniportHandleInterrupt (
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//
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if (adapter->InterruptPending & (R_I_RXOK | R_I_RXERR))
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{
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for (i = 0; i < MAX_RECEIVES_PER_INT; i++)
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for (;;)
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{
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NdisRawReadPortUchar(adapter->IoBase + R_CMD, &command);
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if (command & R_CMD_RXEMPTY)
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@@ -200,6 +199,15 @@ MiniportHandleInterrupt (
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adapter->ReceiveOffset += nicHeader->PacketLength + sizeof(PACKET_HEADER);
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adapter->ReceiveOffset = (adapter->ReceiveOffset + 3) & ~3;
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NdisRawWritePortUshort(adapter->IoBase + R_CAPR, adapter->ReceiveOffset - 0x10);
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if (adapter->InterruptPending & (R_I_RXOVRFLW | R_I_FIFOOVR))
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{
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//
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// We can only clear these interrupts once CAPR has been reset
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//
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NdisRawWritePortUshort(adapter->IoBase + R_IS, R_I_RXOVRFLW | R_I_FIFOOVR);
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adapter->InterruptPending &= ~(R_I_RXOVRFLW | R_I_FIFOOVR);
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}
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}
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NdisMEthIndicateReceiveComplete(adapter->MiniportAdapterHandle);
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@@ -12,9 +12,8 @@
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#define RESOURCE_LIST_TAG 'Rltr'
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#define MAX_RESET_ATTEMPTS 25
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#define MAX_RECEIVES_PER_INT 10
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#define RECEIVE_BUFFER_SIZE (32768)
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#define FULL_RECEIVE_BUFFER_SIZE (32768 + 16 + 2048)
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#define RECEIVE_BUFFER_SIZE (65536)
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#define FULL_RECEIVE_BUFFER_SIZE (65536 + 16 + 2048)
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#define RECV_CRC_LENGTH 4
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#define MINIMUM_FRAME_SIZE 60
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@@ -22,11 +21,11 @@
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#define DRIVER_VERSION 1
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// 32K RX buffer, 512 byte DMA bursts
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#define RC_VAL (0x0001680)
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// 1/2 packet early RX, 512 byte FIFO threshold, 64K RX buffer, unlimited DMA bursts, WRAP
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#define RC_VAL (0x800BF80)
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// 1024 byte DMA bursts
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#define TC_VAL (0x600)
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// 2048 byte DMA bursts
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#define TC_VAL (0x700)
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typedef struct _RTL_ADAPTER {
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NDIS_HANDLE MiniportAdapterHandle;
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