[FAST486]

- Only flush the TLB when needed.
- Flush the TLB after a reset.


svn path=/trunk/; revision=67698

reactos/lib/fast486/common.c

@@ -834,7 +834,7 @@ Fast486TaskSwitch(PFAST486_STATE State, FAST486_TASK_SWITCH_TYPE Type, USHORT Se
     }
 
     /* Flush the TLB */
-    if (State->Tlb) RtlFillMemory(State->Tlb, NUM_TLB_ENTRIES * sizeof(ULONG), 0xFF);
+    Fast486FlushTlb(State);
 
     /* Update the CPL */
     if (NewTssLimit >= (sizeof(FAST486_TSS) - 1)) State->Cpl = GET_SEGMENT_RPL(NewTss.Cs);

reactos/lib/fast486/common.inl

@@ -138,12 +138,23 @@ Fast486GetPageTableEntry(PFAST486_STATE State,
     {
         /* Set the TLB entry */
         State->Tlb[VirtualAddress >> 12] = TableEntry.Value;
+        State->TlbEmpty = FALSE;
     }
 
     /* Return the table entry */
     return TableEntry.Value;
 }
 
+FORCEINLINE
+VOID
+FASTCALL
+Fast486FlushTlb(PFAST486_STATE State)
+{
+    if (!State->Tlb || State->TlbEmpty) return;
+    RtlFillMemory(State->Tlb, NUM_TLB_ENTRIES * sizeof(ULONG), 0xFF);
+    State->TlbEmpty = TRUE;
+}
+
 FORCEINLINE
 BOOLEAN
 FASTCALL

reactos/lib/fast486/extraops.c

@@ -640,10 +640,10 @@ FAST486_OPCODE_HANDLER(Fast486ExtOpcodeLoadControlReg)
     State->PrefetchValid = FALSE;
 #endif
 
-    if (State->Tlb && (ModRegRm.Register == (INT)FAST486_REG_CR3))
+    if (ModRegRm.Register == (INT)FAST486_REG_CR3)
     {
         /* Flush the TLB */
-        RtlFillMemory(State->Tlb, NUM_TLB_ENTRIES * sizeof(ULONG), 0xFF);
+        Fast486FlushTlb(State);
     }
 
     /* Load a value to the control register */

reactos/lib/fast486/fast486.c

@@ -284,6 +284,9 @@ Fast486Reset(PFAST486_STATE State)
     State->IntAckCallback   = IntAckCallback;
     State->FpuCallback      = FpuCallback;
     State->Tlb              = Tlb;
+
+    /* Flush the TLB */
+    Fast486FlushTlb(State);
 }
 
 VOID