diff --git a/reactos/include/reactos/arm/peripherals/pl011.h b/reactos/include/reactos/arm/peripherals/pl011.h
index 6fa3cdc1fc9..857eab4e188 100644
--- a/reactos/include/reactos/arm/peripherals/pl011.h
+++ b/reactos/include/reactos/arm/peripherals/pl011.h
@@ -11,7 +11,7 @@
 //
 // UART Registers
 //
-#define UART_BASE                (ULONG_PTR)0xE00F1000 /* HACK: freeldr mapped it here */
+#define UART_BASE                (ULONG_PTR)0x101F1000
 
 #define UART_PL01x_DR            (UART_BASE + 0x00)
 #define UART_PL01x_RSR           (UART_BASE + 0x04)
diff --git a/reactos/include/reactos/arm/peripherals/pl190.h b/reactos/include/reactos/arm/peripherals/pl190.h
index a6e336a6abf..a452f50abae 100644
--- a/reactos/include/reactos/arm/peripherals/pl190.h
+++ b/reactos/include/reactos/arm/peripherals/pl190.h
@@ -11,10 +11,10 @@
 //
 // VIC Registers
 //
-#define VIC_BASE                (ULONG_PTR)0xE0040000 /* HACK: freeldr mapped it here */
+#define VIC_BASE                (ULONG_PTR)0x10140000
 
-#define VIC_INT_STATUS          (VIC_BASE + 0x00)
-#define VIC_INT_ENABLE          (VIC_BASE + 0x10)
-#define VIC_INT_CLEAR           (VIC_BASE + 0x14)
-#define VIC_SOFT_INT            (VIC_BASE + 0x18)
-#define VIC_SOFT_INT_CLEAR      (VIC_BASE + 0x1C)
+#define VIC_INT_STATUS          (PULONG)(VIC_BASE + 0x00)
+#define VIC_INT_ENABLE          (PULONG)(VIC_BASE + 0x10)
+#define VIC_INT_CLEAR           (PULONG)(VIC_BASE + 0x14)
+#define VIC_SOFT_INT            (PULONG)(VIC_BASE + 0x18)
+#define VIC_SOFT_INT_CLEAR      (PULONG)(VIC_BASE + 0x1C)
diff --git a/reactos/include/reactos/arm/peripherals/sp804.h b/reactos/include/reactos/arm/peripherals/sp804.h
index 68acd91b149..44a09b6f34d 100644
--- a/reactos/include/reactos/arm/peripherals/sp804.h
+++ b/reactos/include/reactos/arm/peripherals/sp804.h
@@ -11,7 +11,7 @@
 //
 // Timer Registers
 //
-#define TIMER_BASE(x)            (ULONG_PTR)(0xE00E2000 + (x * 0x1000))  /* HACK: freeldr mapped it here */
+#define TIMER_BASE(x)            (ULONG_PTR)(0x101E2000 + (x * 0x1000))
 #define TIMER0_LOAD              TIMER_BASE(0) + 0x00
 #define TIMER0_VALUE             TIMER_BASE(0) + 0x04
 #define TIMER0_CONTROL           TIMER_BASE(0) + 0x08