diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/beos/Makefile b/reactos/dll/3rdparty/mesa32/src/drivers/beos/Makefile index 1897d6aa3e8..9c7d6affc3b 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/beos/Makefile +++ b/reactos/dll/3rdparty/mesa32/src/drivers/beos/Makefile @@ -179,7 +179,8 @@ $(TOP)/$(LIB_DIR): mkdir $(TOP)/$(LIB_DIR) $(TOP)/$(LIB_DIR)/$(GL_LIB_NAME): $(OBJECTS) $(MESA_MODULES) $(GLU_MODULES) - @$(TOP)/bin/mklib -o $(GL_LIB) -install $(TOP)/$(LIB_DIR) -major $(MESA_MAJOR) -minor $(MESA_MINOR) -patch $(MESA_TINY) \ + @$(TOP)/bin/mklib -o $(GL_LIB) -ldflags '$(LDFLAGS)' -install $(TOP)/$(LIB_DIR) \ + -major $(MESA_MAJOR) -minor $(MESA_MINOR) -patch $(MESA_TINY) \ $(MKLIB_OPTIONS) $(GL_LIB_DEPS) $(OBJECTS) $(MESA_MODULES) $(GLU_MODULES) # $(GLU_OBJECTS): diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/Makefile.template b/reactos/dll/3rdparty/mesa32/src/drivers/dri/Makefile.template index 6f2314ee8cb..9e84dbca469 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/Makefile.template +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/Makefile.template @@ -74,7 +74,7 @@ default: depend symlinks $(LIBNAME) $(TOP)/$(LIB_DIR)/$(LIBNAME) $(LIBNAME): $(OBJECTS) $(MESA_MODULES) $(WINOBJ) Makefile $(TOP)/src/mesa/drivers/dri/Makefile.template - $(TOP)/bin/mklib -noprefix -o $@ \ + $(TOP)/bin/mklib -ldflags '$(LDFLAGS)' -noprefix -o $@ \ $(OBJECTS) $(MESA_MODULES) $(WINOBJ) $(DRI_LIB_DEPS) @@ -100,8 +100,8 @@ clean: install: $(LIBNAME) - $(INSTALL) -d $(DRI_DRIVER_INSTALL_DIR) - $(INSTALL) -m 755 $(LIBNAME) $(DRI_DRIVER_INSTALL_DIR) + $(INSTALL) -d $(DESTDIR)$(DRI_DRIVER_INSTALL_DIR) + $(INSTALL) -m 755 $(LIBNAME) $(DESTDIR)$(DRI_DRIVER_INSTALL_DIR) include depend diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/dri_bufmgr.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/dri_bufmgr.c index eaa4fb09c70..ebeed9a2030 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/dri_bufmgr.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/dri_bufmgr.c @@ -115,7 +115,7 @@ driFenceType(DriFenceObject * fence) unsigned ret; _glthread_LOCK_MUTEX(bmMutex); - ret = fence->fence.flags; + ret = fence->fence.type; _glthread_UNLOCK_MUTEX(bmMutex); return ret; diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/extension_helper.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/extension_helper.h index 49f3ee94e77..f930eee528a 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/extension_helper.h +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/extension_helper.h @@ -1098,10 +1098,11 @@ static const char IsRenderbufferEXT_names[] = ""; #endif -#if defined(need_GL_VERSION_2_0) +#if defined(need_GL_VERSION_2_0) || defined(need_GL_ATI_separate_stencil) static const char StencilOpSeparate_names[] = "iiii\0" /* Parameter signature */ "glStencilOpSeparate\0" + "glStencilOpSeparateATI\0" ""; #endif @@ -4172,6 +4173,13 @@ static const char ActiveStencilFaceEXT_names[] = ""; #endif +#if defined(need_GL_ATI_separate_stencil) +static const char StencilFuncSeparateATI_names[] = + "iiii\0" /* Parameter signature */ + "glStencilFuncSeparateATI\0" + ""; +#endif + #if defined(need_GL_VERSION_2_0) || defined(need_GL_ARB_shader_objects) static const char GetShaderSourceARB_names[] = "iipp\0" /* Parameter signature */ @@ -5175,6 +5183,14 @@ static const struct dri_extension_function GL_ATI_fragment_shader_functions[] = }; #endif +#if defined(need_GL_ATI_separate_stencil) +static const struct dri_extension_function GL_ATI_separate_stencil_functions[] = { + { StencilOpSeparate_names, StencilOpSeparate_remap_index, -1 }, + { StencilFuncSeparateATI_names, StencilFuncSeparateATI_remap_index, -1 }, + { NULL, 0, 0 } +}; +#endif + #if defined(need_GL_EXT_blend_color) static const struct dri_extension_function GL_EXT_blend_color_functions[] = { { BlendColor_names, -1, 336 }, diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/spantmp2.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/spantmp2.h index 50f3cf55816..53f5f846a0b 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/spantmp2.h +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/common/spantmp2.h @@ -114,7 +114,7 @@ do { \ GLuint p = *(volatile GLuint *) GET_PTR(_x, _y); \ __asm__ __volatile__( "bswap %0; rorl $8, %0" \ - : "=r" (p) : "r" (p) ); \ + : "=r" (p) : "0" (p) ); \ ((GLuint *)rgba)[0] = p; \ } while (0) # elif defined( MESA_BIG_ENDIAN ) diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/glcore/Makefile b/reactos/dll/3rdparty/mesa32/src/drivers/dri/glcore/Makefile index a9e96970fae..968190acfc0 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/glcore/Makefile +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/glcore/Makefile @@ -61,7 +61,8 @@ default: depend $(TOP)/$(LIB_DIR)/$(LIBNAME) $(TOP)/$(LIB_DIR)/$(LIBNAME): $(OBJECTS) $(MESA_MODULES) $(WINOBJ) Makefile - CC="$(CC)" CXX="$(CXX)" $(TOP)/bin/mklib -o $(LIBNAME) -noprefix -install $(TOP)/$(LIB_DIR) \ + CC="$(CC)" CXX="$(CXX)" $(TOP)/bin/mklib -o $(LIBNAME) -noprefix \ + -ldflags '$(LDFLAGS)' -install $(TOP)/$(LIB_DIR) \ $(OBJECTS) $(WINLIB) $(LIB_DEPS) $(WINOBJ) $(MESA_MODULES) diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i810/i810screen.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i810/i810screen.c index f64c10a9ae0..f8cf050d7e4 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i810/i810screen.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i810/i810screen.c @@ -288,8 +288,8 @@ i810InitDriver(__DRIscreenPrivate *sPriv) i810Screen->depth.handle, i810Screen->depth.size, (drmAddress *)&i810Screen->depth.map) != 0) { - FREE(i810Screen); drmUnmap(i810Screen->back.map, i810Screen->back.size); + FREE(i810Screen); sPriv->private = NULL; __driUtilMessage("i810InitDriver: drmMap (2) failed"); return GL_FALSE; diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/i915_texstate.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/i915_texstate.c index 9f0c9491b22..a19d4b65840 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/i915_texstate.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/i915_texstate.c @@ -491,12 +491,19 @@ static void i915SetTexImages( i915ContextPtr i915, abort(); } - - if (i915->intel.intelScreen->deviceID == PCI_CHIP_I945_G || - i915->intel.intelScreen->deviceID == PCI_CHIP_I945_GM) - i945LayoutTextureImages( i915, tObj ); - else - i915LayoutTextureImages( i915, tObj ); + switch (i915->intel.intelScreen->deviceID) { + case PCI_CHIP_I945_G: + case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q33_G: + case PCI_CHIP_Q35_G: + i945LayoutTextureImages( i915, tObj ); + break; + default: + i915LayoutTextureImages( i915, tObj ); + break; + } t->Setup[I915_TEXREG_MS3] = (((tObj->Image[0][t->intel.base.firstLevel]->Height - 1) << MS3_HEIGHT_SHIFT) | diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_context.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_context.c index e1e7cdb7233..bb5ce6473e1 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_context.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_context.c @@ -123,6 +123,14 @@ const GLubyte *intelGetString( GLcontext *ctx, GLenum name ) chipset = "Intel(R) 945G"; break; case PCI_CHIP_I945_GM: chipset = "Intel(R) 945GM"; break; + case PCI_CHIP_I945_GME: + chipset = "Intel(R) 945GME"; break; + case PCI_CHIP_G33_G: + chipset = "Intel(R) G33"; break; + case PCI_CHIP_Q35_G: + chipset = "Intel(R) Q35"; break; + case PCI_CHIP_Q33_G: + chipset = "Intel(R) Q33"; break; default: chipset = "Unknown Intel Chipset"; break; } diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_context.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_context.h index 05195e76d65..50e61789002 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_context.h +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_context.h @@ -454,6 +454,10 @@ extern int INTEL_DEBUG; #define PCI_CHIP_I915_GM 0x2592 #define PCI_CHIP_I945_G 0x2772 #define PCI_CHIP_I945_GM 0x27A2 +#define PCI_CHIP_I945_GME 0x27AE +#define PCI_CHIP_G33_G 0x29C2 +#define PCI_CHIP_Q35_G 0x29B2 +#define PCI_CHIP_Q33_G 0x29D2 /* ================================================================ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_screen.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_screen.c index 67e176a1c6f..ca8610b4965 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_screen.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_screen.c @@ -514,6 +514,10 @@ static GLboolean intelCreateContext( const __GLcontextModes *mesaVis, case PCI_CHIP_I915_GM: case PCI_CHIP_I945_G: case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q35_G: + case PCI_CHIP_Q33_G: return i915CreateContext( mesaVis, driContextPriv, sharedContextPrivate ); diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_tex.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_tex.c index 98ddc796724..5bd280652af 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_tex.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915/intel_tex.c @@ -677,7 +677,11 @@ static void intelUploadTexImage( intelContextPtr intel, /* Time for another vtbl entry: */ else if (intel->intelScreen->deviceID == PCI_CHIP_I945_G || - intel->intelScreen->deviceID == PCI_CHIP_I945_GM) { + intel->intelScreen->deviceID == PCI_CHIP_I945_GM || + intel->intelScreen->deviceID == PCI_CHIP_I945_GME || + intel->intelScreen->deviceID == PCI_CHIP_G33_G || + intel->intelScreen->deviceID == PCI_CHIP_Q33_G || + intel->intelScreen->deviceID == PCI_CHIP_Q35_G) { GLuint row_len = image->Width * image->TexFormat->TexelBytes; GLubyte *dst = (GLubyte *)(t->BufAddr + offset); GLubyte *src = (GLubyte *)image->Data; diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i830_vtbl.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i830_vtbl.c index e432648ada0..5555b74668d 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i830_vtbl.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i830_vtbl.c @@ -519,6 +519,16 @@ i830_emit_state(struct intel_context *intel) static void i830_destroy_context(struct intel_context *intel) { + GLuint i; + struct i830_context *i830 = i830_context(&intel->ctx); + + for (i = 0; i < I830_TEX_UNITS; i++) { + if (i830->state.tex_buffer[i] != NULL) { + driBOUnReference(i830->state.tex_buffer[i]); + i830->state.tex_buffer[i] = NULL; + } + } + _tnl_free_vertices(&intel->ctx); } diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_metaops.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_metaops.c index 3ab62bc806b..397ff75b6f1 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_metaops.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_metaops.c @@ -95,7 +95,7 @@ meta_depth_replace(struct intel_context *intel) i915->meta.Ctx[I915_CTXREG_LIS6] |= (S6_DEPTH_TEST_ENABLE | S6_DEPTH_WRITE_ENABLE); - /* ctx->Driver.DepthFunc( ctx, GL_REPLACE ) + /* ctx->Driver.DepthFunc( ctx, GL_ALWAYS ) */ i915->meta.Ctx[I915_CTXREG_LIS6] &= ~S6_DEPTH_TEST_FUNC_MASK; i915->meta.Ctx[I915_CTXREG_LIS6] |= diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_tex_layout.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_tex_layout.c index 9f40706c36a..7b761a7b221 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_tex_layout.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_tex_layout.c @@ -113,7 +113,7 @@ i915_miptree_layout(struct intel_mipmap_tree * mt) */ for (level = mt->first_level; level <= MAX2(8, mt->last_level); level++) { - intel_miptree_set_level_info(mt, level, 1, 0, mt->total_height, + intel_miptree_set_level_info(mt, level, depth, 0, mt->total_height, width, height, depth); diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_vtbl.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_vtbl.c index ad333b490b7..e911fc40084 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_vtbl.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/i915_vtbl.c @@ -430,6 +430,16 @@ i915_emit_state(struct intel_context *intel) static void i915_destroy_context(struct intel_context *intel) { + GLuint i; + struct i915_context *i915 = i915_context(&intel->ctx); + + for (i = 0; i < I915_TEX_UNITS; i++) { + if (i915->state.tex_buffer[i] != NULL) { + driBOUnReference(i915->state.tex_buffer[i]); + i915->state.tex_buffer[i] = NULL; + } + } + _tnl_free_vertices(&intel->ctx); } diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_blit.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_blit.c index dbe4ba2ac5e..a0601515c16 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_blit.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_blit.c @@ -409,6 +409,9 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask) b = *box; } + if (b.x1 >= b.x2 || b.y1 >= b.y2) + continue; + if (0) _mesa_printf("clear %d,%d..%d,%d, mask %x\n", b.x1, b.y1, b.x2, b.y2, mask); diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_buffers.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_buffers.c index 15d02f8e2cf..78fb720b6b9 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_buffers.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_buffers.c @@ -1124,6 +1124,15 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled); } + /* + * Update depth test state + */ + if (ctx->Depth.Test && fb->Visual.depthBits > 0) { + ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_TRUE); + } + else { + ctx->Driver.Enable(ctx, GL_DEPTH_TEST, GL_FALSE); + } /** ** Release old regions, reference new regions diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_context.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_context.c index 093b3b416b4..40ea7564126 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_context.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_context.c @@ -130,6 +130,18 @@ intelGetString(GLcontext * ctx, GLenum name) case PCI_CHIP_I945_GM: chipset = "Intel(R) 945GM"; break; + case PCI_CHIP_I945_GME: + chipset = "Intel(R) 945GME"; + break; + case PCI_CHIP_G33_G: + chipset = "Intel(R) G33"; + break; + case PCI_CHIP_Q35_G: + chipset = "Intel(R) Q35"; + break; + case PCI_CHIP_Q33_G: + chipset = "Intel(R) Q33"; + break; default: chipset = "Unknown Intel Chipset"; break; diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_context.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_context.h index bcbbb127b12..5fc8eb3e382 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_context.h +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_context.h @@ -385,6 +385,10 @@ extern int INTEL_DEBUG; #define PCI_CHIP_I915_GM 0x2592 #define PCI_CHIP_I945_G 0x2772 #define PCI_CHIP_I945_GM 0x27A2 +#define PCI_CHIP_I945_GME 0x27AE +#define PCI_CHIP_G33_G 0x29C2 +#define PCI_CHIP_Q35_G 0x29B2 +#define PCI_CHIP_Q33_G 0x29D2 /* ================================================================ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_mipmap_tree.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_mipmap_tree.c index 8e83028b26c..564eb9e0197 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_mipmap_tree.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_mipmap_tree.c @@ -79,6 +79,10 @@ intel_miptree_create(struct intel_context *intel, switch (intel->intelScreen->deviceID) { case PCI_CHIP_I945_G: case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q33_G: + case PCI_CHIP_Q35_G: ok = i945_miptree_layout(mt); break; case PCI_CHIP_I915_G: @@ -93,9 +97,28 @@ intel_miptree_create(struct intel_context *intel, break; } - if (ok) + if (ok) { + if (!mt->compressed) { + /* XXX: Align pitch to multiple of 64 bytes for now to allow + * render-to-texture to work in all cases. This should probably be + * replaced at some point by some scheme to only do this when really + * necessary. + */ + mt->pitch = (mt->pitch * cpp + 63) & ~63; + + /* XXX: At least the i915 seems very upset when the pitch is a multiple + * of 1024 and sometimes 512 bytes - performance can drop by several + * times. Go to the next multiple of 64 for now. + */ + if (!(mt->pitch & 511)) + mt->pitch += 64; + + mt->pitch /= cpp; + } + mt->region = intel_region_alloc(intel->intelScreen, mt->cpp, mt->pitch, mt->total_height); + } if (!mt->region) { free(mt); diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_screen.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_screen.c index 5e6df81950b..2acdead63d5 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_screen.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i915tex/intel_screen.c @@ -752,6 +752,10 @@ intelCreateContext(const __GLcontextModes * mesaVis, case PCI_CHIP_I915_GM: case PCI_CHIP_I945_G: case PCI_CHIP_I945_GM: + case PCI_CHIP_I945_GME: + case PCI_CHIP_G33_G: + case PCI_CHIP_Q35_G: + case PCI_CHIP_Q33_G: return i915CreateContext(mesaVis, driContextPriv, sharedContextPrivate); default: diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_aub.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_aub.c index f851a5b7955..c549f7a4f60 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_aub.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_aub.c @@ -80,7 +80,7 @@ static void init_aubfile( FILE *aub_file ) fh.hour = (nr>>16) & 0xff; fh.comment_length = 0x0; - if (fwrite(&fh, sizeof(fh), 1, aub_file) < 0) + if (fwrite(&fh, sizeof(fh), 1, aub_file) < 1) FAIL; /* Setup the GTT starting at main memory address zero (!): @@ -96,12 +96,12 @@ static void init_aubfile( FILE *aub_file ) bh.address = PGETBL_CTL; bh.length = 0x4; - if (fwrite(&bh, sizeof(bh), 1, aub_file) < 0) + if (fwrite(&bh, sizeof(bh), 1, aub_file) < 1) FAIL; data = 0x0 | PGETBL_ENABLED; - if (fwrite(&data, sizeof(data), 1, aub_file) < 0) + if (fwrite(&data, sizeof(data), 1, aub_file) < 1) FAIL; } @@ -128,7 +128,7 @@ static void init_aub_gtt( struct brw_context *brw, bh.address = start_offset / 4096 * 4; bh.length = size / 4096 * 4; - if (fwrite(&bh, sizeof(bh), 1, aub_file) < 0) + if (fwrite(&bh, sizeof(bh), 1, aub_file) < 1) FAIL; for (i = 0; i < size / 4096; i++) { @@ -136,7 +136,7 @@ static void init_aub_gtt( struct brw_context *brw, brw->next_free_page += 4096; - if (fwrite(&data, sizeof(data), 1, aub_file) < 0) + if (fwrite(&data, sizeof(data), 1, aub_file) < 1) FAIL; } @@ -149,10 +149,10 @@ static void write_block_header( FILE *aub_file, { sz = (sz + 3) & ~3; - if (fwrite(bh, sizeof(*bh), 1, aub_file) < 0) + if (fwrite(bh, sizeof(*bh), 1, aub_file) < 1) FAIL; - if (fwrite(data, sz, 1, aub_file) < 0) + if (fwrite(data, sz, 1, aub_file) < 1) FAIL; fflush(aub_file); @@ -162,7 +162,7 @@ static void write_block_header( FILE *aub_file, static void write_dump_bmp( FILE *aub_file, struct aub_dump_bmp *db ) { - if (fwrite(db, sizeof(*db), 1, aub_file) < 0) + if (fwrite(db, sizeof(*db), 1, aub_file) < 1) FAIL; fflush(aub_file); diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_clip.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_clip.c index 3bec153075a..8287fd9edf3 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_clip.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_clip.c @@ -212,6 +212,10 @@ static void upload_clip_prog( struct brw_context *brw ) } } + if (brw->attribs.Polygon->BackMode != GL_FILL || + brw->attribs.Polygon->FrontMode != GL_FILL) + key.do_unfilled = 1; + /* Most cases the fixed function units will handle. Cases where * one or more polygon faces are unfilled will require help: */ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_curbe.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_curbe.c index 3f0aaa1f86d..5bf0ed536ba 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_curbe.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_curbe.c @@ -90,7 +90,7 @@ static void calculate_curbe_offsets( struct brw_context *brw ) */ if (nr_fp_regs > brw->curbe.wm_size || nr_vp_regs > brw->curbe.vs_size || - nr_clip_regs > brw->curbe.clip_size || + nr_clip_regs != brw->curbe.clip_size || (total_regs < brw->curbe.total_size / 4 && brw->curbe.total_size > 16)) { diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_draw.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_draw.c index c7798b14a93..f7964727d5d 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_draw.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_draw.c @@ -330,6 +330,7 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, else { /* Otherwise, explicitly do the cliprects at this point: */ + GLuint nprims = 0; for (j = 0; j < brw->intel.numClipRects; j++) { brw_emit_cliprect(brw, &brw->intel.pClipRects[j]); @@ -337,6 +338,11 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, */ for (i = 0; i < nr_prims; i++) { brw_emit_prim(brw, &prim[i]); + + if (++nprims == VBO_MAX_PRIM) { + intel_batchbuffer_flush(brw->intel.batch); + nprims = 0; + } } } } diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_sf_emit.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_sf_emit.c index cbaf018c44a..2ea9816e285 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_sf_emit.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_sf_emit.c @@ -582,7 +582,9 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c ) (1<<_3DPRIM_TRIFAN_NOSTIPPLE))); jmp = brw_JMPI(p, ip, ip, brw_imm_w(0)); { + brw_push_insn_state(p); brw_emit_tri_setup( c ); + brw_pop_insn_state(p); /* note - thread killed in subroutine */ } brw_land_fwd_jump(p, jmp); @@ -596,7 +598,9 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c ) (1<<_3DPRIM_LINESTRIP_CONT_BF))); jmp = brw_JMPI(p, ip, ip, brw_imm_w(0)); { + brw_push_insn_state(p); brw_emit_line_setup( c ); + brw_pop_insn_state(p); /* note - thread killed in subroutine */ } brw_land_fwd_jump(p, jmp); diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_vs_tnl.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_vs_tnl.c index 35adc4846a0..14483b325a9 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_vs_tnl.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_vs_tnl.c @@ -1000,13 +1000,19 @@ static void build_lighting( struct tnl_program *p ) STATE_POSITION); struct ureg V = get_eye_position(p); struct ureg dist = get_temp(p); + struct ureg tmpPpli = get_temp(p); VPpli = get_temp(p); half = get_temp(p); - + + /* In homogeneous object coordinates + */ + emit_op1(p, OPCODE_RCP, dist, 0, swizzle1(Ppli, W)); + emit_op2(p, OPCODE_MUL, tmpPpli, 0, Ppli, dist); + /* Calulate VPpli vector */ - emit_op2(p, OPCODE_SUB, VPpli, 0, Ppli, V); + emit_op2(p, OPCODE_SUB, VPpli, 0, tmpPpli, V); /* Normalize VPpli. The dist value also used in * attenuation below. @@ -1038,6 +1044,7 @@ static void build_lighting( struct tnl_program *p ) emit_normalize_vec3(p, half, half); release_temp(p, dist); + release_temp(p, tmpPpli); } /* Calculate dot products: diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_fp.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_fp.c index ff97d87dc45..dc57fd263c2 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_fp.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_fp.c @@ -525,7 +525,57 @@ static void precalc_tex( struct brw_wm_compile *c, struct prog_src_register coord; struct prog_dst_register tmpcoord; - if (inst->TexSrcTarget == TEXTURE_RECT_INDEX) { + if (inst->TexSrcTarget == TEXTURE_CUBE_INDEX) { + struct prog_instruction *out; + struct prog_dst_register tmp0 = get_temp(c); + struct prog_src_register tmp0src = src_reg_from_dst(tmp0); + struct prog_dst_register tmp1 = get_temp(c); + struct prog_src_register tmp1src = src_reg_from_dst(tmp1); + struct prog_src_register src0 = inst->SrcReg[0]; + + tmpcoord = get_temp(c); + coord = src_reg_from_dst(tmpcoord); + + out = emit_op(c, OPCODE_MOV, + tmpcoord, + 0, 0, 0, + src0, + src_undef(), + src_undef()); + out->SrcReg[0].NegateBase = 0; + out->SrcReg[0].Abs = 1; + + emit_op(c, OPCODE_MAX, + tmp0, + 0, 0, 0, + src_swizzle1(coord, X), + src_swizzle1(coord, Y), + src_undef()); + + emit_op(c, OPCODE_MAX, + tmp1, + 0, 0, 0, + tmp0src, + src_swizzle1(coord, Z), + src_undef()); + + emit_op(c, OPCODE_RCP, + tmp0, + 0, 0, 0, + tmp1src, + src_undef(), + src_undef()); + + emit_op(c, OPCODE_MUL, + tmpcoord, + 0, 0, 0, + src0, + tmp0src, + src_undef()); + + release_temp(c, tmp0); + release_temp(c, tmp1); + } else if (inst->TexSrcTarget == TEXTURE_RECT_INDEX) { struct prog_src_register scale = search_or_add_param5( c, STATE_INTERNAL, diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_sampler_state.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_sampler_state.c index 93d4cfc3a5f..794c7d98169 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_sampler_state.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_sampler_state.c @@ -173,12 +173,12 @@ static void brw_update_sampler_state( struct gl_texture_unit *texUnit, * message (sample_c). So need to recompile WM program when * shadow comparison is enabled on each/any texture unit. */ - sampler->ss0.shadow_function = intel_translate_compare_func(texObj->CompareFunc); + sampler->ss0.shadow_function = intel_translate_shadow_compare_func(texObj->CompareFunc); } /* Set LOD bias: */ - sampler->ss0.lod_bias = S_FIXED(texUnit->LodBias + texObj->LodBias, 6); + sampler->ss0.lod_bias = S_FIXED(CLAMP(texUnit->LodBias + texObj->LodBias, -16, 15), 6); sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ @@ -192,8 +192,8 @@ static void brw_update_sampler_state( struct gl_texture_unit *texUnit, */ sampler->ss0.base_level = U_FIXED(0, 1); - sampler->ss1.max_lod = U_FIXED(MAX2(texObj->MaxLod, 0), 6); - sampler->ss1.min_lod = U_FIXED(MAX2(texObj->MinLod, 0), 6); + sampler->ss1.max_lod = U_FIXED(MIN2(MAX2(texObj->MaxLod, 0), 13), 6); + sampler->ss1.min_lod = U_FIXED(MIN2(MAX2(texObj->MinLod, 0), 13), 6); sampler->ss2.default_color_pointer = sdc_gs_offset >> 5; } diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_state.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_state.c index ff5cb31bdd1..5b4f2abd0e2 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_state.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/brw_wm_state.c @@ -117,7 +117,7 @@ static void upload_wm_unit(struct brw_context *brw ) wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; /* CACHE_NEW_SAMPLER */ - wm.wm4.sampler_count = brw->wm.sampler_count; + wm.wm4.sampler_count = (brw->wm.sampler_count + 1) / 4; wm.wm4.sampler_state_pointer = brw->wm.sampler_gs_offset >> 5; /* BRW_NEW_FRAGMENT_PROGRAM */ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_buffers.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_buffers.c index d155c039d77..de6a867cca4 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_buffers.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_buffers.c @@ -31,7 +31,9 @@ #include "intel_regions.h" #include "intel_batchbuffer.h" #include "context.h" +#include "utils.h" #include "framebuffer.h" +#include "vblank.h" #include "macros.h" #include "swrast/swrast.h" @@ -190,8 +192,40 @@ void intelWindowMoved( struct intel_context *intel ) } } + { + if (intel->intelScreen->driScrnPriv->ddxMinor >= 7) { + volatile drmI830Sarea *sarea = intel->sarea; + drm_clip_rect_t drw_rect = { .x1 = dPriv->x, .x2 = dPriv->x + dPriv->w, + .y1 = dPriv->y, .y2 = dPriv->y + dPriv->h + }; + drm_clip_rect_t pipeA_rect = { .x1 = sarea->pipeA_x, + .x2 = sarea->pipeA_x + sarea->pipeA_w, + .y1 = sarea->pipeA_y, + .y2 = sarea->pipeA_y + sarea->pipeA_h }; + drm_clip_rect_t pipeB_rect = { .x1 = sarea->pipeB_x, + .x2 = sarea->pipeB_x + sarea->pipeB_w, + .y1 = sarea->pipeB_y, + .y2 = sarea->pipeB_y + sarea->pipeB_h }; + GLint areaA = driIntersectArea( drw_rect, pipeA_rect ); + GLint areaB = driIntersectArea( drw_rect, pipeB_rect ); + GLuint flags = intel->vblank_flags; + + if (areaB > areaA || (areaA > 0 && areaB > 0)) { + flags = intel->vblank_flags | VBLANK_FLAG_SECONDARY; + } else { + flags = intel->vblank_flags & ~VBLANK_FLAG_SECONDARY; + } + + if (flags != intel->vblank_flags) { + intel->vblank_flags = flags; + driGetCurrentVBlank(dPriv, intel->vblank_flags, &intel->vbl_seq); + } + } else { + intel->vblank_flags &= ~VBLANK_FLAG_SECONDARY; + } + } _mesa_resize_framebuffer(&intel->ctx, - (GLframebuffer*)dPriv->driverPrivate, + (GLframebuffer*)dPriv->driverPrivate, dPriv->w, dPriv->h); /* Set state we know depends on drawable parameters: diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_context.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_context.c index 10eb9a2e28d..33efed431db 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_context.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_context.c @@ -262,7 +262,7 @@ intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q) }; intel->stats_wm++; intelFinish(&intel->ctx); - drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io)); + drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io)); } static void @@ -276,7 +276,7 @@ intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q) .data = &tmp }; intelFinish(&intel->ctx); - drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io)); + drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io)); q->Result = tmp - q->Result; q->Ready = GL_TRUE; intel->stats_wm--; @@ -487,7 +487,7 @@ GLboolean intelInitContext( struct intel_context *intel, _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); _mesa_enable_extension( ctx, "GL_S3_s3tc" ); } - else if (driQueryOptionb (&intelScreen->optionCache, "force_s3tc_enable")) { + else if (driQueryOptionb (&intel->optionCache, "force_s3tc_enable")) { _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); } @@ -567,6 +567,10 @@ GLboolean intelMakeCurrent(__DRIcontextPrivate *driContextPriv, if (driContextPriv) { struct intel_context *intel = (struct intel_context *) driContextPriv->driverPrivate; + if (intel->driReadDrawable != driReadPriv) { + intel->driReadDrawable = driReadPriv; + } + if ( intel->driDrawable != driDrawPriv ) { /* Shouldn't the readbuffer be stored also? */ driDrawableInitVBlank( driDrawPriv, intel->vblank_flags, diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_context.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_context.h index 808512f7fd5..9f69f23706d 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_context.h +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_context.h @@ -234,6 +234,7 @@ struct intel_context int driFd; __DRIdrawablePrivate *driDrawable; + __DRIdrawablePrivate *driReadDrawable; __DRIscreenPrivate *driScreen; intelScreenPrivate *intelScreen; volatile drmI830Sarea *sarea; @@ -463,7 +464,7 @@ extern void intelInitStateFuncs( struct dd_function_table *functions ); #define BLENDFACT_INV_CONST_ALPHA 0x0f #define BLENDFACT_MASK 0x0f - +extern int intel_translate_shadow_compare_func( GLenum func ); extern int intel_translate_compare_func( GLenum func ); extern int intel_translate_stencil_op( GLenum op ); extern int intel_translate_blend_factor( GLenum factor ); diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_pixel_bitmap.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_pixel_bitmap.c index 421fcc5e511..df9d6885c08 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_pixel_bitmap.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_pixel_bitmap.c @@ -168,12 +168,15 @@ do_blit_bitmap( GLcontext *ctx, { struct intel_context *intel = intel_context(ctx); struct intel_region *dst = intel_drawbuf_region(intel); - + GLfloat tmpColor[4]; + union { GLuint ui; GLubyte ub[4]; } color; + if (!dst) + return GL_FALSE; if (unpack->BufferObj->Name) { bitmap = map_pbo(ctx, width, height, unpack, bitmap); @@ -181,10 +184,16 @@ do_blit_bitmap( GLcontext *ctx, return GL_TRUE; /* even though this is an error, we're done */ } - UNCLAMPED_FLOAT_TO_CHAN(color.ub[0], ctx->Current.RasterColor[2]); - UNCLAMPED_FLOAT_TO_CHAN(color.ub[1], ctx->Current.RasterColor[1]); - UNCLAMPED_FLOAT_TO_CHAN(color.ub[2], ctx->Current.RasterColor[0]); - UNCLAMPED_FLOAT_TO_CHAN(color.ub[3], ctx->Current.RasterColor[3]); + COPY_4V(tmpColor, ctx->Current.RasterColor); + + if (NEED_SECONDARY_COLOR(ctx)) { + ADD_3V(tmpColor, tmpColor, ctx->Current.RasterSecondaryColor); + } + + UNCLAMPED_FLOAT_TO_CHAN(color.ub[0], tmpColor[2]); + UNCLAMPED_FLOAT_TO_CHAN(color.ub[1], tmpColor[1]); + UNCLAMPED_FLOAT_TO_CHAN(color.ub[2], tmpColor[0]); + UNCLAMPED_FLOAT_TO_CHAN(color.ub[3], tmpColor[3]); /* Does zoom apply to bitmaps? */ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_pixel_copy.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_pixel_copy.c index 58dc49505fe..3bdf2fb4790 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_pixel_copy.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_pixel_copy.c @@ -231,6 +231,7 @@ do_blit_copypixels(GLcontext * ctx, if (intel->driDrawable->numClipRects) { __DRIdrawablePrivate *dPriv = intel->driDrawable; + __DRIdrawablePrivate *dReadPriv = intel->driReadDrawable; drm_clip_rect_t *box = dPriv->pClipRects; drm_clip_rect_t dest_rect; GLint nbox = dPriv->numClipRects; @@ -262,8 +263,8 @@ do_blit_copypixels(GLcontext * ctx, srcy = dPriv->h - srcy - height; dstx += dPriv->x; dsty += dPriv->y; - srcx += dPriv->x; - srcy += dPriv->y; + srcx += dReadPriv->x; + srcy += dReadPriv->y; /* Clip against the source region. This is the only source * clipping we do. Dst is clipped with cliprects below. diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_state.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_state.c index ec6e0465d4a..701b30cc91d 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_state.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/intel_state.c @@ -38,6 +38,31 @@ #include "intel_regions.h" #include "swrast/swrast.h" +int intel_translate_shadow_compare_func( GLenum func ) +{ + switch(func) { + case GL_NEVER: + return COMPAREFUNC_ALWAYS; + case GL_LESS: + return COMPAREFUNC_LEQUAL; + case GL_LEQUAL: + return COMPAREFUNC_LESS; + case GL_GREATER: + return COMPAREFUNC_GEQUAL; + case GL_GEQUAL: + return COMPAREFUNC_GREATER; + case GL_NOTEQUAL: + return COMPAREFUNC_EQUAL; + case GL_EQUAL: + return COMPAREFUNC_NOTEQUAL; + case GL_ALWAYS: + return COMPAREFUNC_NEVER; + } + + fprintf(stderr, "Unknown value in %s: %x\n", __FUNCTION__, func); + return COMPAREFUNC_NEVER; +} + int intel_translate_compare_func( GLenum func ) { switch(func) { diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/server/i830_common.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/server/i830_common.h index f320378c2a5..fe2b8e8b5d4 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/server/i830_common.h +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/i965/server/i830_common.h @@ -119,6 +119,16 @@ typedef struct { unsigned int depth_tiled; unsigned int rotated_tiled; unsigned int rotated2_tiled; + + int pipeA_x; + int pipeA_y; + int pipeA_w; + int pipeA_h; + int pipeB_x; + int pipeB_y; + int pipeB_w; + int pipeB_h; + } drmI830Sarea; /* Flags for perf_boxes diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_context.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_context.h index e840a502c0b..a06a2f5bb4e 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_context.h +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_context.h @@ -180,6 +180,7 @@ struct r200_tex_obj { drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; /* Six, for the cube faces */ + GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ GLuint pp_txfilter; /* hardware register values */ GLuint pp_txformat; diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_tex.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_tex.h index 4438cc02a82..68e9a0ed5f0 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_tex.h +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_tex.h @@ -36,6 +36,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef __R200_TEX_H__ #define __R200_TEX_H__ +extern void r200SetTexOffset(__DRIcontext *pDRICtx, GLint texname, + unsigned long long offset, GLint depth, + GLuint pitch); + extern void r200UpdateTextureState( GLcontext *ctx ); extern int r200UploadTexImages( r200ContextPtr rmesa, r200TexObjPtr t, GLuint face ); diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_texmem.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_texmem.c index 28988c97556..9daafcf5937 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_texmem.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_texmem.c @@ -182,7 +182,8 @@ static void r200UploadRectSubImage( r200ContextPtr rmesa, /* In this case, could also use GART texturing. This is * currently disabled, but has been tested & works. */ - t->pp_txoffset = r200GartOffsetFromVirtual( rmesa, texImage->Data ); + if ( !t->image_override ) + t->pp_txoffset = r200GartOffsetFromVirtual( rmesa, texImage->Data ); t->pp_txpitch = texImage->RowStride * texFormat->TexelBytes - 32; if (R200_DEBUG & DEBUG_TEXTURE) @@ -468,7 +469,7 @@ int r200UploadTexImages( r200ContextPtr rmesa, r200TexObjPtr t, GLuint face ) t->base.firstLevel, t->base.lastLevel ); } - if ( !t || t->base.totalSize == 0 ) + if ( !t || t->base.totalSize == 0 || t->image_override ) return 0; if (R200_DEBUG & DEBUG_SYNC) { diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_texstate.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_texstate.c index 875d3bab73f..af5092bb972 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_texstate.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/r200_texstate.c @@ -38,6 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "context.h" #include "macros.h" #include "texformat.h" +#include "texobj.h" #include "enums.h" #include "r200_context.h" @@ -73,10 +74,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \ && (tx_table_le[f].format != 0xffffffff) ) -static const struct { +struct tx_table { GLuint format, filter; -} -tx_table_be[] = +}; + +static const struct tx_table tx_table_be[] = { [ MESA_FORMAT_RGBA8888 ] = { R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, _ALPHA_REV(RGBA8888), @@ -105,16 +107,13 @@ tx_table_be[] = _ALPHA(RGBA_DXT5), }; -static const struct { - GLuint format, filter; -} -tx_table_le[] = +static const struct tx_table tx_table_le[] = { _ALPHA(RGBA8888), [ MESA_FORMAT_RGBA8888_REV ] = { R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, _ALPHA(ARGB8888), _ALPHA_REV(ARGB8888), - _INVALID(RGB888), + [ MESA_FORMAT_RGB888 ] = { R200_TXFORMAT_ARGB8888, 0 }, _COLOR(RGB565), _COLOR_REV(RGB565), _ALPHA(ARGB4444), @@ -161,30 +160,23 @@ static void r200SetTexImages( r200ContextPtr rmesa, GLint i, texelBytes; GLint numLevels; GLint log2Width, log2Height, log2Depth; - const GLuint ui = 1; - const GLubyte littleEndian = *((const GLubyte *) &ui); /* Set the hardware texture format */ + if ( !t->image_override ) { + if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) { + t->pp_txformat &= ~(R200_TXFORMAT_FORMAT_MASK | + R200_TXFORMAT_ALPHA_IN_MAP); + t->pp_txfilter &= ~R200_YUV_TO_RGB; - t->pp_txformat &= ~(R200_TXFORMAT_FORMAT_MASK | - R200_TXFORMAT_ALPHA_IN_MAP); - t->pp_txfilter &= ~R200_YUV_TO_RGB; - - if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) { - if (littleEndian) { t->pp_txformat |= tx_table_le[ baseImage->TexFormat->MesaFormat ].format; t->pp_txfilter |= tx_table_le[ baseImage->TexFormat->MesaFormat ].filter; } else { - t->pp_txformat |= tx_table_be[ baseImage->TexFormat->MesaFormat ].format; - t->pp_txfilter |= tx_table_be[ baseImage->TexFormat->MesaFormat ].filter; + _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); + return; } } - else { - _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); - return; - } texelBytes = baseImage->TexFormat->TexelBytes; @@ -381,11 +373,13 @@ static void r200SetTexImages( r200ContextPtr rmesa, * requires 64-byte aligned pitches, and we may/may not need the * blitter. NPOT only! */ - if (baseImage->IsCompressed) - t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63); - else - t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63); - t->pp_txpitch -= 32; + if ( !t->image_override ) { + if (baseImage->IsCompressed) + t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63); + else + t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63); + t->pp_txpitch -= 32; + } t->dirty_state = TEX_ALL; @@ -980,6 +974,46 @@ static GLboolean r200UpdateTextureEnv( GLcontext *ctx, int unit, int slot, GLuin return GL_TRUE; } +void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname, + unsigned long long offset, GLint depth, GLuint pitch) +{ + r200ContextPtr rmesa = + (r200ContextPtr) ((__DRIcontextPrivate *) pDRICtx->private)-> + driverPrivate; + struct gl_texture_object *tObj = + _mesa_lookup_texture(rmesa->glCtx, texname); + r200TexObjPtr t; + + if (!tObj) + return; + + t = (r200TexObjPtr) tObj->DriverData; + + t->image_override = GL_TRUE; + + if (!offset) + return; + + t->pp_txoffset = offset; + t->pp_txpitch = pitch - 32; + + switch (depth) { + case 32: + t->pp_txformat = tx_table_le[MESA_FORMAT_ARGB8888].format; + t->pp_txfilter |= tx_table_le[MESA_FORMAT_ARGB8888].filter; + break; + case 24: + default: + t->pp_txformat = tx_table_le[MESA_FORMAT_RGB888].format; + t->pp_txfilter |= tx_table_le[MESA_FORMAT_RGB888].filter; + break; + case 16: + t->pp_txformat = tx_table_le[MESA_FORMAT_RGB565].format; + t->pp_txfilter |= tx_table_le[MESA_FORMAT_RGB565].filter; + break; + } +} + #define REF_COLOR 1 #define REF_ALPHA 2 @@ -1561,7 +1595,7 @@ static GLboolean enable_tex_2d( GLcontext *ctx, int unit ) R200_FIREVERTICES( rmesa ); r200SetTexImages( rmesa, tObj ); r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, 0 ); - if ( !t->base.memBlock ) + if ( !t->base.memBlock && !t->image_override ) return GL_FALSE; } @@ -1669,7 +1703,9 @@ static GLboolean enable_tex_rect( GLcontext *ctx, int unit ) R200_FIREVERTICES( rmesa ); r200SetTexImages( rmesa, tObj ); r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, 0 ); - if ( !t->base.memBlock && !rmesa->prefer_gart_client_texturing ) + if ( !t->base.memBlock && + !t->image_override && + !rmesa->prefer_gart_client_texturing ) return GL_FALSE; } diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/radeon_chipset.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/radeon_chipset.h new file mode 100644 index 00000000000..7318099093a --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/radeon_chipset.h @@ -0,0 +1,181 @@ +#ifndef _RADEON_CHIPSET_H +#define _RADEON_CHIPSET_H +/* Including xf86PciInfo.h introduces a bunch of errors... + */ + +/* General chip classes: + * r100 includes R100, RV100, RV200, RS100, RS200, RS250. + * r200 includes R200, RV250, RV280, RS300. + * r300 includes R300, RV350, RV370. + * (RS* denotes IGP) + */ +#define PCI_CHIP_RV380_3150 0x3150 +#define PCI_CHIP_RV380_3152 0x3152 +#define PCI_CHIP_RV380_3154 0x3154 +#define PCI_CHIP_RV380_3E50 0x3E50 +#define PCI_CHIP_RV380_3E54 0x3E54 +#define PCI_CHIP_RS100_4136 0x4136 +#define PCI_CHIP_RS200_4137 0x4137 +#define PCI_CHIP_R300_AD 0x4144 +#define PCI_CHIP_R300_AE 0x4145 +#define PCI_CHIP_R300_AF 0x4146 +#define PCI_CHIP_R300_AG 0x4147 +#define PCI_CHIP_R350_AH 0x4148 +#define PCI_CHIP_R350_AI 0x4149 +#define PCI_CHIP_R350_AJ 0x414A +#define PCI_CHIP_R350_AK 0x414B +#define PCI_CHIP_RV350_AP 0x4150 +#define PCI_CHIP_RV350_AQ 0x4151 +#define PCI_CHIP_RV350_AR 0x4152 +#define PCI_CHIP_RV350_AS 0x4153 +#define PCI_CHIP_RV350_AT 0x4154 +#define PCI_CHIP_RV350_AU 0x4155 +#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_RS250_4237 0x4237 +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_R200_BC 0x4243 +#define PCI_CHIP_RS100_4336 0x4336 +#define PCI_CHIP_RS200_4337 0x4337 +#define PCI_CHIP_RS250_4437 0x4437 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_R420_JH 0x4A48 +#define PCI_CHIP_R420_JI 0x4A49 +#define PCI_CHIP_R420_JJ 0x4A4A +#define PCI_CHIP_R420_JK 0x4A4B +#define PCI_CHIP_R420_JL 0x4A4C +#define PCI_CHIP_R420_JM 0x4A4D +#define PCI_CHIP_R420_JN 0x4A4E +#define PCI_CHIP_R420_JO 0x4A4F +#define PCI_CHIP_R420_JP 0x4A50 +#define PCI_CHIP_R420_JT 0x4A54 +#define PCI_CHIP_R481_4B49 0x4B49 +#define PCI_CHIP_R481_4B4A 0x4B4A +#define PCI_CHIP_R481_4B4B 0x4B4B +#define PCI_CHIP_R481_4B4C 0x4B4C +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_R350_NH 0x4E48 +#define PCI_CHIP_R350_NI 0x4E49 +#define PCI_CHIP_R360_NJ 0x4E4A +#define PCI_CHIP_R350_NK 0x4E4B +#define PCI_CHIP_RV350_NP 0x4E50 +#define PCI_CHIP_RV350_NQ 0x4E51 +#define PCI_CHIP_RV350_NR 0x4E52 +#define PCI_CHIP_RV350_NS 0x4E53 +#define PCI_CHIP_RV350_NT 0x4E54 +#define PCI_CHIP_RV350_NV 0x4E56 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_R200_QH 0x5148 +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QM 0x514D +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RADEON_QY 0x5159 +#define PCI_CHIP_RADEON_QZ 0x515A +#define PCI_CHIP_RN50_515E 0x515E +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV370_5462 0x5462 +#define PCI_CHIP_RV370_5464 0x5464 +#define PCI_CHIP_R423_UH 0x5548 +#define PCI_CHIP_R423_UI 0x5549 +#define PCI_CHIP_R423_UJ 0x554A +#define PCI_CHIP_R423_UK 0x554B +#define PCI_CHIP_R430_554C 0x554C +#define PCI_CHIP_R430_554D 0x554D +#define PCI_CHIP_R430_554E 0x554E +#define PCI_CHIP_R430_554F 0x554F +#define PCI_CHIP_R423_5550 0x5550 +#define PCI_CHIP_R423_UQ 0x5551 +#define PCI_CHIP_R423_UR 0x5552 +#define PCI_CHIP_R423_UT 0x5554 +#define PCI_CHIP_RV410_564A 0x564A +#define PCI_CHIP_RV410_564B 0x564B +#define PCI_CHIP_RV410_564F 0x564F +#define PCI_CHIP_RV410_5652 0x5652 +#define PCI_CHIP_RV410_5653 0x5653 +#define PCI_CHIP_RS300_5834 0x5834 +#define PCI_CHIP_RS300_5835 0x5835 +#define PCI_CHIP_RS480_5954 0x5954 +#define PCI_CHIP_RS480_5955 0x5955 +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5965 0x5965 +#define PCI_CHIP_RN50_5969 0x5969 +#define PCI_CHIP_RS482_5974 0x5974 +#define PCI_CHIP_RS482_5975 0x5975 +#define PCI_CHIP_RS400_5A41 0x5A41 +#define PCI_CHIP_RS400_5A42 0x5A42 +#define PCI_CHIP_RC410_5A61 0x5A61 +#define PCI_CHIP_RC410_5A62 0x5A62 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV370_5B62 0x5B62 +#define PCI_CHIP_RV370_5B63 0x5B63 +#define PCI_CHIP_RV370_5B64 0x5B64 +#define PCI_CHIP_RV370_5B65 0x5B65 +#define PCI_CHIP_RV280_5C61 0x5C61 +#define PCI_CHIP_RV280_5C63 0x5C63 +#define PCI_CHIP_R430_5D48 0x5D48 +#define PCI_CHIP_R430_5D49 0x5D49 +#define PCI_CHIP_R430_5D4A 0x5D4A +#define PCI_CHIP_R480_5D4C 0x5D4C +#define PCI_CHIP_R480_5D4D 0x5D4D +#define PCI_CHIP_R480_5D4E 0x5D4E +#define PCI_CHIP_R480_5D4F 0x5D4F +#define PCI_CHIP_R480_5D50 0x5D50 +#define PCI_CHIP_R480_5D52 0x5D52 +#define PCI_CHIP_R423_5D57 0x5D57 +#define PCI_CHIP_RV410_5E48 0x5E48 +#define PCI_CHIP_RV410_5E4A 0x5E4A +#define PCI_CHIP_RV410_5E4B 0x5E4B +#define PCI_CHIP_RV410_5E4C 0x5E4C +#define PCI_CHIP_RV410_5E4D 0x5E4D +#define PCI_CHIP_RV410_5E4F 0x5E4F +#define PCI_CHIP_RS350_7834 0x7834 +#define PCI_CHIP_RS350_7835 0x7835 + +enum { + CHIP_FAMILY_R100, + CHIP_FAMILY_RV100, + CHIP_FAMILY_RS100, + CHIP_FAMILY_RV200, + CHIP_FAMILY_RS200, + CHIP_FAMILY_R200, + CHIP_FAMILY_RV250, + CHIP_FAMILY_RS300, + CHIP_FAMILY_RV280, + CHIP_FAMILY_R300, + CHIP_FAMILY_R350, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, + CHIP_FAMILY_R420, + CHIP_FAMILY_RV410, + CHIP_FAMILY_RS400, + CHIP_FAMILY_LAST +}; + +/* General classes of Radeons, as described above the device ID section */ +#define RADEON_CLASS_R100 (0 << 0) +#define RADEON_CLASS_R200 (1 << 0) +#define RADEON_CLASS_R300 (2 << 0) +#define RADEON_CLASS_MASK (3 << 0) + +#define RADEON_CHIPSET_TCL (1 << 2) /* tcl support - any radeon */ +#define RADEON_CHIPSET_BROKEN_STENCIL (1 << 3) /* r100 stencil bug */ +#define R200_CHIPSET_YCBCR_BROKEN (1 << 4) /* r200 ycbcr bug */ + +#endif /* _RADEON_CHIPSET_H */ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/radeon_screen.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/radeon_screen.c new file mode 100644 index 00000000000..682cf3a5ee5 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/radeon_screen.c @@ -0,0 +1,1104 @@ +/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and + VA Linux Systems Inc., Fremont, California. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/** + * \file radeon_screen.c + * Screen initialization functions for the Radeon driver. + * + * \author Kevin E. Martin + * \author Gareth Hughes + */ + +#include "glheader.h" +#include "imports.h" +#include "mtypes.h" +#include "framebuffer.h" +#include "renderbuffer.h" + +#define STANDALONE_MMIO +#include "radeon_chipset.h" +#include "radeon_macros.h" +#include "radeon_screen.h" +#if !RADEON_COMMON +#include "radeon_context.h" +#include "radeon_span.h" +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) +#include "r200_context.h" +#include "r200_ioctl.h" +#include "r200_span.h" +#include "r200_tex.h" +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) +#include "r300_context.h" +#include "r300_fragprog.h" +#include "r300_tex.h" +#include "radeon_span.h" +#endif + +#include "utils.h" +#include "context.h" +#include "vblank.h" +#include "drirenderbuffer.h" + +#include "GL/internal/dri_interface.h" + +/* Radeon configuration + */ +#include "xmlpool.h" + +#if !RADEON_COMMON /* R100 */ +PUBLIC const char __driConfigOptions[] = +DRI_CONF_BEGIN + DRI_CONF_SECTION_PERFORMANCE + DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) + DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) + DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) + DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) + DRI_CONF_HYPERZ(false) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_QUALITY + DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) + DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") + DRI_CONF_NO_NEG_LOD_BIAS(false) + DRI_CONF_FORCE_S3TC_ENABLE(false) + DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) + DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) + DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) + DRI_CONF_ALLOW_LARGE_TEXTURES(1) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_DEBUG + DRI_CONF_NO_RAST(false) + DRI_CONF_SECTION_END +DRI_CONF_END; +static const GLuint __driNConfigOptions = 14; + +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + +PUBLIC const char __driConfigOptions[] = +DRI_CONF_BEGIN + DRI_CONF_SECTION_PERFORMANCE + DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) + DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) + DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) + DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) + DRI_CONF_HYPERZ(false) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_QUALITY + DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) + DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") + DRI_CONF_NO_NEG_LOD_BIAS(false) + DRI_CONF_FORCE_S3TC_ENABLE(false) + DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) + DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) + DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) + DRI_CONF_ALLOW_LARGE_TEXTURES(1) + DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") + DRI_CONF_SECTION_END + DRI_CONF_SECTION_DEBUG + DRI_CONF_NO_RAST(false) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_SOFTWARE + DRI_CONF_NV_VERTEX_PROGRAM(false) + DRI_CONF_SECTION_END +DRI_CONF_END; +static const GLuint __driNConfigOptions = 16; + +extern const struct dri_extension blend_extensions[]; +extern const struct dri_extension ARB_vp_extension[]; +extern const struct dri_extension NV_vp_extension[]; +extern const struct dri_extension ATI_fs_extension[]; +extern const struct dri_extension point_extensions[]; + +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + +/* TODO: integrate these into xmlpool.h! */ +#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Number of texture image units") \ + DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ +DRI_CONF_OPT_END + +#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Number of texture coordinate units") \ + DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ +DRI_CONF_OPT_END + +#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ + DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_S3TC(def) \ +DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ + DRI_CONF_DESC(en,"Disable S3TC compression") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_FALLBACK(def) \ +DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ + DRI_CONF_DESC(en,"Disable Low-impact fallback") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ +DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ + DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ +DRI_CONF_OPT_END + +#define DRI_CONF_FP_OPTIMIZATION(def) \ +DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ + DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ + DRI_CONF_ENUM(0,"Optimize for Speed") \ + DRI_CONF_ENUM(1,"Optimize for Quality") \ + DRI_CONF_DESC_END \ +DRI_CONF_OPT_END + +const char __driConfigOptions[] = +DRI_CONF_BEGIN + DRI_CONF_SECTION_PERFORMANCE + DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) + DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) + DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) + DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) + DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) + DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) + DRI_CONF_DISABLE_FALLBACK(false) + DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_QUALITY + DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) + DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") + DRI_CONF_NO_NEG_LOD_BIAS(false) + DRI_CONF_FORCE_S3TC_ENABLE(false) + DRI_CONF_DISABLE_S3TC(false) + DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) + DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) + DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) + DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_DEBUG + DRI_CONF_NO_RAST(false) + DRI_CONF_SECTION_END +DRI_CONF_END; +static const GLuint __driNConfigOptions = 18; + +#ifndef RADEON_DEBUG +int RADEON_DEBUG = 0; + +static const struct dri_debug_control debug_control[] = { + {"fall", DEBUG_FALLBACKS}, + {"tex", DEBUG_TEXTURE}, + {"ioctl", DEBUG_IOCTL}, + {"prim", DEBUG_PRIMS}, + {"vert", DEBUG_VERTS}, + {"state", DEBUG_STATE}, + {"code", DEBUG_CODEGEN}, + {"vfmt", DEBUG_VFMT}, + {"vtxf", DEBUG_VFMT}, + {"verb", DEBUG_VERBOSE}, + {"dri", DEBUG_DRI}, + {"dma", DEBUG_DMA}, + {"san", DEBUG_SANITY}, + {"sync", DEBUG_SYNC}, + {"pix", DEBUG_PIXEL}, + {"mem", DEBUG_MEMORY}, + {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ + {NULL, 0} +}; +#endif /* RADEON_DEBUG */ + +#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ + +extern const struct dri_extension card_extensions[]; + +static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); + +static int +radeonGetParam(int fd, int param, void *value) +{ + int ret; + drm_radeon_getparam_t gp; + + gp.param = param; + gp.value = value; + + ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); + return ret; +} + +static __GLcontextModes * +radeonFillInModes( unsigned pixel_bits, unsigned depth_bits, + unsigned stencil_bits, GLboolean have_back_buffer ) +{ + __GLcontextModes * modes; + __GLcontextModes * m; + unsigned num_modes; + unsigned depth_buffer_factor; + unsigned back_buffer_factor; + GLenum fb_format; + GLenum fb_type; + + /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy + * enough to add support. Basically, if a context is created with an + * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping + * will never be used. + */ + static const GLenum back_buffer_modes[] = { + GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ + }; + + u_int8_t depth_bits_array[2]; + u_int8_t stencil_bits_array[2]; + + + depth_bits_array[0] = depth_bits; + depth_bits_array[1] = depth_bits; + + /* Just like with the accumulation buffer, always provide some modes + * with a stencil buffer. It will be a sw fallback, but some apps won't + * care about that. + */ + stencil_bits_array[0] = 0; + stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; + + depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; + back_buffer_factor = (have_back_buffer) ? 2 : 1; + + num_modes = depth_buffer_factor * back_buffer_factor * 4; + + if ( pixel_bits == 16 ) { + fb_format = GL_RGB; + fb_type = GL_UNSIGNED_SHORT_5_6_5; + } + else { + fb_format = GL_BGRA; + fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; + } + + modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) ); + m = modes; + if ( ! driFillInModes( & m, fb_format, fb_type, + depth_bits_array, stencil_bits_array, depth_buffer_factor, + back_buffer_modes, back_buffer_factor, + GLX_TRUE_COLOR ) ) { + fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", + __func__, __LINE__ ); + return NULL; + } + + if ( ! driFillInModes( & m, fb_format, fb_type, + depth_bits_array, stencil_bits_array, depth_buffer_factor, + back_buffer_modes, back_buffer_factor, + GLX_DIRECT_COLOR ) ) { + fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", + __func__, __LINE__ ); + return NULL; + } + + /* Mark the visual as slow if there are "fake" stencil bits. + */ + for ( m = modes ; m != NULL ; m = m->next ) { + if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) { + m->visualRating = GLX_SLOW_CONFIG; + } + } + + return modes; +} + + +/* Create the device specific screen private data struct. + */ +static radeonScreenPtr +radeonCreateScreen( __DRIscreenPrivate *sPriv ) +{ + radeonScreenPtr screen; + RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; + unsigned char *RADEONMMIO; + PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension = + (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension")); + void * const psc = sPriv->psc->screenConfigs; + + if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { + fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); + return GL_FALSE; + } + + /* Allocate the private area */ + screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); + if ( !screen ) { + __driUtilMessage("%s: Could not allocate memory for screen structure", + __FUNCTION__); + return NULL; + } + +#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); +#endif + + /* parse information in __driConfigOptions */ + driParseOptionInfo (&screen->optionCache, + __driConfigOptions, __driNConfigOptions); + + /* This is first since which regions we map depends on whether or + * not we are using a PCI card. + */ + screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); + { + int ret; + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, + &screen->gart_buffer_offset); + + if (ret) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); + return NULL; + } + + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, + &screen->gart_base); + if (ret) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); + return NULL; + } + + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, + &screen->irq); + if (ret) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); + return NULL; + } + screen->drmSupportsCubeMapsR200 = (sPriv->drmMinor >= 7); + screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11); + screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16); + screen->drmSupportsFragShader = (sPriv->drmMinor >= 18); + screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13); + screen->drmSupportsCubeMapsR100 = (sPriv->drmMinor >= 15); + screen->drmSupportsVertexProgram = (sPriv->drmMinor >= 25); + } + + screen->mmio.handle = dri_priv->registerHandle; + screen->mmio.size = dri_priv->registerSize; + if ( drmMap( sPriv->fd, + screen->mmio.handle, + screen->mmio.size, + &screen->mmio.map ) ) { + FREE( screen ); + __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); + return NULL; + } + + RADEONMMIO = screen->mmio.map; + + screen->status.handle = dri_priv->statusHandle; + screen->status.size = dri_priv->statusSize; + if ( drmMap( sPriv->fd, + screen->status.handle, + screen->status.size, + &screen->status.map ) ) { + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); + return NULL; + } + screen->scratch = (__volatile__ u_int32_t *) + ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); + + screen->buffers = drmMapBufs( sPriv->fd ); + if ( !screen->buffers ) { + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); + return NULL; + } + + if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { + screen->gartTextures.handle = dri_priv->gartTexHandle; + screen->gartTextures.size = dri_priv->gartTexMapSize; + if ( drmMap( sPriv->fd, + screen->gartTextures.handle, + screen->gartTextures.size, + (drmAddressPtr)&screen->gartTextures.map ) ) { + drmUnmapBufs( screen->buffers ); + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); + return NULL; + } + + screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; + } + + screen->chip_flags = 0; + /* XXX: add more chipsets */ + switch ( dri_priv->deviceID ) { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + case PCI_CHIP_RADEON_QY: + case PCI_CHIP_RADEON_QZ: + case PCI_CHIP_RN50_515E: + case PCI_CHIP_RN50_5969: + screen->chip_family = CHIP_FAMILY_RV100; + break; + + case PCI_CHIP_RS100_4136: + case PCI_CHIP_RS100_4336: + screen->chip_family = CHIP_FAMILY_RS100; + break; + + case PCI_CHIP_RS200_4137: + case PCI_CHIP_RS200_4337: + case PCI_CHIP_RS250_4237: + case PCI_CHIP_RS250_4437: + screen->chip_family = CHIP_FAMILY_RS200; + break; + + case PCI_CHIP_RADEON_QD: + case PCI_CHIP_RADEON_QE: + case PCI_CHIP_RADEON_QF: + case PCI_CHIP_RADEON_QG: + /* all original radeons (7200) presumably have a stencil op bug */ + screen->chip_family = CHIP_FAMILY_R100; + screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; + break; + + case PCI_CHIP_RV200_QW: + case PCI_CHIP_RV200_QX: + case PCI_CHIP_RADEON_LW: + case PCI_CHIP_RADEON_LX: + screen->chip_family = CHIP_FAMILY_RV200; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_R200_BB: + case PCI_CHIP_R200_BC: + case PCI_CHIP_R200_QH: + case PCI_CHIP_R200_QL: + case PCI_CHIP_R200_QM: + screen->chip_family = CHIP_FAMILY_R200; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV250_If: + case PCI_CHIP_RV250_Ig: + case PCI_CHIP_RV250_Ld: + case PCI_CHIP_RV250_Lf: + case PCI_CHIP_RV250_Lg: + screen->chip_family = CHIP_FAMILY_RV250; + screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV280_5960: + case PCI_CHIP_RV280_5961: + case PCI_CHIP_RV280_5962: + case PCI_CHIP_RV280_5964: + case PCI_CHIP_RV280_5965: + case PCI_CHIP_RV280_5C61: + case PCI_CHIP_RV280_5C63: + screen->chip_family = CHIP_FAMILY_RV280; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RS300_5834: + case PCI_CHIP_RS300_5835: + case PCI_CHIP_RS350_7834: + case PCI_CHIP_RS350_7835: + screen->chip_family = CHIP_FAMILY_RS300; + break; + + case PCI_CHIP_R300_AD: + case PCI_CHIP_R300_AE: + case PCI_CHIP_R300_AF: + case PCI_CHIP_R300_AG: + case PCI_CHIP_R300_ND: + case PCI_CHIP_R300_NE: + case PCI_CHIP_R300_NF: + case PCI_CHIP_R300_NG: + screen->chip_family = CHIP_FAMILY_R300; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV350_AP: + case PCI_CHIP_RV350_AQ: + case PCI_CHIP_RV350_AR: + case PCI_CHIP_RV350_AS: + case PCI_CHIP_RV350_AT: + case PCI_CHIP_RV350_AV: + case PCI_CHIP_RV350_AU: + case PCI_CHIP_RV350_NP: + case PCI_CHIP_RV350_NQ: + case PCI_CHIP_RV350_NR: + case PCI_CHIP_RV350_NS: + case PCI_CHIP_RV350_NT: + case PCI_CHIP_RV350_NV: + screen->chip_family = CHIP_FAMILY_RV350; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_R350_AH: + case PCI_CHIP_R350_AI: + case PCI_CHIP_R350_AJ: + case PCI_CHIP_R350_AK: + case PCI_CHIP_R350_NH: + case PCI_CHIP_R350_NI: + case PCI_CHIP_R360_NJ: + case PCI_CHIP_R350_NK: + screen->chip_family = CHIP_FAMILY_R350; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV370_5460: + case PCI_CHIP_RV370_5462: + case PCI_CHIP_RV370_5464: + case PCI_CHIP_RV370_5B60: + case PCI_CHIP_RV370_5B62: + case PCI_CHIP_RV370_5B63: + case PCI_CHIP_RV370_5B64: + case PCI_CHIP_RV370_5B65: + case PCI_CHIP_RV380_3150: + case PCI_CHIP_RV380_3152: + case PCI_CHIP_RV380_3154: + case PCI_CHIP_RV380_3E50: + case PCI_CHIP_RV380_3E54: + screen->chip_family = CHIP_FAMILY_RV380; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_R420_JN: + case PCI_CHIP_R420_JH: + case PCI_CHIP_R420_JI: + case PCI_CHIP_R420_JJ: + case PCI_CHIP_R420_JK: + case PCI_CHIP_R420_JL: + case PCI_CHIP_R420_JM: + case PCI_CHIP_R420_JO: + case PCI_CHIP_R420_JP: + case PCI_CHIP_R420_JT: + case PCI_CHIP_R481_4B49: + case PCI_CHIP_R481_4B4A: + case PCI_CHIP_R481_4B4B: + case PCI_CHIP_R481_4B4C: + case PCI_CHIP_R423_UH: + case PCI_CHIP_R423_UI: + case PCI_CHIP_R423_UJ: + case PCI_CHIP_R423_UK: + case PCI_CHIP_R430_554C: + case PCI_CHIP_R430_554D: + case PCI_CHIP_R430_554E: + case PCI_CHIP_R430_554F: + case PCI_CHIP_R423_5550: + case PCI_CHIP_R423_UQ: + case PCI_CHIP_R423_UR: + case PCI_CHIP_R423_UT: + case PCI_CHIP_R430_5D48: + case PCI_CHIP_R430_5D49: + case PCI_CHIP_R430_5D4A: + case PCI_CHIP_R480_5D4C: + case PCI_CHIP_R480_5D4D: + case PCI_CHIP_R480_5D4E: + case PCI_CHIP_R480_5D4F: + case PCI_CHIP_R480_5D50: + case PCI_CHIP_R480_5D52: + case PCI_CHIP_R423_5D57: + screen->chip_family = CHIP_FAMILY_R420; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV410_564A: + case PCI_CHIP_RV410_564B: + case PCI_CHIP_RV410_564F: + case PCI_CHIP_RV410_5652: + case PCI_CHIP_RV410_5653: + case PCI_CHIP_RV410_5E48: + case PCI_CHIP_RV410_5E4A: + case PCI_CHIP_RV410_5E4B: + case PCI_CHIP_RV410_5E4C: + case PCI_CHIP_RV410_5E4D: + case PCI_CHIP_RV410_5E4F: + screen->chip_family = CHIP_FAMILY_RV410; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RS480_5954: + case PCI_CHIP_RS480_5955: + case PCI_CHIP_RS482_5974: + case PCI_CHIP_RS482_5975: + case PCI_CHIP_RS400_5A41: + case PCI_CHIP_RS400_5A42: + case PCI_CHIP_RC410_5A61: + case PCI_CHIP_RC410_5A62: + screen->chip_family = CHIP_FAMILY_RS400; + fprintf(stderr, "Warning, xpress200 detected.\n"); + break; + + default: + fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", + dri_priv->deviceID); + return NULL; + } + if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && + sPriv->ddxMinor < 2) { + fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); + return NULL; + } + + if (screen->chip_family <= CHIP_FAMILY_RS200) + screen->chip_flags |= RADEON_CLASS_R100; + else if (screen->chip_family <= CHIP_FAMILY_RV280) + screen->chip_flags |= RADEON_CLASS_R200; + else + screen->chip_flags |= RADEON_CLASS_R300; + + screen->cpp = dri_priv->bpp / 8; + screen->AGPMode = dri_priv->AGPMode; + + screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16; + + if ( sPriv->drmMinor >= 10 ) { + drm_radeon_setparam_t sp; + + sp.param = RADEON_SETPARAM_FB_LOCATION; + sp.value = screen->fbLocation; + + drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, + &sp, sizeof( sp ) ); + } + + screen->frontOffset = dri_priv->frontOffset; + screen->frontPitch = dri_priv->frontPitch; + screen->backOffset = dri_priv->backOffset; + screen->backPitch = dri_priv->backPitch; + screen->depthOffset = dri_priv->depthOffset; + screen->depthPitch = dri_priv->depthPitch; + + /* Check if ddx has set up a surface reg to cover depth buffer */ + screen->depthHasSurface = ((sPriv->ddxMajor > 4) && + (screen->chip_flags & RADEON_CHIPSET_TCL)); + + if ( dri_priv->textureSize == 0 ) { + screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; + screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; + screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = + dri_priv->log2GARTTexGran; + } else { + screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset + + screen->fbLocation; + screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; + screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = + dri_priv->log2TexGran; + } + + if ( !screen->gartTextures.map || dri_priv->textureSize == 0 + || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { + screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; + screen->texOffset[RADEON_GART_TEX_HEAP] = 0; + screen->texSize[RADEON_GART_TEX_HEAP] = 0; + screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; + } else { + screen->numTexHeaps = RADEON_NR_TEX_HEAPS; + screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; + screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; + screen->logTexGranularity[RADEON_GART_TEX_HEAP] = + dri_priv->log2GARTTexGran; + } + + if ( glx_enable_extension != NULL ) { + if ( screen->irq != 0 ) { + (*glx_enable_extension)( psc, "GLX_SGI_swap_control" ); + (*glx_enable_extension)( psc, "GLX_SGI_video_sync" ); + (*glx_enable_extension)( psc, "GLX_MESA_swap_control" ); + } + + (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" ); + if (IS_R200_CLASS(screen)) + (*glx_enable_extension)( psc, "GLX_MESA_allocate_memory" ); + + (*glx_enable_extension)( psc, "GLX_MESA_copy_sub_buffer" ); + (*glx_enable_extension)( psc, "GLX_SGI_make_current_read" ); + } + +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + if (IS_R200_CLASS(screen)) { + sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA; + sPriv->psc->freeMemory = (void *) r200FreeMemoryMESA; + sPriv->psc->memoryOffset = (void *) r200GetMemoryOffsetMESA; + } +#endif + + screen->driScreen = sPriv; + screen->sarea_priv_offset = dri_priv->sarea_priv_offset; + return screen; +} + +/* Destroy the device specific screen private data struct. + */ +static void +radeonDestroyScreen( __DRIscreenPrivate *sPriv ) +{ + radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; + + if (!screen) + return; + + if ( screen->gartTextures.map ) { + drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); + } + drmUnmapBufs( screen->buffers ); + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + + /* free all option information */ + driDestroyOptionInfo (&screen->optionCache); + + FREE( screen ); + sPriv->private = NULL; +} + + +/* Initialize the driver specific screen private data. + */ +static GLboolean +radeonInitDriver( __DRIscreenPrivate *sPriv ) +{ + sPriv->private = (void *) radeonCreateScreen( sPriv ); + if ( !sPriv->private ) { + radeonDestroyScreen( sPriv ); + return GL_FALSE; + } + + return GL_TRUE; +} + + +/** + * Create the Mesa framebuffer and renderbuffers for a given window/drawable. + * + * \todo This function (and its interface) will need to be updated to support + * pbuffers. + */ +static GLboolean +radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, + __DRIdrawablePrivate *driDrawPriv, + const __GLcontextModes *mesaVis, + GLboolean isPixmap ) +{ + radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; + + if (isPixmap) { + return GL_FALSE; /* not implemented */ + } + else { + const GLboolean swDepth = GL_FALSE; + const GLboolean swAlpha = GL_FALSE; + const GLboolean swAccum = mesaVis->accumRedBits > 0; + const GLboolean swStencil = mesaVis->stencilBits > 0 && + mesaVis->depthBits != 24; + struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); + + /* front color renderbuffer */ + { + driRenderbuffer *frontRb + = driNewRenderbuffer(GL_RGBA, + driScrnPriv->pFB + screen->frontOffset, + screen->cpp, + screen->frontOffset, screen->frontPitch, + driDrawPriv); + radeonSetSpanFunctions(frontRb, mesaVis); + _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base); + } + + /* back color renderbuffer */ + if (mesaVis->doubleBufferMode) { + driRenderbuffer *backRb + = driNewRenderbuffer(GL_RGBA, + driScrnPriv->pFB + screen->backOffset, + screen->cpp, + screen->backOffset, screen->backPitch, + driDrawPriv); + radeonSetSpanFunctions(backRb, mesaVis); + _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base); + } + + /* depth renderbuffer */ + if (mesaVis->depthBits == 16) { + driRenderbuffer *depthRb + = driNewRenderbuffer(GL_DEPTH_COMPONENT16, + driScrnPriv->pFB + screen->depthOffset, + screen->cpp, + screen->depthOffset, screen->depthPitch, + driDrawPriv); + radeonSetSpanFunctions(depthRb, mesaVis); + _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); + depthRb->depthHasSurface = screen->depthHasSurface; + } + else if (mesaVis->depthBits == 24) { + driRenderbuffer *depthRb + = driNewRenderbuffer(GL_DEPTH_COMPONENT24, + driScrnPriv->pFB + screen->depthOffset, + screen->cpp, + screen->depthOffset, screen->depthPitch, + driDrawPriv); + radeonSetSpanFunctions(depthRb, mesaVis); + _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); + depthRb->depthHasSurface = screen->depthHasSurface; + } + + /* stencil renderbuffer */ + if (mesaVis->stencilBits > 0 && !swStencil) { + driRenderbuffer *stencilRb + = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT, + driScrnPriv->pFB + screen->depthOffset, + screen->cpp, + screen->depthOffset, screen->depthPitch, + driDrawPriv); + radeonSetSpanFunctions(stencilRb, mesaVis); + _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); + stencilRb->depthHasSurface = screen->depthHasSurface; + } + + _mesa_add_soft_renderbuffers(fb, + GL_FALSE, /* color */ + swDepth, + swStencil, + swAccum, + swAlpha, + GL_FALSE /* aux */); + driDrawPriv->driverPrivate = (void *) fb; + + return (driDrawPriv->driverPrivate != NULL); + } +} + + +static void +radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +{ + _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); +} + +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) +/** + * Choose the appropriate CreateContext function based on the chipset. + * Eventually, all drivers will go through this process. + */ +static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, + __DRIcontextPrivate * driContextPriv, + void *sharedContextPriv) +{ + __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); + + if (IS_R300_CLASS(screen)) + return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); + return GL_FALSE; +} + +/** + * Choose the appropriate DestroyContext function based on the chipset. + */ +static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) +{ + radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; + + if (IS_R300_CLASS(radeon->radeonScreen)) + return r300DestroyContext(driContextPriv); +} + + +#endif + +#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) +static struct __DriverAPIRec radeonAPI = { + .InitDriver = radeonInitDriver, + .DestroyScreen = radeonDestroyScreen, + .CreateContext = radeonCreateContext, + .DestroyContext = radeonDestroyContext, + .CreateBuffer = radeonCreateBuffer, + .DestroyBuffer = radeonDestroyBuffer, + .SwapBuffers = radeonSwapBuffers, + .MakeCurrent = radeonMakeCurrent, + .UnbindContext = radeonUnbindContext, + .GetSwapInfo = getSwapInfo, + .GetMSC = driGetMSC32, + .WaitForMSC = driWaitForMSC32, + .WaitForSBC = NULL, + .SwapBuffersMSC = NULL, + .CopySubBuffer = radeonCopySubBuffer, +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + .setTexOffset = r300SetTexOffset, +#endif +}; +#else +static const struct __DriverAPIRec r200API = { + .InitDriver = radeonInitDriver, + .DestroyScreen = radeonDestroyScreen, + .CreateContext = r200CreateContext, + .DestroyContext = r200DestroyContext, + .CreateBuffer = radeonCreateBuffer, + .DestroyBuffer = radeonDestroyBuffer, + .SwapBuffers = r200SwapBuffers, + .MakeCurrent = r200MakeCurrent, + .UnbindContext = r200UnbindContext, + .GetSwapInfo = getSwapInfo, + .GetMSC = driGetMSC32, + .WaitForMSC = driWaitForMSC32, + .WaitForSBC = NULL, + .SwapBuffersMSC = NULL, + .CopySubBuffer = r200CopySubBuffer, + .setTexOffset = r200SetTexOffset +}; +#endif + +/** + * This is the bootstrap function for the driver. libGL supplies all of the + * requisite information about the system, and the driver initializes itself. + * This routine also fills in the linked list pointed to by \c driver_modes + * with the \c __GLcontextModes that the driver can support for windows or + * pbuffers. + * + * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on + * failure. + */ +PUBLIC void * +__driCreateNewScreen_20050727( __DRInativeDisplay *dpy, + int scrn, __DRIscreen *psc, + const __GLcontextModes * modes, + const __DRIversion * ddx_version, + const __DRIversion * dri_version, + const __DRIversion * drm_version, + const __DRIframebuffer * frame_buffer, + drmAddress pSAREA, int fd, + int internal_api_version, + const __DRIinterfaceMethods * interface, + __GLcontextModes ** driver_modes ) +{ + __DRIscreenPrivate *psp; +#if !RADEON_COMMON + static const char *driver_name = "Radeon"; + static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; + static const __DRIversion dri_expected = { 4, 0, 0 }; + static const __DRIversion drm_expected = { 1, 6, 0 }; +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + static const char *driver_name = "R200"; + static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; + static const __DRIversion dri_expected = { 4, 0, 0 }; + static const __DRIversion drm_expected = { 1, 6, 0 }; +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + static const char *driver_name = "R300"; + static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; + static const __DRIversion dri_expected = { 4, 0, 0 }; + static const __DRIversion drm_expected = { 1, 24, 0 }; +#endif + + dri_interface = interface; + + if ( ! driCheckDriDdxDrmVersions3( driver_name, + dri_version, & dri_expected, + ddx_version, & ddx_expected, + drm_version, & drm_expected ) ) { + return NULL; + } +#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) + psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL, + ddx_version, dri_version, drm_version, + frame_buffer, pSAREA, fd, + internal_api_version, &radeonAPI); +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL, + ddx_version, dri_version, drm_version, + frame_buffer, pSAREA, fd, + internal_api_version, &r200API); +#endif + + if ( psp != NULL ) { + RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; + if (driver_modes) { + *driver_modes = radeonFillInModes( dri_priv->bpp, + (dri_priv->bpp == 16) ? 16 : 24, + (dri_priv->bpp == 16) ? 0 : 8, + (dri_priv->backOffset != dri_priv->depthOffset) ); + } + + /* Calling driInitExtensions here, with a NULL context pointer, + * does not actually enable the extensions. It just makes sure + * that all the dispatch offsets for all the extensions that + * *might* be enables are known. This is needed because the + * dispatch offsets need to be known when _mesa_context_create + * is called, but we can't enable the extensions until we have a + * context pointer. + * + * Hello chicken. Hello egg. How are you two today? + */ + driInitExtensions( NULL, card_extensions, GL_FALSE ); +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + driInitExtensions( NULL, blend_extensions, GL_FALSE ); + driInitSingleExtension( NULL, ARB_vp_extension ); + driInitSingleExtension( NULL, NV_vp_extension ); + driInitSingleExtension( NULL, ATI_fs_extension ); + driInitExtensions( NULL, point_extensions, GL_FALSE ); +#endif + } + + return (void *) psp; +} + + +/** + * Get information about previous buffer swaps. + */ +static int +getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) +{ +#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) + radeonContextPtr rmesa; +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + r200ContextPtr rmesa; +#endif + + if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) + || (dPriv->driContextPriv->driverPrivate == NULL) + || (sInfo == NULL) ) { + return -1; + } + + rmesa = dPriv->driContextPriv->driverPrivate; + sInfo->swap_count = rmesa->swap_count; + sInfo->swap_ust = rmesa->swap_ust; + sInfo->swap_missed_count = rmesa->swap_missed_count; + + sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) + ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) + : 0.0; + + return 0; +} diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/radeon_screen.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/radeon_screen.h new file mode 100644 index 00000000000..25e6fcf399a --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/radeon_screen.h @@ -0,0 +1,115 @@ +/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.h,v 1.5 2002/12/16 16:18:58 dawes Exp $ */ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and + VA Linux Systems Inc., Fremont, California. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin + * Gareth Hughes + */ + +#ifndef __RADEON_SCREEN_H__ +#define __RADEON_SCREEN_H__ + +/* + * IMPORTS: these headers contain all the DRI, X and kernel-related + * definitions that we need. + */ +#include "dri_util.h" +#include "radeon_dri.h" +#include "radeon_chipset.h" +#include "radeon_reg.h" +#include "drm_sarea.h" +#include "xmlconfig.h" + + +typedef struct { + drm_handle_t handle; /* Handle to the DRM region */ + drmSize size; /* Size of the DRM region */ + drmAddress map; /* Mapping of the DRM region */ +} radeonRegionRec, *radeonRegionPtr; + +typedef struct { + int chip_family; + int chip_flags; + int cpp; + int card_type; + int AGPMode; + unsigned int irq; /* IRQ number (0 means none) */ + + unsigned int fbLocation; + unsigned int frontOffset; + unsigned int frontPitch; + unsigned int backOffset; + unsigned int backPitch; + + unsigned int depthOffset; + unsigned int depthPitch; + + /* Shared texture data */ + int numTexHeaps; + int texOffset[RADEON_NR_TEX_HEAPS]; + int texSize[RADEON_NR_TEX_HEAPS]; + int logTexGranularity[RADEON_NR_TEX_HEAPS]; + + radeonRegionRec mmio; + radeonRegionRec status; + radeonRegionRec gartTextures; + + drmBufMapPtr buffers; + + __volatile__ u_int32_t *scratch; + + __DRIscreenPrivate *driScreen; + unsigned int sarea_priv_offset; + unsigned int gart_buffer_offset; /* offset in card memory space */ + unsigned int gart_texture_offset; /* offset in card memory space */ + unsigned int gart_base; + + GLboolean drmSupportsCubeMapsR200; /* need radeon kernel module >= 1.7 */ + GLboolean drmSupportsBlendColor; /* need radeon kernel module >= 1.11 */ + GLboolean drmSupportsTriPerf; /* need radeon kernel module >= 1.16 */ + GLboolean drmSupportsFragShader; /* need radeon kernel module >= 1.18 */ + GLboolean drmSupportsPointSprites; /* need radeon kernel module >= 1.13 */ + GLboolean drmSupportsCubeMapsR100; /* need radeon kernel module >= 1.15 */ + GLboolean drmSupportsVertexProgram; /* need radeon kernel module >= 1.25 */ + GLboolean depthHasSurface; + + /* Configuration cache with default values for all contexts */ + driOptionCache optionCache; +} radeonScreenRec, *radeonScreenPtr; + +#define IS_R100_CLASS(screen) \ + ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R100) +#define IS_R200_CLASS(screen) \ + ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R200) +#define IS_R300_CLASS(screen) \ + ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R300) + +#endif /* __RADEON_SCREEN_H__ */ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon.h new file mode 100644 index 00000000000..6f6c2e6d257 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon.h @@ -0,0 +1,209 @@ +/** + * \file server/radeon.h + * \brief Radeon 2D driver data structures. + */ + +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.29 2002/10/12 01:38:07 martin Exp $ */ + +#ifndef _RADEON_H_ +#define _RADEON_H_ + +#include "xf86drm.h" /* drm_handle_t, etc */ + +# define RADEON_AGP_1X_MODE 0x01 +# define RADEON_AGP_2X_MODE 0x02 +# define RADEON_AGP_4X_MODE 0x04 +# define RADEON_AGP_FW_MODE 0x10 +# define RADEON_AGP_MODE_MASK 0x17 +#define RADEON_CP_CSQ_CNTL 0x0740 +# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) +# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) +# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) +# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) +# define RADEON_CSQ_PRIBM_INDBM (4 << 28) +# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) + +#define RADEON_PCIGART_TABLE_SIZE 32768 + +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_RV250_Id 0x4964 +#define PCI_CHIP_RV250_Ie 0x4965 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Le 0x4C65 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QN 0x514E +#define PCI_CHIP_R200_QO 0x514F +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RADEON_QY 0x5159 +#define PCI_CHIP_RADEON_QZ 0x515A +#define PCI_CHIP_R200_Ql 0x516C +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV280_Y_ 0x5960 +#define PCI_CHIP_RV280_Ya 0x5961 +#define PCI_CHIP_RV280_Yb 0x5962 +#define PCI_CHIP_RV280_Yc 0x5963 + +/** + * \brief Chip families. + */ +typedef enum { + CHIP_FAMILY_UNKNOW, + CHIP_FAMILY_LEGACY, + CHIP_FAMILY_R128, + CHIP_FAMILY_M3, + CHIP_FAMILY_RADEON, + CHIP_FAMILY_VE, + CHIP_FAMILY_M6, + CHIP_FAMILY_RV200, + CHIP_FAMILY_M7, + CHIP_FAMILY_R200, + CHIP_FAMILY_RV250, + CHIP_FAMILY_M9, + CHIP_FAMILY_RV280, + CHIP_FAMILY_R300, + CHIP_FAMILY_R350, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ + CHIP_FAMILY_R420, /* R420/R423/M18 */ +} RADEONChipFamily; + + +typedef unsigned long memType; + + +/** + * \brief Radeon DDX driver private data. + */ +typedef struct { + int Chipset; /**< \brief Chipset number */ + RADEONChipFamily ChipFamily; /**< \brief Chip family */ + + unsigned long LinearAddr; /**< \brief Frame buffer physical address */ + + + drmSize registerSize; /**< \brief MMIO register map size */ + drm_handle_t registerHandle; /**< \brief MMIO register map handle */ + + int IsPCI; /* Current card is a PCI card */ + + /** + * \name AGP + */ + /*@{*/ + drmSize gartSize; /**< \brief AGP map size */ + drm_handle_t gartMemHandle; /**< \brief AGP map handle */ + unsigned long gartOffset; /**< \brief AGP offset */ + int gartMode; /**< \brief AGP mode */ + int gartFastWrite; + /*@}*/ + + /** + * \name CP ring buffer data + */ + /*@{*/ + unsigned long ringStart; /**< \brief Offset into AGP space */ + drm_handle_t ringHandle; /**< \brief Handle from drmAddMap() */ + drmSize ringMapSize; /**< \brief Size of map */ + int ringSize; /**< \brief Size of ring (in MB) */ + + unsigned long ringReadOffset; /**< \brief Read offset into AGP space */ + drm_handle_t ringReadPtrHandle;/**< \brief Handle from drmAddMap() */ + drmSize ringReadMapSize; /**< \brief Size of map */ + /*@}*/ + + /** + * \name CP vertex/indirect buffer data + */ + /*@{*/ + unsigned long bufStart; /**< \brief Offset into AGP space */ + drm_handle_t bufHandle; /**< \brief Handle from drmAddMap() */ + drmSize bufMapSize; /**< \brief Size of map */ + int bufSize; /**< \brief Size of buffers (in MB) */ + int bufNumBufs; /**< \brief Number of buffers */ + /*@}*/ + + /** + * \name CP AGP Texture data + */ + /*@{*/ + unsigned long gartTexStart; /**< \brief Offset into AGP space */ + drm_handle_t gartTexHandle; /**< \brief Handle from drmAddMap() */ + drmSize gartTexMapSize; /**< \brief Size of map */ + int gartTexSize; /**< \brief Size of AGP tex space (in MB) */ + int log2GARTTexGran; + /*@}*/ + + int drmMinor; /**< \brief DRM device minor number */ + + int frontOffset; /**< \brief Front color buffer offset */ + int frontPitch; /**< \brief Front color buffer pitch */ + int backOffset; /**< \brief Back color buffer offset */ + int backPitch; /**< \brief Back color buffer pitch */ + int depthOffset; /**< \brief Depth buffer offset */ + int depthPitch; /**< \brief Depth buffer pitch */ + int textureOffset; /**< \brief Texture area offset */ + int textureSize; /**< \brief Texture area size */ + int log2TexGran; /**< \brief Texture granularity in base 2 log */ + + unsigned int frontPitchOffset; + unsigned int backPitchOffset; + unsigned int depthPitchOffset; + + int colorTiling; /**< \brief Enable color tiling */ + + int irq; /**< \brief IRQ number */ + int page_flip_enable; /**< \brief Page Flip enable */ + unsigned int gen_int_cntl; + unsigned int crtc_offset_cntl; + + unsigned long pcieGartTableOffset; +} RADEONInfoRec, *RADEONInfoPtr; + + +#endif /* _RADEON_H_ */ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_dri.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_dri.c new file mode 100644 index 00000000000..7ead588dac8 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_dri.c @@ -0,0 +1,1337 @@ +/** + * \file server/radeon_dri.c + * \brief File to perform the device-specific initialization tasks typically + * done in the X server. + * + * Here they are converted to run in the client (or perhaps a standalone + * process), and to work with the frame buffer device rather than the X + * server infrastructure. + */ + +#include +#include +#include +#include +#include + +#include "driver.h" +#include "drm.h" +#include "memops.h" + +#include "radeon.h" +#include "radeon_dri.h" +#include "radeon_macros.h" +#include "radeon_reg.h" +#include "drm_sarea.h" + +static size_t radeon_drm_page_size; + +static int RadeonSetParam(const DRIDriverContext *ctx, int param, int value) +{ + drm_radeon_setparam_t sp; + + memset(&sp, 0, sizeof(sp)); + sp.param = param; + sp.value = value; + + if (drmCommandWrite(ctx->drmFD, DRM_RADEON_SETPARAM, &sp, sizeof(sp))) { + return -1; + } + + return 0; +} + +/** + * \brief Wait for free FIFO entries. + * + * \param ctx display handle. + * \param entries number of free entries to wait. + * + * It polls the free entries from the chip until it reaches the requested value + * or a timeout (3000 tries) occurs. Aborts the program if the FIFO times out. + */ +static void RADEONWaitForFifo( const DRIDriverContext *ctx, + int entries ) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + int i; + + for (i = 0; i < 3000; i++) { + int fifo_slots = + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; + if (fifo_slots >= entries) return; + } + + /* There are recoveries possible, but I haven't seen them work + * in practice: + */ + fprintf(stderr, "FIFO timed out: %d entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS)); + exit(1); +} + +/** + * \brief Read a PLL register. + * + * \param ctx display handle. + * \param addr PLL register index. + * + * \return value of the PLL register. + */ +static unsigned int RADEONINPLL( const DRIDriverContext *ctx, int addr) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + unsigned int data; + + OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); + data = INREG(RADEON_CLOCK_CNTL_DATA); + + return data; +} + +/** + * \brief Reset graphics card to known state. + * + * \param ctx display handle. + * + * Resets the values of several Radeon registers. + */ +static void RADEONEngineReset( const DRIDriverContext *ctx ) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + unsigned int clock_cntl_index; + unsigned int mclk_cntl; + unsigned int rbbm_soft_reset; + unsigned int host_path_cntl; + int i; + + OUTREGP(RADEON_RB2D_DSTCACHE_CTLSTAT, + RADEON_RB2D_DC_FLUSH_ALL, + ~RADEON_RB2D_DC_FLUSH_ALL); + for (i = 0; i < 512; i++) { + if (!(INREG(RADEON_RB2D_DSTCACHE_CTLSTAT) & RADEON_RB2D_DC_BUSY)) + break; + } + + clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); + + mclk_cntl = INPLL(ctx, RADEON_MCLK_CNTL); + OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl | + RADEON_FORCEON_MCLKA | + RADEON_FORCEON_MCLKB | + RADEON_FORCEON_YCLKA | + RADEON_FORCEON_YCLKB | + RADEON_FORCEON_MC | + RADEON_FORCEON_AIC)); + + /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some + * unexpected behaviour on some machines. Here we use + * RADEON_HOST_PATH_CNTL to reset it. + */ + host_path_cntl = INREG(RADEON_HOST_PATH_CNTL); + rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); + + OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | + RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB)); + INREG(RADEON_RBBM_SOFT_RESET); + OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & + (unsigned int) ~(RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB))); + INREG(RADEON_RBBM_SOFT_RESET); + + OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET); + INREG(RADEON_HOST_PATH_CNTL); + OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl); + + OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); + + OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); + OUTPLL(RADEON_MCLK_CNTL, mclk_cntl); +} + +/** + * \brief Restore the drawing engine. + * + * \param ctx display handle + * + * Resets the graphics card and sets initial values for several registers of + * the card's drawing engine. + * + * Turns on the radeon command processor engine (i.e., the ringbuffer). + */ +static int RADEONEngineRestore( const DRIDriverContext *ctx ) +{ + RADEONInfoPtr info = ctx->driverPrivate; + unsigned char *RADEONMMIO = ctx->MMIOAddress; + int pitch64, datatype, dp_gui_master_cntl, err; + + fprintf(stderr, "%s\n", __FUNCTION__); + + OUTREG(RADEON_RB3D_CNTL, 0); + RADEONEngineReset( ctx ); + + switch (ctx->bpp) { + case 16: datatype = 4; break; + case 32: datatype = 6; break; + default: return 0; + } + + dp_gui_master_cntl = + ((datatype << RADEON_GMC_DST_DATATYPE_SHIFT) + | RADEON_GMC_CLR_CMP_CNTL_DIS); + + pitch64 = ((ctx->shared.virtualWidth * (ctx->bpp / 8) + 0x3f)) >> 6; + + RADEONWaitForFifo(ctx, 1); + OUTREG(RADEON_DEFAULT_OFFSET, ((INREG(RADEON_DEFAULT_OFFSET) & 0xC0000000) + | (pitch64 << 22))); + + RADEONWaitForFifo(ctx, 1); + OUTREG(RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); + + RADEONWaitForFifo(ctx, 1); + OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX + | RADEON_DEFAULT_SC_BOTTOM_MAX)); + + RADEONWaitForFifo(ctx, 1); + OUTREG(RADEON_DP_GUI_MASTER_CNTL, (dp_gui_master_cntl + | RADEON_GMC_BRUSH_SOLID_COLOR + | RADEON_GMC_SRC_DATATYPE_COLOR)); + + RADEONWaitForFifo(ctx, 7); + OUTREG(RADEON_DST_LINE_START, 0); + OUTREG(RADEON_DST_LINE_END, 0); + OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); + OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0); + OUTREG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff); + OUTREG(RADEON_DP_SRC_BKGD_CLR, 0); + OUTREG(RADEON_DP_WRITE_MASK, 0xffffffff); + OUTREG(RADEON_AUX_SC_CNTL, 0); + +/* RADEONWaitForIdleMMIO(ctx); */ + usleep(100); + + + OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl); + if (info->colorTiling) + info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; + OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl); + + /* Initialize and start the CP if required */ + if ((err = drmCommandNone(ctx->drmFD, DRM_RADEON_CP_START)) != 0) { + fprintf(stderr, "%s: CP start %d\n", __FUNCTION__, err); + return 0; + } + + return 1; +} + + +/** + * \brief Shutdown the drawing engine. + * + * \param ctx display handle + * + * Turns off the command processor engine & restores the graphics card + * to a state that fbdev understands. + */ +static int RADEONEngineShutdown( const DRIDriverContext *ctx ) +{ + drm_radeon_cp_stop_t stop; + int ret, i; + + stop.flush = 1; + stop.idle = 1; + + ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop, + sizeof(drm_radeon_cp_stop_t)); + + if (ret == 0) { + return 0; + } else if (errno != EBUSY) { + return -errno; + } + + stop.flush = 0; + + i = 0; + do { + ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop, + sizeof(drm_radeon_cp_stop_t)); + } while (ret && errno == EBUSY && i++ < 10); + + if (ret == 0) { + return 0; + } else if (errno != EBUSY) { + return -errno; + } + + stop.idle = 0; + + if (drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, + &stop, sizeof(drm_radeon_cp_stop_t))) { + return -errno; + } else { + return 0; + } +} + +/** + * \brief Compute base 2 logarithm. + * + * \param val value. + * + * \return base 2 logarithm of \p val. + */ +static int RADEONMinBits(int val) +{ + int bits; + + if (!val) return 1; + for (bits = 0; val; val >>= 1, ++bits); + return bits; +} + +/** + * \brief Initialize the AGP state + * + * \param ctx display handle. + * \param info driver private data. + * + * \return one on success, or zero on failure. + * + * Acquires and enables the AGP device. Reserves memory in the AGP space for + * the ring buffer, vertex buffers and textures. Initialize the Radeon + * registers to point to that memory and add client mappings. + */ +static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + unsigned long mode; + int ret; + int s, l; + + if (drmAgpAcquire(ctx->drmFD) < 0) { + fprintf(stderr, "[gart] AGP not available\n"); + return 0; + } + + /* Modify the mode if the default mode is not appropriate for this + * particular combination of graphics card and AGP chipset. + */ + mode = drmAgpGetMode(ctx->drmFD); /* Default mode */ + + /* Disable fast write entirely - too many lockups. + */ + mode &= ~RADEON_AGP_MODE_MASK; + switch (ctx->agpmode) { + case 4: mode |= RADEON_AGP_4X_MODE; + case 2: mode |= RADEON_AGP_2X_MODE; + case 1: default: mode |= RADEON_AGP_1X_MODE; + } + + if (drmAgpEnable(ctx->drmFD, mode) < 0) { + fprintf(stderr, "[gart] AGP not enabled\n"); + drmAgpRelease(ctx->drmFD); + return 0; + } + else + fprintf(stderr, "[gart] AGP enabled at %dx\n", ctx->agpmode); + + /* Workaround for some hardware bugs */ + if (info->ChipFamily < CHIP_FAMILY_R200) + OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000); + + info->gartOffset = 0; + + if ((ret = drmAgpAlloc(ctx->drmFD, info->gartSize*1024*1024, 0, NULL, + &info->gartMemHandle)) < 0) { + fprintf(stderr, "[gart] Out of memory (%d)\n", ret); + drmAgpRelease(ctx->drmFD); + return 0; + } + fprintf(stderr, + "[gart] %d kB allocated with handle 0x%08x\n", + info->gartSize*1024, (unsigned)info->gartMemHandle); + + if (drmAgpBind(ctx->drmFD, + info->gartMemHandle, info->gartOffset) < 0) { + fprintf(stderr, "[gart] Could not bind\n"); + drmAgpFree(ctx->drmFD, info->gartMemHandle); + drmAgpRelease(ctx->drmFD); + return 0; + } + + /* Initialize the CP ring buffer data */ + info->ringStart = info->gartOffset; + info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size; + + info->ringReadOffset = info->ringStart + info->ringMapSize; + info->ringReadMapSize = radeon_drm_page_size; + + /* Reserve space for vertex/indirect buffers */ + info->bufStart = info->ringReadOffset + info->ringReadMapSize; + info->bufMapSize = info->bufSize*1024*1024; + + /* Reserve the rest for AGP textures */ + info->gartTexStart = info->bufStart + info->bufMapSize; + s = (info->gartSize*1024*1024 - info->gartTexStart); + l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + info->gartTexMapSize = (s >> l) << l; + info->log2GARTTexGran = l; + + if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize, + DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) { + fprintf(stderr, "[gart] Could not add ring mapping\n"); + return 0; + } + fprintf(stderr, "[gart] ring handle = 0x%08x\n", info->ringHandle); + + + if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize, + DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) { + fprintf(stderr, + "[gart] Could not add ring read ptr mapping\n"); + return 0; + } + + fprintf(stderr, + "[gart] ring read ptr handle = 0x%08lx\n", + info->ringReadPtrHandle); + + if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize, + DRM_AGP, 0, &info->bufHandle) < 0) { + fprintf(stderr, + "[gart] Could not add vertex/indirect buffers mapping\n"); + return 0; + } + fprintf(stderr, + "[gart] vertex/indirect buffers handle = 0x%08x\n", + info->bufHandle); + + if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize, + DRM_AGP, 0, &info->gartTexHandle) < 0) { + fprintf(stderr, + "[gart] Could not add AGP texture map mapping\n"); + return 0; + } + fprintf(stderr, + "[gart] AGP texture map handle = 0x%08lx\n", + info->gartTexHandle); + + /* Initialize Radeon's AGP registers */ + /* Ring buffer is at AGP offset 0 */ + OUTREG(RADEON_AGP_BASE, info->ringHandle); + + return 1; +} + +/* Initialize the PCI GART state. Request memory for use in PCI space, + * and initialize the Radeon registers to point to that memory. + */ +static int RADEONDRIPciInit(const DRIDriverContext *ctx, RADEONInfoPtr info) +{ + int ret; + int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL; + int s, l; + + ret = drmScatterGatherAlloc(ctx->drmFD, info->gartSize*1024*1024, + &info->gartMemHandle); + if (ret < 0) { + fprintf(stderr, "[pci] Out of memory (%d)\n", ret); + return 0; + } + fprintf(stderr, + "[pci] %d kB allocated with handle 0x%08lx\n", + info->gartSize*1024, info->gartMemHandle); + + info->gartOffset = 0; + + /* Initialize the CP ring buffer data */ + info->ringStart = info->gartOffset; + info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size; + + info->ringReadOffset = info->ringStart + info->ringMapSize; + info->ringReadMapSize = radeon_drm_page_size; + + /* Reserve space for vertex/indirect buffers */ + info->bufStart = info->ringReadOffset + info->ringReadMapSize; + info->bufMapSize = info->bufSize*1024*1024; + + /* Reserve the rest for AGP textures */ + info->gartTexStart = info->bufStart + info->bufMapSize; + s = (info->gartSize*1024*1024 - info->gartTexStart); + l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + info->gartTexMapSize = (s >> l) << l; + info->log2GARTTexGran = l; + + if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize, + DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) { + fprintf(stderr, + "[pci] Could not add ring mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] ring handle = 0x%08x\n", info->ringHandle); + + if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize, + DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) { + fprintf(stderr, + "[pci] Could not add ring read ptr mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] ring read ptr handle = 0x%08lx\n", + info->ringReadPtrHandle); + + if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize, + DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) { + fprintf(stderr, + "[pci] Could not add vertex/indirect buffers mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] vertex/indirect buffers handle = 0x%08lx\n", + info->bufHandle); + + if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize, + DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) { + fprintf(stderr, + "[pci] Could not add GART texture map mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] GART texture map handle = 0x%08x\n", + info->gartTexHandle); + + return 1; +} + + +/** + * \brief Initialize the kernel data structures and enable the CP engine. + * + * \param ctx display handle. + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * This function is a wrapper around the DRM_RADEON_CP_INIT command, passing + * all the parameters in a drm_radeon_init_t structure. + */ +static int RADEONDRIKernelInit( const DRIDriverContext *ctx, + RADEONInfoPtr info) +{ + int cpp = ctx->bpp / 8; + drm_radeon_init_t drmInfo; + int ret; + + memset(&drmInfo, 0, sizeof(drm_radeon_init_t)); + + if ( (info->ChipFamily == CHIP_FAMILY_R200) || + (info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_M9) || + (info->ChipFamily == CHIP_FAMILY_RV280) ) + drmInfo.func = RADEON_INIT_R200_CP; + else + drmInfo.func = RADEON_INIT_CP; + + /* This is the struct passed to the kernel module for its initialization */ + drmInfo.sarea_priv_offset = sizeof(drm_sarea_t); + drmInfo.is_pci = ctx->isPCI; + drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE; + drmInfo.gart_size = info->gartSize*1024*1024; + drmInfo.ring_size = info->ringSize*1024*1024; + drmInfo.usec_timeout = 1000; + drmInfo.fb_bpp = ctx->bpp; + drmInfo.depth_bpp = ctx->bpp; + drmInfo.front_offset = info->frontOffset; + drmInfo.front_pitch = info->frontPitch * cpp; + drmInfo.back_offset = info->backOffset; + drmInfo.back_pitch = info->backPitch * cpp; + drmInfo.depth_offset = info->depthOffset; + drmInfo.depth_pitch = info->depthPitch * cpp; + drmInfo.fb_offset = info->LinearAddr; + drmInfo.mmio_offset = info->registerHandle; + drmInfo.ring_offset = info->ringHandle; + drmInfo.ring_rptr_offset = info->ringReadPtrHandle; + drmInfo.buffers_offset = info->bufHandle; + drmInfo.gart_textures_offset = info->gartTexHandle; + + ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_INIT, &drmInfo, + sizeof(drm_radeon_init_t)); + + return ret >= 0; +} + + +/** + * \brief Initialize the AGP heap. + * + * \param ctx display handle. + * \param info driver private data. + * + * This function is a wrapper around the DRM_RADEON_INIT_HEAP command, passing + * all the parameters in a drm_radeon_mem_init_heap structure. + */ +static void RADEONDRIAgpHeapInit(const DRIDriverContext *ctx, + RADEONInfoPtr info) +{ + drm_radeon_mem_init_heap_t drmHeap; + + /* Start up the simple memory manager for gart space */ + drmHeap.region = RADEON_MEM_REGION_GART; + drmHeap.start = 0; + drmHeap.size = info->gartTexMapSize; + + if (drmCommandWrite(ctx->drmFD, DRM_RADEON_INIT_HEAP, + &drmHeap, sizeof(drmHeap))) { + fprintf(stderr, + "[drm] Failed to initialized gart heap manager\n"); + } else { + fprintf(stderr, + "[drm] Initialized kernel gart heap manager, %d\n", + info->gartTexMapSize); + } +} + +/** + * \brief Add a map for the vertex buffers that will be accessed by any + * DRI-based clients. + * + * \param ctx display handle. + * \param info driver private data. + * + * \return one on success, or zero on failure. + * + * Calls drmAddBufs() with the previously allocated vertex buffers. + */ +static int RADEONDRIBufInit( const DRIDriverContext *ctx, RADEONInfoPtr info ) +{ + /* Initialize vertex buffers */ + info->bufNumBufs = drmAddBufs(ctx->drmFD, + info->bufMapSize / RADEON_BUFFER_SIZE, + RADEON_BUFFER_SIZE, + ctx->isPCI ? DRM_SG_BUFFER : DRM_AGP_BUFFER, + info->bufStart); + + if (info->bufNumBufs <= 0) { + fprintf(stderr, + "[drm] Could not create vertex/indirect buffers list\n"); + return 0; + } + fprintf(stderr, + "[drm] Added %d %d byte vertex/indirect buffers\n", + info->bufNumBufs, RADEON_BUFFER_SIZE); + + return 1; +} + +/** + * \brief Install an IRQ handler. + * + * \param ctx display handle. + * \param info driver private data. + * + * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to + * IRQ-free operation on failure. + */ +static void RADEONDRIIrqInit(const DRIDriverContext *ctx, + RADEONInfoPtr info) +{ + if (!info->irq) { + info->irq = drmGetInterruptFromBusID(ctx->drmFD, + ctx->pciBus, + ctx->pciDevice, + ctx->pciFunc); + + if ((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) { + fprintf(stderr, + "[drm] failure adding irq handler, " + "there is a device already using that irq\n" + "[drm] falling back to irq-free operation\n"); + info->irq = 0; + } + } + + if (info->irq) + fprintf(stderr, + "[drm] dma control initialized, using IRQ %d\n", + info->irq); +} + +static int RADEONCheckDRMVersion( const DRIDriverContext *ctx, + RADEONInfoPtr info ) +{ + drmVersionPtr version; + + version = drmGetVersion(ctx->drmFD); + if (version) { + int req_minor, req_patch; + + /* Need 1.8.x for proper cleanup-on-client-exit behaviour. + */ + req_minor = 8; + req_patch = 0; + + if (version->version_major != 1 || + version->version_minor < req_minor || + (version->version_minor == req_minor && + version->version_patchlevel < req_patch)) { + /* Incompatible drm version */ + fprintf(stderr, + "[dri] RADEONDRIScreenInit failed because of a version " + "mismatch.\n" + "[dri] radeon.o kernel module version is %d.%d.%d " + "but version 1.%d.%d or newer is needed.\n" + "[dri] Disabling DRI.\n", + version->version_major, + version->version_minor, + version->version_patchlevel, + req_minor, + req_patch); + drmFreeVersion(version); + return 0; + } + + info->drmMinor = version->version_minor; + drmFreeVersion(version); + } + + return 1; +} + +static int RADEONMemoryInit( const DRIDriverContext *ctx, RADEONInfoPtr info ) +{ + int width_bytes = ctx->shared.virtualWidth * ctx->cpp; + int cpp = ctx->cpp; + int bufferSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); + int depthSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); + int l; + + info->frontOffset = 0; + info->frontPitch = ctx->shared.virtualWidth; + + fprintf(stderr, + "Using %d MB AGP aperture\n", info->gartSize); + fprintf(stderr, + "Using %d MB for the ring buffer\n", info->ringSize); + fprintf(stderr, + "Using %d MB for vertex/indirect buffers\n", info->bufSize); + fprintf(stderr, + "Using %d MB for AGP textures\n", info->gartTexSize); + + /* Front, back and depth buffers - everything else texture?? + */ + info->textureSize = ctx->shared.fbSize - 2 * bufferSize - depthSize; + + if (ctx->colorTiling==1) + { + info->textureSize = ctx->shared.fbSize - ((ctx->shared.fbSize - info->textureSize + width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes*16); + } + + if (info->textureSize < 0) + return 0; + + l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + + /* Round the texture size up to the nearest whole number of + * texture regions. Again, be greedy about this, don't + * round down. + */ + info->log2TexGran = l; + info->textureSize = (info->textureSize >> l) << l; + + /* Set a minimum usable local texture heap size. This will fit + * two 256x256x32bpp textures. + */ + if (info->textureSize < 512 * 1024) { + info->textureOffset = 0; + info->textureSize = 0; + } + + /* Reserve space for textures */ + if (ctx->colorTiling==1) + { + info->textureOffset = ((ctx->shared.fbSize - info->textureSize) / + (width_bytes * 16)) * (width_bytes*16); + } + else + { + info->textureOffset = ((ctx->shared.fbSize - info->textureSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + } + /* Reserve space for the shared depth + * buffer. + */ + info->depthOffset = ((info->textureOffset - depthSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + info->depthPitch = ctx->shared.virtualWidth; + + info->backOffset = ((info->depthOffset - bufferSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + info->backPitch = ctx->shared.virtualWidth; + + + fprintf(stderr, + "Will use back buffer at offset 0x%x\n", + info->backOffset); + fprintf(stderr, + "Will use depth buffer at offset 0x%x\n", + info->depthOffset); + fprintf(stderr, + "Will use %d kb for textures at offset 0x%x\n", + info->textureSize/1024, info->textureOffset); + + info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) | + (info->frontOffset >> 10)); + + info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) | + (info->backOffset >> 10)); + + info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) | + (info->depthOffset >> 10)); + + return 1; +} + +static int RADEONColorTilingInit( const DRIDriverContext *ctx, RADEONInfoPtr info ) +{ + int width_bytes = ctx->shared.virtualWidth * ctx->cpp; + int bufferSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + RADEON_BUFFER_ALIGN) + & ~RADEON_BUFFER_ALIGN); + /* Setup color tiling */ + if (info->drmMinor<14) + info->colorTiling=0; + + if (info->colorTiling) + { + + int colorTilingFlag; + drm_radeon_surface_alloc_t front,back; + + RadeonSetParam(ctx, RADEON_SETPARAM_SWITCH_TILING, info->colorTiling ? 1 : 0); + + /* Setup the surfaces */ + if (info->ChipFamily < CHIP_FAMILY_R200) + colorTilingFlag=RADEON_SURF_TILE_COLOR_MACRO; + else + colorTilingFlag=R200_SURF_TILE_COLOR_MACRO; + + front.address = info->frontOffset; + front.size = bufferSize; + front.flags = (width_bytes) | colorTilingFlag; + drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &front,sizeof(front)); + + back.address = info->backOffset; + back.size = bufferSize; + back.flags = (width_bytes) | colorTilingFlag; + drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &back,sizeof(back)); + + } + return 1; +} + + + +/** + * Called at the start of each server generation. + * + * \param ctx display handle. + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * Performs static frame buffer allocation. Opens the DRM device and add maps + * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more + * information. Creates a \e server context to grab the lock for the + * initialization ioctls and calls the other initilization functions in this + * file. Starts the CP engine via the DRM_RADEON_CP_START command. + * + * Setups a RADEONDRIRec structure to be passed to radeon_dri.so for its + * initialization. + */ +static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info ) +{ + RADEONDRIPtr pRADEONDRI; + int err; + + usleep(100); + /*assert(!ctx->IsClient);*/ + + { + int width_bytes = (ctx->shared.virtualWidth * ctx->cpp); + int maxy = ctx->shared.fbSize / width_bytes; + + + if (maxy <= ctx->shared.virtualHeight * 3) { + fprintf(stderr, + "Static buffer allocation failed -- " + "need at least %d kB video memory (have %d kB)\n", + (ctx->shared.virtualWidth * ctx->shared.virtualHeight * + ctx->cpp * 3 + 1023) / 1024, + ctx->shared.fbSize / 1024); + return 0; + } + } + + + if (info->ChipFamily >= CHIP_FAMILY_R300) { + fprintf(stderr, + "Direct rendering not yet supported on " + "Radeon 9700 and newer cards\n"); + return 0; + } + + radeon_drm_page_size = getpagesize(); + + info->registerSize = ctx->MMIOSize; + ctx->shared.SAREASize = SAREA_MAX; + + /* Note that drmOpen will try to load the kernel module, if needed. */ + ctx->drmFD = drmOpen("radeon", NULL ); + if (ctx->drmFD < 0) { + fprintf(stderr, "[drm] drmOpen failed\n"); + return 0; + } + + if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) { + fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n", + ctx->drmFD, ctx->pciBusID, strerror(-err)); + return 0; + } + + if (drmAddMap( ctx->drmFD, + 0, + ctx->shared.SAREASize, + DRM_SHM, + DRM_CONTAINS_LOCK, + &ctx->shared.hSAREA) < 0) + { + fprintf(stderr, "[drm] drmAddMap failed\n"); + return 0; + } + fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n", + ctx->shared.SAREASize, ctx->shared.hSAREA); + + if (drmMap( ctx->drmFD, + ctx->shared.hSAREA, + ctx->shared.SAREASize, + (drmAddressPtr)(&ctx->pSAREA)) < 0) + { + fprintf(stderr, "[drm] drmMap failed\n"); + return 0; + } + memset(ctx->pSAREA, 0, ctx->shared.SAREASize); + fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n", + ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize); + + /* Need to AddMap the framebuffer and mmio regions here: + */ + if (drmAddMap( ctx->drmFD, + (drm_handle_t)ctx->FBStart, + ctx->FBSize, + DRM_FRAME_BUFFER, +#ifndef _EMBEDDED + 0, +#else + DRM_READ_ONLY, +#endif + &ctx->shared.hFrameBuffer) < 0) + { + fprintf(stderr, "[drm] drmAddMap framebuffer failed\n"); + return 0; + } + + fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n", + ctx->shared.hFrameBuffer); + + + + if (drmAddMap(ctx->drmFD, + ctx->MMIOStart, + ctx->MMIOSize, + DRM_REGISTERS, + DRM_READ_ONLY, + &info->registerHandle) < 0) { + fprintf(stderr, "[drm] drmAddMap mmio failed\n"); + return 0; + } + fprintf(stderr, + "[drm] register handle = 0x%08lx\n", info->registerHandle); + + /* Check the radeon DRM version */ + if (!RADEONCheckDRMVersion(ctx, info)) { + return 0; + } + + if (ctx->isPCI) { + /* Initialize PCI */ + if (!RADEONDRIPciInit(ctx, info)) + return 0; + } + else { + /* Initialize AGP */ + if (!RADEONDRIAgpInit(ctx, info)) + return 0; + } + + /* Memory manager setup */ + if (!RADEONMemoryInit(ctx, info)) { + return 0; + } + + /* Create a 'server' context so we can grab the lock for + * initialization ioctls. + */ + if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) { + fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err); + return 0; + } + + DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); + + /* Initialize the kernel data structures */ + if (!RADEONDRIKernelInit(ctx, info)) { + fprintf(stderr, "RADEONDRIKernelInit failed\n"); + DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext); + return 0; + } + + /* Initialize the vertex buffers list */ + if (!RADEONDRIBufInit(ctx, info)) { + fprintf(stderr, "RADEONDRIBufInit failed\n"); + DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext); + return 0; + } + + RADEONColorTilingInit(ctx, info); + + /* Initialize IRQ */ + RADEONDRIIrqInit(ctx, info); + + /* Initialize kernel gart memory manager */ + RADEONDRIAgpHeapInit(ctx, info); + + fprintf(stderr,"color tiling %sabled\n", info->colorTiling?"en":"dis"); + fprintf(stderr,"page flipping %sabled\n", info->page_flip_enable?"en":"dis"); + /* Initialize the SAREA private data structure */ + { + drm_radeon_sarea_t *pSAREAPriv; + pSAREAPriv = (drm_radeon_sarea_t *)(((char*)ctx->pSAREA) + + sizeof(drm_sarea_t)); + memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); + pSAREAPriv->pfState = info->page_flip_enable; + } + + + /* Quick hack to clear the front & back buffers. Could also use + * the clear ioctl to do this, but would need to setup hw state + * first. + */ + drimemsetio((char *)ctx->FBAddress + info->frontOffset, + 0, + info->frontPitch * ctx->cpp * ctx->shared.virtualHeight ); + + drimemsetio((char *)ctx->FBAddress + info->backOffset, + 0, + info->backPitch * ctx->cpp * ctx->shared.virtualHeight ); + + /* This is the struct passed to radeon_dri.so for its initialization */ + ctx->driverClientMsg = malloc(sizeof(RADEONDRIRec)); + ctx->driverClientMsgSize = sizeof(RADEONDRIRec); + pRADEONDRI = (RADEONDRIPtr)ctx->driverClientMsg; + pRADEONDRI->deviceID = info->Chipset; + pRADEONDRI->width = ctx->shared.virtualWidth; + pRADEONDRI->height = ctx->shared.virtualHeight; + pRADEONDRI->depth = ctx->bpp; /* XXX: depth */ + pRADEONDRI->bpp = ctx->bpp; + pRADEONDRI->IsPCI = ctx->isPCI; + pRADEONDRI->AGPMode = ctx->agpmode; + pRADEONDRI->frontOffset = info->frontOffset; + pRADEONDRI->frontPitch = info->frontPitch; + pRADEONDRI->backOffset = info->backOffset; + pRADEONDRI->backPitch = info->backPitch; + pRADEONDRI->depthOffset = info->depthOffset; + pRADEONDRI->depthPitch = info->depthPitch; + pRADEONDRI->textureOffset = info->textureOffset; + pRADEONDRI->textureSize = info->textureSize; + pRADEONDRI->log2TexGran = info->log2TexGran; + pRADEONDRI->registerHandle = info->registerHandle; + pRADEONDRI->registerSize = info->registerSize; + pRADEONDRI->statusHandle = info->ringReadPtrHandle; + pRADEONDRI->statusSize = info->ringReadMapSize; + pRADEONDRI->gartTexHandle = info->gartTexHandle; + pRADEONDRI->gartTexMapSize = info->gartTexMapSize; + pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran; + pRADEONDRI->gartTexOffset = info->gartTexStart; + pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t); + + /* Don't release the lock now - let the VT switch handler do it. */ + + return 1; +} + + +/** + * \brief Get Radeon chip family from chipset number. + * + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * Called by radeonInitFBDev() to set RADEONInfoRec::ChipFamily + * according to the value of RADEONInfoRec::Chipset. Fails if the + * chipset is unrecognized or not appropriate for this driver (i.e., not + * an r100 style radeon) + */ +static int get_chipfamily_from_chipset( RADEONInfoPtr info ) +{ + switch (info->Chipset) { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + info->ChipFamily = CHIP_FAMILY_M6; + break; + + case PCI_CHIP_RADEON_QY: + case PCI_CHIP_RADEON_QZ: + info->ChipFamily = CHIP_FAMILY_VE; + break; + + case PCI_CHIP_R200_QL: + case PCI_CHIP_R200_QN: + case PCI_CHIP_R200_QO: + case PCI_CHIP_R200_Ql: + case PCI_CHIP_R200_BB: + info->ChipFamily = CHIP_FAMILY_R200; + break; + + case PCI_CHIP_RV200_QW: /* RV200 desktop */ + case PCI_CHIP_RV200_QX: + info->ChipFamily = CHIP_FAMILY_RV200; + break; + + case PCI_CHIP_RADEON_LW: + case PCI_CHIP_RADEON_LX: + info->ChipFamily = CHIP_FAMILY_M7; + break; + + case PCI_CHIP_RV250_Id: + case PCI_CHIP_RV250_Ie: + case PCI_CHIP_RV250_If: + case PCI_CHIP_RV250_Ig: + info->ChipFamily = CHIP_FAMILY_RV250; + break; + + case PCI_CHIP_RV250_Ld: + case PCI_CHIP_RV250_Le: + case PCI_CHIP_RV250_Lf: + case PCI_CHIP_RV250_Lg: + info->ChipFamily = CHIP_FAMILY_M9; + break; + + case PCI_CHIP_RV280_Y_: + case PCI_CHIP_RV280_Ya: + case PCI_CHIP_RV280_Yb: + case PCI_CHIP_RV280_Yc: + info->ChipFamily = CHIP_FAMILY_RV280; + break; + + case PCI_CHIP_R300_ND: + case PCI_CHIP_R300_NE: + case PCI_CHIP_R300_NF: + case PCI_CHIP_R300_NG: + info->ChipFamily = CHIP_FAMILY_R300; + break; + + default: + /* Original Radeon/7200 */ + info->ChipFamily = CHIP_FAMILY_RADEON; + } + + return 1; +} + + +/** + * \brief Validate the fbdev mode. + * + * \param ctx display handle. + * + * \return one on success, or zero on failure. + * + * Saves some registers and returns 1. + * + * \sa radeonValidateMode(). + */ +static int radeonValidateMode( const DRIDriverContext *ctx ) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + RADEONInfoPtr info = ctx->driverPrivate; + + info->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL); + info->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); + + if (info->colorTiling) + info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; + return 1; +} + + +/** + * \brief Examine mode returned by fbdev. + * + * \param ctx display handle. + * + * \return one on success, or zero on failure. + * + * Restores registers that fbdev has clobbered and returns 1. + * + * \sa radeonValidateMode(). + */ +static int radeonPostValidateMode( const DRIDriverContext *ctx ) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + RADEONInfoPtr info = ctx->driverPrivate; + + RADEONColorTilingInit( ctx, info); + OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl); + if (info->colorTiling) + info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; + OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl); + + return 1; +} + + +/** + * \brief Initialize the framebuffer device mode + * + * \param ctx display handle. + * + * \return one on success, or zero on failure. + * + * Fills in \p info with some default values and some information from \p ctx + * and then calls RADEONScreenInit() for the screen initialization. + * + * Before exiting clears the framebuffer memory accessing it directly. + */ +static int radeonInitFBDev( DRIDriverContext *ctx ) +{ + RADEONInfoPtr info = calloc(1, sizeof(*info)); + + { + int dummy = ctx->shared.virtualWidth; + + if (ctx->colorTiling==1) + { + switch (ctx->bpp / 8) { + case 1: dummy = (ctx->shared.virtualWidth + 255) & ~255; break; + case 2: dummy = (ctx->shared.virtualWidth + 127) & ~127; break; + case 3: + case 4: dummy = (ctx->shared.virtualWidth + 63) & ~63; break; + } + } else { + switch (ctx->bpp / 8) { + case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break; + case 2: dummy = (ctx->shared.virtualWidth + 31) & ~31; break; + case 3: + case 4: dummy = (ctx->shared.virtualWidth + 15) & ~15; break; + } + } + + ctx->shared.virtualWidth = dummy; + ctx->shared.Width = dummy; + } + + fprintf(stderr,"shared virtual width is %d\n", ctx->shared.virtualWidth); + ctx->driverPrivate = (void *)info; + + info->gartFastWrite = RADEON_DEFAULT_AGP_FAST_WRITE; + info->gartSize = RADEON_DEFAULT_AGP_SIZE; + info->gartTexSize = RADEON_DEFAULT_AGP_TEX_SIZE; + info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; + info->ringSize = RADEON_DEFAULT_RING_SIZE; + info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP; + info->colorTiling = ctx->colorTiling; + + info->Chipset = ctx->chipset; + + if (!get_chipfamily_from_chipset( info )) { + fprintf(stderr, "Unknown or non-radeon chipset -- cannot continue\n"); + fprintf(stderr, "==> Verify PCI BusID is correct in miniglx.conf\n"); + return 0; + } + + info->frontPitch = ctx->shared.virtualWidth; + info->LinearAddr = ctx->FBStart & 0xfc000000; + + + if (!RADEONScreenInit( ctx, info )) + return 0; + + + return 1; +} + + +/** + * \brief The screen is being closed, so clean up any state and free any + * resources used by the DRI. + * + * \param ctx display handle. + * + * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver + * private data. + */ +static void radeonHaltFBDev( DRIDriverContext *ctx ) +{ + drmUnmap( ctx->pSAREA, ctx->shared.SAREASize ); + drmClose(ctx->drmFD); + + if (ctx->driverPrivate) { + free(ctx->driverPrivate); + ctx->driverPrivate = 0; + } +} + + +extern void radeonNotifyFocus( int ); + +/** + * \brief Exported driver interface for Mini GLX. + * + * \sa DRIDriverRec. + */ +const struct DRIDriverRec __driDriver = { + radeonValidateMode, + radeonPostValidateMode, + radeonInitFBDev, + radeonHaltFBDev, + RADEONEngineShutdown, + RADEONEngineRestore, +#ifndef _EMBEDDED + 0, +#else + radeonNotifyFocus, +#endif +}; diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_dri.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_dri.h new file mode 100644 index 00000000000..ecd53233394 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_dri.h @@ -0,0 +1,116 @@ +/** + * \file server/radeon_dri.h + * \brief Radeon server-side structures. + * + * \author Kevin E. Martin + * \author Rickard E. Faith + */ + +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h,v 1.3 2002/04/24 16:20:40 martin Exp $ */ + +#ifndef _RADEON_DRI_ +#define _RADEON_DRI_ + +#include "xf86drm.h" +#include "drm.h" +#include "radeon_drm.h" + +/* DRI Driver defaults */ +#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO +#define RADEON_DEFAULT_CP_BM_MODE RADEON_CSQ_PRIBM_INDBM +#define RADEON_DEFAULT_AGP_MODE 1 +#define RADEON_DEFAULT_AGP_FAST_WRITE 0 +#define RADEON_DEFAULT_AGP_SIZE 8 /* MB (must be 2^n and > 4MB) */ +#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */ +#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */ +#define RADEON_DEFAULT_AGP_TEX_SIZE 1 /* MB (must be page aligned) */ +#define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */ +#define RADEON_DEFAULT_PAGE_FLIP 0 /* page flipping diabled */ +#define RADEON_BUFFER_ALIGN 0x00000fff + +/** + * \brief Radeon DRI driver private data. + */ +typedef struct { + /** + * \name DRI screen private data + */ + /*@{*/ + int deviceID; /**< \brief PCI device ID */ + int width; /**< \brief width in pixels of display */ + int height; /**< \brief height in scanlines of display */ + int depth; /**< \brief depth of display (8, 15, 16, 24) */ + int bpp; /**< \brief bit depth of display (8, 16, 24, 32) */ + + int IsPCI; /**< \brief is current card a PCI card? */ + int AGPMode; /**< \brief AGP mode */ + + int frontOffset; /**< \brief front buffer offset */ + int frontPitch; /**< \brief front buffer pitch */ + int backOffset; /**< \brief shared back buffer offset */ + int backPitch; /**< \brief shared back buffer pitch */ + int depthOffset; /**< \brief shared depth buffer offset */ + int depthPitch; /**< \brief shared depth buffer pitch */ + int textureOffset; /**< \brief start of texture data in frame buffer */ + int textureSize; /**< \brief size of texture date */ + int log2TexGran; /**< \brief log2 texture granularity */ + /*@}*/ + + /** + * \name MMIO register data + */ + /*@{*/ + drm_handle_t registerHandle; /**< \brief MMIO register map size */ + drmSize registerSize; /**< \brief MMIO register map handle */ + /*@}*/ + + /** + * \name CP in-memory status information + */ + /*@{*/ + drm_handle_t statusHandle; /**< \brief status map handle */ + drmSize statusSize; /**< \brief status map size */ + /*@}*/ + + /** + * \name CP AGP Texture data + */ + /*@{*/ + drm_handle_t gartTexHandle; /**< \brief AGP texture area map handle */ + drmSize gartTexMapSize; /**< \brief AGP texture area map size */ + int log2GARTTexGran; /**< \brief AGP texture granularity in log base 2 */ + int gartTexOffset; /**< \brief AGP texture area offset in AGP space */ + /*@}*/ + + unsigned int sarea_priv_offset; /**< \brief offset of the private SAREA data*/ +} RADEONDRIRec, *RADEONDRIPtr; + +#endif diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_egl.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_egl.c new file mode 100644 index 00000000000..2f6ea559032 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_egl.c @@ -0,0 +1,1088 @@ +/* + * EGL driver for radeon_dri.so + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "eglconfig.h" +#include "eglcontext.h" +#include "egldisplay.h" +#include "egldriver.h" +#include "eglglobals.h" +#include "egllog.h" +#include "eglmode.h" +#include "eglscreen.h" +#include "eglsurface.h" +#include "egldri.h" + +#include "mtypes.h" +#include "memops.h" +#include "drm.h" +#include "drm_sarea.h" +#include "radeon_drm.h" +#include "radeon_dri.h" +#include "radeon.h" + +static size_t radeon_drm_page_size; + +/** + * radeon driver-specific driver class derived from _EGLDriver + */ +typedef struct radeon_driver +{ + _EGLDriver Base; /* base class/object */ + GLuint radeonStuff; +} radeonDriver; + +static int +RADEONSetParam(driDisplay *disp, int param, int value) +{ + drm_radeon_setparam_t sp; + int ret; + + memset(&sp, 0, sizeof(sp)); + sp.param = param; + sp.value = value; + + if ((ret=drmCommandWrite(disp->drmFD, DRM_RADEON_SETPARAM, &sp, sizeof(sp)))) { + fprintf(stderr,"Set param failed\n", ret); + return -1; + } + + return 0; +} + +static int +RADEONCheckDRMVersion(driDisplay *disp, RADEONInfoPtr info) +{ + drmVersionPtr version; + + version = drmGetVersion(disp->drmFD); + if (version) { + int req_minor, req_patch; + + /* Need 1.21.x for card type detection getparam + */ + req_minor = 21; + req_patch = 0; + + if (version->version_major != 1 || + version->version_minor < req_minor || + (version->version_minor == req_minor && + version->version_patchlevel < req_patch)) { + /* Incompatible drm version */ + fprintf(stderr, + "[dri] RADEONDRIScreenInit failed because of a version " + "mismatch.\n" + "[dri] radeon.o kernel module version is %d.%d.%d " + "but version 1.%d.%d or newer is needed.\n" + "[dri] Disabling DRI.\n", + version->version_major, + version->version_minor, + version->version_patchlevel, + req_minor, + req_patch); + drmFreeVersion(version); + return 0; + } + + info->drmMinor = version->version_minor; + drmFreeVersion(version); + } + + return 1; +} + + +/** + * \brief Compute base 2 logarithm. + * + * \param val value. + * + * \return base 2 logarithm of \p val. + */ +static int RADEONMinBits(int val) +{ + int bits; + + if (!val) return 1; + for (bits = 0; val; val >>= 1, ++bits); + return bits; +} + + +/* Initialize the PCI GART state. Request memory for use in PCI space, + * and initialize the Radeon registers to point to that memory. + */ +static int RADEONDRIPciInit(driDisplay *disp, RADEONInfoPtr info) +{ + int ret; + int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL; + int s, l; + + ret = drmScatterGatherAlloc(disp->drmFD, info->gartSize*1024*1024, + &info->gartMemHandle); + if (ret < 0) { + fprintf(stderr, "[pci] Out of memory (%d)\n", ret); + return 0; + } + fprintf(stderr, + "[pci] %d kB allocated with handle 0x%04lx\n", + info->gartSize*1024, (long) info->gartMemHandle); + + info->gartOffset = 0; + + /* Initialize the CP ring buffer data */ + info->ringStart = info->gartOffset; + info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size; + + info->ringReadOffset = info->ringStart + info->ringMapSize; + info->ringReadMapSize = radeon_drm_page_size; + + /* Reserve space for vertex/indirect buffers */ + info->bufStart = info->ringReadOffset + info->ringReadMapSize; + info->bufMapSize = info->bufSize*1024*1024; + + /* Reserve the rest for AGP textures */ + info->gartTexStart = info->bufStart + info->bufMapSize; + s = (info->gartSize*1024*1024 - info->gartTexStart); + l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + info->gartTexMapSize = (s >> l) << l; + info->log2GARTTexGran = l; + + if (drmAddMap(disp->drmFD, info->ringStart, info->ringMapSize, + DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) { + fprintf(stderr, + "[pci] Could not add ring mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] ring handle = 0x%08lx\n", info->ringHandle); + + if (drmAddMap(disp->drmFD, info->ringReadOffset, info->ringReadMapSize, + DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) { + fprintf(stderr, + "[pci] Could not add ring read ptr mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] ring read ptr handle = 0x%08lx\n", + info->ringReadPtrHandle); + + if (drmAddMap(disp->drmFD, info->bufStart, info->bufMapSize, + DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) { + fprintf(stderr, + "[pci] Could not add vertex/indirect buffers mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] vertex/indirect buffers handle = 0x%08lx\n", + info->bufHandle); + + if (drmAddMap(disp->drmFD, info->gartTexStart, info->gartTexMapSize, + DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) { + fprintf(stderr, + "[pci] Could not add GART texture map mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] GART texture map handle = 0x%08lx\n", + info->gartTexHandle); + + return 1; +} + + +/** + * \brief Initialize the AGP state + * + * \param ctx display handle. + * \param info driver private data. + * + * \return one on success, or zero on failure. + * + * Acquires and enables the AGP device. Reserves memory in the AGP space for + * the ring buffer, vertex buffers and textures. Initialize the Radeon + * registers to point to that memory and add client mappings. + */ +static int RADEONDRIAgpInit( driDisplay *disp, RADEONInfoPtr info) +{ + int mode, ret; + int s, l; + int agpmode = 1; + + if (drmAgpAcquire(disp->drmFD) < 0) { + fprintf(stderr, "[gart] AGP not available\n"); + return 0; + } + + mode = drmAgpGetMode(disp->drmFD); /* Default mode */ + /* Disable fast write entirely - too many lockups. + */ + mode &= ~RADEON_AGP_MODE_MASK; + switch (agpmode) { + case 4: mode |= RADEON_AGP_4X_MODE; + case 2: mode |= RADEON_AGP_2X_MODE; + case 1: default: mode |= RADEON_AGP_1X_MODE; + } + + if (drmAgpEnable(disp->drmFD, mode) < 0) { + fprintf(stderr, "[gart] AGP not enabled\n"); + drmAgpRelease(disp->drmFD); + return 0; + } + +#if 0 + /* Workaround for some hardware bugs */ + if (info->ChipFamily < CHIP_FAMILY_R200) + OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000); +#endif + info->gartOffset = 0; + + if ((ret = drmAgpAlloc(disp->drmFD, info->gartSize*1024*1024, 0, NULL, + &info->gartMemHandle)) < 0) { + fprintf(stderr, "[gart] Out of memory (%d)\n", ret); + drmAgpRelease(disp->drmFD); + return 0; + } + fprintf(stderr, + "[gart] %d kB allocated with handle 0x%08x\n", + info->gartSize*1024, (unsigned)info->gartMemHandle); + + if (drmAgpBind(disp->drmFD, + info->gartMemHandle, info->gartOffset) < 0) { + fprintf(stderr, "[gart] Could not bind\n"); + drmAgpFree(disp->drmFD, info->gartMemHandle); + drmAgpRelease(disp->drmFD); + return 0; + } + + /* Initialize the CP ring buffer data */ + info->ringStart = info->gartOffset; + info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size; + + info->ringReadOffset = info->ringStart + info->ringMapSize; + info->ringReadMapSize = radeon_drm_page_size; + + /* Reserve space for vertex/indirect buffers */ + info->bufStart = info->ringReadOffset + info->ringReadMapSize; + info->bufMapSize = info->bufSize*1024*1024; + + /* Reserve the rest for AGP textures */ + info->gartTexStart = info->bufStart + info->bufMapSize; + s = (info->gartSize*1024*1024 - info->gartTexStart); + l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + info->gartTexMapSize = (s >> l) << l; + info->log2GARTTexGran = l; + + if (drmAddMap(disp->drmFD, info->ringStart, info->ringMapSize, + DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) { + fprintf(stderr, "[gart] Could not add ring mapping\n"); + return 0; + } + fprintf(stderr, "[gart] ring handle = 0x%08lx\n", info->ringHandle); + + + if (drmAddMap(disp->drmFD, info->ringReadOffset, info->ringReadMapSize, + DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) { + fprintf(stderr, + "[gart] Could not add ring read ptr mapping\n"); + return 0; + } + + fprintf(stderr, + "[gart] ring read ptr handle = 0x%08lx\n", + info->ringReadPtrHandle); + + if (drmAddMap(disp->drmFD, info->bufStart, info->bufMapSize, + DRM_AGP, 0, &info->bufHandle) < 0) { + fprintf(stderr, + "[gart] Could not add vertex/indirect buffers mapping\n"); + return 0; + } + fprintf(stderr, + "[gart] vertex/indirect buffers handle = 0x%08lx\n", + info->bufHandle); + + if (drmAddMap(disp->drmFD, info->gartTexStart, info->gartTexMapSize, + DRM_AGP, 0, &info->gartTexHandle) < 0) { + fprintf(stderr, + "[gart] Could not add AGP texture map mapping\n"); + return 0; + } + fprintf(stderr, + "[gart] AGP texture map handle = 0x%08lx\n", + info->gartTexHandle); + + return 1; +} + + +/** + * Initialize all the memory-related fields of the RADEONInfo object. + * This includes the various 'offset' and 'size' fields. + */ +static int +RADEONMemoryInit(driDisplay *disp, RADEONInfoPtr info) +{ + int width_bytes = disp->virtualWidth * disp->cpp; + int cpp = disp->cpp; + int bufferSize = ((disp->virtualHeight * width_bytes + + RADEON_BUFFER_ALIGN) + & ~RADEON_BUFFER_ALIGN); + int depthSize = ((((disp->virtualHeight+15) & ~15) * width_bytes + + RADEON_BUFFER_ALIGN) + & ~RADEON_BUFFER_ALIGN); + int l; + int pcie_gart_table_size = 0; + + info->frontOffset = 0; + info->frontPitch = disp->virtualWidth; + + if (disp->card_type==RADEON_CARD_PCIE) + pcie_gart_table_size = RADEON_PCIGART_TABLE_SIZE; + + /* Front, back and depth buffers - everything else texture?? + */ + info->textureSize = disp->fbSize - pcie_gart_table_size - 2 * bufferSize - depthSize; + + if (info->textureSize < 0) + return 0; + + l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + + /* Round the texture size up to the nearest whole number of + * texture regions. Again, be greedy about this, don't + * round down. + */ + info->log2TexGran = l; + info->textureSize = (info->textureSize >> l) << l; + + /* Set a minimum usable local texture heap size. This will fit + * two 256x256x32bpp textures. + */ + if (info->textureSize < 512 * 1024) { + info->textureOffset = 0; + info->textureSize = 0; + } + + /* Reserve space for textures */ + info->textureOffset = ((disp->fbSize - pcie_gart_table_size - info->textureSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + + /* Reserve space for the shared depth + * buffer. + */ + info->depthOffset = ((info->textureOffset - depthSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + info->depthPitch = disp->virtualWidth; + + info->backOffset = ((info->depthOffset - bufferSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + info->backPitch = disp->virtualWidth; + + if (pcie_gart_table_size) + info->pcieGartTableOffset = disp->fbSize - pcie_gart_table_size; + + fprintf(stderr, + "Will use back buffer at offset 0x%x, pitch %d\n", + info->backOffset, info->backPitch); + fprintf(stderr, + "Will use depth buffer at offset 0x%x, pitch %d\n", + info->depthOffset, info->depthPitch); + fprintf(stderr, + "Will use %d kb for textures at offset 0x%x\n", + info->textureSize/1024, info->textureOffset); + if (pcie_gart_table_size) + { + fprintf(stderr, + "Will use %d kb for PCIE GART Table at offset 0x%x\n", + pcie_gart_table_size/1024, info->pcieGartTableOffset); + } + + /* XXX I don't think these are needed. */ +#if 0 + info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) | + (info->frontOffset >> 10)); + + info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) | + (info->backOffset >> 10)); + + info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) | + (info->depthOffset >> 10)); +#endif + + if (pcie_gart_table_size) + RADEONSetParam(disp, RADEON_SETPARAM_PCIGART_LOCATION, info->pcieGartTableOffset); + + return 1; +} + + +/** + * \brief Initialize the kernel data structures and enable the CP engine. + * + * \param ctx display handle. + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * This function is a wrapper around the DRM_RADEON_CP_INIT command, passing + * all the parameters in a drm_radeon_init_t structure. + */ +static int RADEONDRIKernelInit( driDisplay *disp, + RADEONInfoPtr info) +{ + int cpp = disp->bpp / 8; + drm_radeon_init_t drmInfo; + int ret; + + memset(&drmInfo, 0, sizeof(drmInfo)); + + if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) + drmInfo.func = RADEON_INIT_R300_CP; + else if ( (info->ChipFamily == CHIP_FAMILY_R200) || + (info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_M9) || + (info->ChipFamily == CHIP_FAMILY_RV280) ) + drmInfo.func = RADEON_INIT_R200_CP; + else + drmInfo.func = RADEON_INIT_CP; + + /* This is the struct passed to the kernel module for its initialization */ + /* XXX problem here: + * The front/back/depth_offset/pitch fields may change depending upon + * which drawing surface we're using!!! They can't be set just once + * during initialization. + * Looks like we'll need a new ioctl to update these fields for drawing + * to other surfaces... + */ + drmInfo.sarea_priv_offset = sizeof(drm_sarea_t); + drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE; + drmInfo.gart_size = info->gartSize*1024*1024; + drmInfo.ring_size = info->ringSize*1024*1024; + drmInfo.usec_timeout = 1000; + drmInfo.fb_bpp = disp->bpp; + drmInfo.depth_bpp = disp->bpp; + drmInfo.front_offset = info->frontOffset; + drmInfo.front_pitch = info->frontPitch * cpp; + drmInfo.back_offset = info->backOffset; + drmInfo.back_pitch = info->backPitch * cpp; + drmInfo.depth_offset = info->depthOffset; + drmInfo.depth_pitch = info->depthPitch * cpp; + drmInfo.ring_offset = info->ringHandle; + drmInfo.ring_rptr_offset = info->ringReadPtrHandle; + drmInfo.buffers_offset = info->bufHandle; + drmInfo.gart_textures_offset = info->gartTexHandle; + + ret = drmCommandWrite(disp->drmFD, DRM_RADEON_CP_INIT, &drmInfo, + sizeof(drm_radeon_init_t)); + + return ret >= 0; +} + + +/** + * \brief Add a map for the vertex buffers that will be accessed by any + * DRI-based clients. + * + * \param ctx display handle. + * \param info driver private data. + * + * \return one on success, or zero on failure. + * + * Calls drmAddBufs() with the previously allocated vertex buffers. + */ +static int RADEONDRIBufInit( driDisplay *disp, RADEONInfoPtr info ) +{ + /* Initialize vertex buffers */ + info->bufNumBufs = drmAddBufs(disp->drmFD, + info->bufMapSize / RADEON_BUFFER_SIZE, + RADEON_BUFFER_SIZE, + (disp->card_type!=RADEON_CARD_AGP) ? DRM_SG_BUFFER : DRM_AGP_BUFFER, + info->bufStart); + + if (info->bufNumBufs <= 0) { + fprintf(stderr, + "[drm] Could not create vertex/indirect buffers list\n"); + return 0; + } + fprintf(stderr, + "[drm] Added %d %d byte vertex/indirect buffers\n", + info->bufNumBufs, RADEON_BUFFER_SIZE); + + return 1; +} + + +/** + * \brief Install an IRQ handler. + * + * \param disp display handle. + * \param info driver private data. + * + * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to + * IRQ-free operation on failure. + */ +static void RADEONDRIIrqInit(driDisplay *disp, RADEONInfoPtr info) +{ + if ((drmCtlInstHandler(disp->drmFD, 0)) != 0) + fprintf(stderr, "[drm] failure adding irq handler, " + "there is a device already using that irq\n" + "[drm] falling back to irq-free operation\n"); +} + + +/** + * \brief Initialize the AGP heap. + * + * \param disp display handle. + * \param info driver private data. + * + * This function is a wrapper around the DRM_RADEON_INIT_HEAP command, passing + * all the parameters in a drm_radeon_mem_init_heap structure. + */ +static void RADEONDRIAgpHeapInit(driDisplay *disp, + RADEONInfoPtr info) +{ + drm_radeon_mem_init_heap_t drmHeap; + + /* Start up the simple memory manager for gart space */ + drmHeap.region = RADEON_MEM_REGION_GART; + drmHeap.start = 0; + drmHeap.size = info->gartTexMapSize; + + if (drmCommandWrite(disp->drmFD, DRM_RADEON_INIT_HEAP, + &drmHeap, sizeof(drmHeap))) { + fprintf(stderr, + "[drm] Failed to initialized gart heap manager\n"); + } else { + fprintf(stderr, + "[drm] Initialized kernel gart heap manager, %d\n", + info->gartTexMapSize); + } +} + +static int RADEONGetCardType(driDisplay *disp, RADEONInfoPtr info) +{ + drm_radeon_getparam_t gp; + int ret; + + gp.param = RADEON_PARAM_CARD_TYPE; + gp.value = &disp->card_type; + + ret=drmCommandWriteRead(disp->drmFD, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); + if (ret) { + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_CARD_TYPE) : %d\n", ret); + return -1; + } + + return disp->card_type; +} + +/** + * Called at the start of each server generation. + * + * \param disp display handle. + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * Performs static frame buffer allocation. Opens the DRM device and add maps + * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more + * information. Creates a \e server context to grab the lock for the + * initialization ioctls and calls the other initilization functions in this + * file. Starts the CP engine via the DRM_RADEON_CP_START command. + * + * Setups a RADEONDRIRec structure to be passed to radeon_dri.so for its + * initialization. + */ +static int +RADEONScreenInit( driDisplay *disp, RADEONInfoPtr info, + RADEONDRIPtr pRADEONDRI) +{ + int i, err; + + /* XXX this probably isn't needed here */ + { + int width_bytes = (disp->virtualWidth * disp->cpp); + int maxy = disp->fbSize / width_bytes; + + if (maxy <= disp->virtualHeight * 3) { + _eglLog(_EGL_WARNING, + "Static buffer allocation failed -- " + "need at least %d kB video memory (have %d kB)\n", + (disp->virtualWidth * disp->virtualHeight * + disp->cpp * 3 + 1023) / 1024, + disp->fbSize / 1024); + return 0; + } + } + + /* Memory manager setup */ + if (!RADEONMemoryInit(disp, info)) { + return 0; + } + + /* Create a 'server' context so we can grab the lock for + * initialization ioctls. + */ + if ((err = drmCreateContext(disp->drmFD, &disp->serverContext)) != 0) { + _eglLog(_EGL_WARNING, "%s: drmCreateContext failed %d\n", + __FUNCTION__, err); + return 0; + } + + DRM_LOCK(disp->drmFD, disp->pSAREA, disp->serverContext, 0); + + /* Initialize the kernel data structures */ + if (!RADEONDRIKernelInit(disp, info)) { + _eglLog(_EGL_WARNING, "RADEONDRIKernelInit failed\n"); + DRM_UNLOCK(disp->drmFD, disp->pSAREA, disp->serverContext); + return 0; + } + + /* Initialize the vertex buffers list */ + if (!RADEONDRIBufInit(disp, info)) { + fprintf(stderr, "RADEONDRIBufInit failed\n"); + DRM_UNLOCK(disp->drmFD, disp->pSAREA, disp->serverContext); + return 0; + } + + /* Initialize IRQ */ + RADEONDRIIrqInit(disp, info); + + /* Initialize kernel gart memory manager */ + RADEONDRIAgpHeapInit(disp, info); + + /* Initialize the SAREA private data structure */ + { + drm_radeon_sarea_t *pSAREAPriv; + pSAREAPriv = (drm_radeon_sarea_t *)(((char*)disp->pSAREA) + + sizeof(drm_sarea_t)); + memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); + pSAREAPriv->pfState = info->page_flip_enable; + } + + for ( i = 0;; i++ ) { + drmMapType type; + drmMapFlags flags; + drm_handle_t handle, offset; + drmSize size; + int rc, mtrr; + + if ( ( rc = drmGetMap( disp->drmFD, i, &offset, &size, &type, &flags, &handle, &mtrr ) ) != 0 ) + break; + if ( type == DRM_REGISTERS ) { + pRADEONDRI->registerHandle = offset; + pRADEONDRI->registerSize = size; + break; + } + } + /* Quick hack to clear the front & back buffers. Could also use + * the clear ioctl to do this, but would need to setup hw state + * first. + */ + drimemsetio((char *)disp->pFB + info->frontOffset, + 0xEE, + info->frontPitch * disp->cpp * disp->virtualHeight ); + + drimemsetio((char *)disp->pFB + info->backOffset, + 0x30, + info->backPitch * disp->cpp * disp->virtualHeight ); + + + /* This is the struct passed to radeon_dri.so for its initialization */ + pRADEONDRI->deviceID = info->Chipset; + pRADEONDRI->width = disp->virtualWidth; + pRADEONDRI->height = disp->virtualHeight; + pRADEONDRI->depth = disp->bpp; /* XXX: depth */ + pRADEONDRI->bpp = disp->bpp; + pRADEONDRI->IsPCI = (disp->card_type != RADEON_CARD_AGP);; + pRADEONDRI->frontOffset = info->frontOffset; + pRADEONDRI->frontPitch = info->frontPitch; + pRADEONDRI->backOffset = info->backOffset; + pRADEONDRI->backPitch = info->backPitch; + pRADEONDRI->depthOffset = info->depthOffset; + pRADEONDRI->depthPitch = info->depthPitch; + pRADEONDRI->textureOffset = info->textureOffset; + pRADEONDRI->textureSize = info->textureSize; + pRADEONDRI->log2TexGran = info->log2TexGran; + pRADEONDRI->statusHandle = info->ringReadPtrHandle; + pRADEONDRI->statusSize = info->ringReadMapSize; + pRADEONDRI->gartTexHandle = info->gartTexHandle; + pRADEONDRI->gartTexMapSize = info->gartTexMapSize; + pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran; + pRADEONDRI->gartTexOffset = info->gartTexStart; + pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t); + + /* Don't release the lock now - let the VT switch handler do it. */ + + return 1; +} + + +/** + * \brief Get Radeon chip family from chipset number. + * + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * Called by radeonInitFBDev() to set RADEONInfoRec::ChipFamily + * according to the value of RADEONInfoRec::Chipset. Fails if the + * chipset is unrecognized or not appropriate for this driver (i.e., not + * an r100 style radeon) + */ +static int get_chipfamily_from_chipset( RADEONInfoPtr info ) +{ + switch (info->Chipset) { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + info->ChipFamily = CHIP_FAMILY_M6; + break; + + case PCI_CHIP_RADEON_QY: + case PCI_CHIP_RADEON_QZ: + info->ChipFamily = CHIP_FAMILY_VE; + break; + + case PCI_CHIP_R200_QL: + case PCI_CHIP_R200_QN: + case PCI_CHIP_R200_QO: + case PCI_CHIP_R200_Ql: + case PCI_CHIP_R200_BB: + info->ChipFamily = CHIP_FAMILY_R200; + break; + + case PCI_CHIP_RV200_QW: /* RV200 desktop */ + case PCI_CHIP_RV200_QX: + info->ChipFamily = CHIP_FAMILY_RV200; + break; + + case PCI_CHIP_RADEON_LW: + case PCI_CHIP_RADEON_LX: + info->ChipFamily = CHIP_FAMILY_M7; + break; + + case PCI_CHIP_RV250_Id: + case PCI_CHIP_RV250_Ie: + case PCI_CHIP_RV250_If: + case PCI_CHIP_RV250_Ig: + info->ChipFamily = CHIP_FAMILY_RV250; + break; + + case PCI_CHIP_RV250_Ld: + case PCI_CHIP_RV250_Le: + case PCI_CHIP_RV250_Lf: + case PCI_CHIP_RV250_Lg: + info->ChipFamily = CHIP_FAMILY_M9; + break; + + case PCI_CHIP_RV280_Y_: + case PCI_CHIP_RV280_Ya: + case PCI_CHIP_RV280_Yb: + case PCI_CHIP_RV280_Yc: + info->ChipFamily = CHIP_FAMILY_RV280; + break; + + case PCI_CHIP_R300_ND: + case PCI_CHIP_R300_NE: + case PCI_CHIP_R300_NF: + case PCI_CHIP_R300_NG: + info->ChipFamily = CHIP_FAMILY_R300; + break; + + case PCI_CHIP_RV370_5460: + info->ChipFamily = CHIP_FAMILY_RV380; + break; + + default: + /* Original Radeon/7200 */ + info->ChipFamily = CHIP_FAMILY_RADEON; + } + + return 1; +} + + +/** + * \brief Initialize the framebuffer device mode + * + * \param disp display handle. + * + * \return one on success, or zero on failure. + * + * Fills in \p info with some default values and some information from \p disp + * and then calls RADEONScreenInit() for the screen initialization. + * + * Before exiting clears the framebuffer memory accessing it directly. + */ +static int radeonInitFBDev( driDisplay *disp, RADEONDRIPtr pRADEONDRI ) +{ + int err; + RADEONInfoPtr info = calloc(1, sizeof(*info)); + + disp->driverPrivate = (void *)info; + + info->gartFastWrite = RADEON_DEFAULT_AGP_FAST_WRITE; + info->gartSize = RADEON_DEFAULT_AGP_SIZE; + info->gartTexSize = RADEON_DEFAULT_AGP_TEX_SIZE; + info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; + info->ringSize = RADEON_DEFAULT_RING_SIZE; + info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP; + + fprintf(stderr, + "Using %d MB AGP aperture\n", info->gartSize); + fprintf(stderr, + "Using %d MB for the ring buffer\n", info->ringSize); + fprintf(stderr, + "Using %d MB for vertex/indirect buffers\n", info->bufSize); + fprintf(stderr, + "Using %d MB for AGP textures\n", info->gartTexSize); + fprintf(stderr, + "page flipping %sabled\n", info->page_flip_enable?"en":"dis"); + + info->Chipset = disp->chipset; + + if (!get_chipfamily_from_chipset( info )) { + fprintf(stderr, "Unknown or non-radeon chipset -- cannot continue\n"); + fprintf(stderr, "==> Verify PCI BusID is correct in miniglx.conf\n"); + return 0; + } +#if 0 + if (info->ChipFamily >= CHIP_FAMILY_R300) { + fprintf(stderr, + "Direct rendering not yet supported on " + "Radeon 9700 and newer cards\n"); + return 0; + } +#endif + +#if 00 + /* don't seem to need this here */ + info->frontPitch = disp->virtualWidth; +#endif + + /* Check the radeon DRM version */ + if (!RADEONCheckDRMVersion(disp, info)) { + return 0; + } + + if (RADEONGetCardType(disp, info)<0) + return 0; + + if (disp->card_type!=RADEON_CARD_AGP) { + /* Initialize PCI */ + if (!RADEONDRIPciInit(disp, info)) + return 0; + } + else { + /* Initialize AGP */ + if (!RADEONDRIAgpInit(disp, info)) + return 0; + } + + if (!RADEONScreenInit( disp, info, pRADEONDRI)) + return 0; + + /* Initialize and start the CP if required */ + if ((err = drmCommandNone(disp->drmFD, DRM_RADEON_CP_START)) != 0) { + fprintf(stderr, "%s: CP start %d\n", __FUNCTION__, err); + return 0; + } + + return 1; +} + + +/** + * Create list of all supported surface configs, attach list to the display. + */ +static EGLBoolean +radeonFillInConfigs(_EGLDisplay *disp, unsigned pixel_bits, + unsigned depth_bits, + unsigned stencil_bits, GLboolean have_back_buffer) +{ + _EGLConfig *configs; + _EGLConfig *c; + unsigned int i, num_configs; + unsigned int depth_buffer_factor; + unsigned int back_buffer_factor; + GLenum fb_format; + GLenum fb_type; + + /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy + * enough to add support. Basically, if a context is created with an + * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping + * will never be used. + */ + static const GLenum back_buffer_modes[] = { + GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ + }; + + u_int8_t depth_bits_array[2]; + u_int8_t stencil_bits_array[2]; + + depth_bits_array[0] = depth_bits; + depth_bits_array[1] = depth_bits; + + /* Just like with the accumulation buffer, always provide some modes + * with a stencil buffer. It will be a sw fallback, but some apps won't + * care about that. + */ + stencil_bits_array[0] = 0; + stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; + + depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; + back_buffer_factor = (have_back_buffer) ? 2 : 1; + + num_configs = depth_buffer_factor * back_buffer_factor * 2; + + if (pixel_bits == 16) { + fb_format = GL_RGB; + fb_type = GL_UNSIGNED_SHORT_5_6_5; + } else { + fb_format = GL_RGBA; + fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; + } + + configs = calloc(sizeof(*configs), num_configs); + c = configs; + if (!_eglFillInConfigs(c, fb_format, fb_type, + depth_bits_array, stencil_bits_array, + depth_buffer_factor, + back_buffer_modes, back_buffer_factor, + GLX_TRUE_COLOR)) { + fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", + __func__, __LINE__); + return EGL_FALSE; + } + + /* Mark the visual as slow if there are "fake" stencil bits. + */ + for (i = 0, c = configs; i < num_configs; i++, c++) { + int stencil = GET_CONFIG_ATTRIB(c, EGL_STENCIL_SIZE); + if ((stencil != 0) && (stencil != stencil_bits)) { + SET_CONFIG_ATTRIB(c, EGL_CONFIG_CAVEAT, EGL_SLOW_CONFIG); + } + } + + for (i = 0, c = configs; i < num_configs; i++, c++) + _eglAddConfig(disp, c); + + free(configs); + + return EGL_TRUE; +} + + +/** + * Show the given surface on the named screen. + * If surface is EGL_NO_SURFACE, disable the screen's output. + */ +static EGLBoolean +radeonShowScreenSurfaceMESA(_EGLDriver *drv, EGLDisplay dpy, EGLScreenMESA screen, + EGLSurface surface, EGLModeMESA m) +{ + EGLBoolean b = _eglDRIShowScreenSurfaceMESA(drv, dpy, screen, surface, m); + return b; +} + + +/** + * Called via eglInitialize() by user. + */ +static EGLBoolean +radeonInitialize(_EGLDriver *drv, EGLDisplay dpy, EGLint *major, EGLint *minor) +{ + __DRIframebuffer framebuffer; + driDisplay *display; + + /* one-time init */ + radeon_drm_page_size = getpagesize(); + + if (!_eglDRIInitialize(drv, dpy, major, minor)) + return EGL_FALSE; + + display = Lookup_driDisplay(dpy); + + framebuffer.dev_priv_size = sizeof(RADEONDRIRec); + framebuffer.dev_priv = malloc(sizeof(RADEONDRIRec)); + + /* XXX we shouldn't hard-code values here! */ + /* we won't know the screen surface size until the user calls + * eglCreateScreenSurfaceMESA(). + */ +#if 0 + display->virtualWidth = 1024; + display->virtualHeight = 768; +#else + display->virtualWidth = 1280; + display->virtualHeight = 1024; +#endif + display->bpp = 32; + display->cpp = 4; + + if (!_eglDRIGetDisplayInfo(display)) + return EGL_FALSE; + + framebuffer.base = display->pFB; + framebuffer.width = display->virtualWidth; + framebuffer.height = display->virtualHeight; + framebuffer.stride = display->virtualWidth; + framebuffer.size = display->fbSize; + radeonInitFBDev( display, framebuffer.dev_priv ); + + if (!_eglDRICreateDisplay(display, &framebuffer)) + return EGL_FALSE; + + if (!_eglDRICreateScreens(display)) + return EGL_FALSE; + + /* create a variety of both 32 and 16-bit configurations */ + radeonFillInConfigs(&display->Base, 32, 24, 8, GL_TRUE); + radeonFillInConfigs(&display->Base, 16, 16, 0, GL_TRUE); + + drv->Initialized = EGL_TRUE; + return EGL_TRUE; +} + + +/** + * The bootstrap function. Return a new radeonDriver object and + * plug in API functions. + */ +_EGLDriver * +_eglMain(_EGLDisplay *dpy) +{ + radeonDriver *radeon; + + radeon = (radeonDriver *) calloc(1, sizeof(*radeon)); + if (!radeon) { + return NULL; + } + + /* First fill in the dispatch table with defaults */ + _eglDRIInitDriverFallbacks(&radeon->Base); + + /* then plug in our radeon-specific functions */ + radeon->Base.API.Initialize = radeonInitialize; + radeon->Base.API.ShowScreenSurfaceMESA = radeonShowScreenSurfaceMESA; + + return &radeon->Base; +} diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_macros.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_macros.h new file mode 100644 index 00000000000..60f0fa2d351 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_macros.h @@ -0,0 +1,129 @@ +/** + * \file server/radeon_macros.h + * \brief Macros for Radeon MMIO operation. + * + * \authors Kevin E. Martin + * \authors Rickard E. Faith + * \authors Alan Hourihane + */ + +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.20 2002/10/12 01:38:07 martin Exp $ */ + +#ifndef _RADEON_MACROS_H_ +#define _RADEON_MACROS_H_ + +#include + +# define MMIO_IN8(base, offset) \ + *(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) +# define MMIO_IN32(base, offset) \ + read_MMIO_LE32(base, offset) +# define MMIO_OUT8(base, offset, val) \ + *(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val) +# define MMIO_OUT32(base, offset, val) \ + *(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = CPU_TO_LE32(val) + + + /* Memory mapped register access macros */ +#define INREG8(addr) MMIO_IN8(RADEONMMIO, addr) +#define INREG(addr) MMIO_IN32(RADEONMMIO, addr) +#define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val) +#define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val) + +#define ADDRREG(addr) ((volatile GLuint *)(pointer)(RADEONMMIO + (addr))) + + +#define OUTREGP(addr, val, mask) \ +do { \ + GLuint tmp = INREG(addr); \ + tmp &= (mask); \ + tmp |= (val); \ + OUTREG(addr, tmp); \ +} while (0) + +#define INPLL(dpy, addr) RADEONINPLL(dpy, addr) + +#define OUTPLL(addr, val) \ +do { \ + OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | \ + RADEON_PLL_WR_EN)); \ + OUTREG(RADEON_CLOCK_CNTL_DATA, val); \ +} while (0) + +#define OUTPLLP(dpy, addr, val, mask) \ +do { \ + GLuint tmp = INPLL(dpy, addr); \ + tmp &= (mask); \ + tmp |= (val); \ + OUTPLL(addr, tmp); \ +} while (0) + +#define OUTPAL_START(idx) \ +do { \ + OUTREG8(RADEON_PALETTE_INDEX, (idx)); \ +} while (0) + +#define OUTPAL_NEXT(r, g, b) \ +do { \ + OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \ +} while (0) + +#define OUTPAL_NEXT_CARD32(v) \ +do { \ + OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \ +} while (0) + +#define OUTPAL(idx, r, g, b) \ +do { \ + OUTPAL_START((idx)); \ + OUTPAL_NEXT((r), (g), (b)); \ +} while (0) + +#define INPAL_START(idx) \ +do { \ + OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \ +} while (0) + +#define INPAL_NEXT() INREG(RADEON_PALETTE_DATA) + +#define PAL_SELECT(idx) \ +do { \ + if (!idx) { \ + OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ + (GLuint)~RADEON_DAC2_PALETTE_ACC_CTL); \ + } else { \ + OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \ + RADEON_DAC2_PALETTE_ACC_CTL); \ + } \ +} while (0) + + +#endif diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_reg.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_reg.h new file mode 100644 index 00000000000..4dcce638460 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r200/server/radeon_reg.h @@ -0,0 +1,2144 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.30 2003/10/07 22:47:12 martin Exp $ */ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * Rickard E. Faith + * Alan Hourihane + * + * References: + * + * !!!! FIXME !!!! + * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical + * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April + * 1999. + * + * !!!! FIXME !!!! + * RAGE 128 Software Development Manual (Technical Reference Manual P/N + * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. + * + */ + +/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h + * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT + * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ + +#ifndef _RADEON_REG_H_ +#define _RADEON_REG_H_ + + /* Registers for 2D/Video/Overlay */ +#define RADEON_ADAPTER_ID 0x0f2c /* PCI */ +#define RADEON_AGP_BASE 0x0170 +#define RADEON_AGP_CNTL 0x0174 +# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) +# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) +# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) +# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) +# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) +# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) +# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) +# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) +#define RADEON_AGP_COMMAND 0x0f60 /* PCI */ +#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ +# define RADEON_AGP_ENABLE (1<<8) +#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ +#define RADEON_AGP_STATUS 0x0f5c /* PCI */ +# define RADEON_AGP_1X_MODE 0x01 +# define RADEON_AGP_2X_MODE 0x02 +# define RADEON_AGP_4X_MODE 0x04 +# define RADEON_AGP_FW_MODE 0x10 +# define RADEON_AGP_MODE_MASK 0x17 +#define RADEON_ATTRDR 0x03c1 /* VGA */ +#define RADEON_ATTRDW 0x03c0 /* VGA */ +#define RADEON_ATTRX 0x03c0 /* VGA */ +#define RADEON_AUX_SC_CNTL 0x1660 +# define RADEON_AUX1_SC_EN (1 << 0) +# define RADEON_AUX1_SC_MODE_OR (0 << 1) +# define RADEON_AUX1_SC_MODE_NAND (1 << 1) +# define RADEON_AUX2_SC_EN (1 << 2) +# define RADEON_AUX2_SC_MODE_OR (0 << 3) +# define RADEON_AUX2_SC_MODE_NAND (1 << 3) +# define RADEON_AUX3_SC_EN (1 << 4) +# define RADEON_AUX3_SC_MODE_OR (0 << 5) +# define RADEON_AUX3_SC_MODE_NAND (1 << 5) +#define RADEON_AUX1_SC_BOTTOM 0x1670 +#define RADEON_AUX1_SC_LEFT 0x1664 +#define RADEON_AUX1_SC_RIGHT 0x1668 +#define RADEON_AUX1_SC_TOP 0x166c +#define RADEON_AUX2_SC_BOTTOM 0x1680 +#define RADEON_AUX2_SC_LEFT 0x1674 +#define RADEON_AUX2_SC_RIGHT 0x1678 +#define RADEON_AUX2_SC_TOP 0x167c +#define RADEON_AUX3_SC_BOTTOM 0x1690 +#define RADEON_AUX3_SC_LEFT 0x1684 +#define RADEON_AUX3_SC_RIGHT 0x1688 +#define RADEON_AUX3_SC_TOP 0x168c +#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 +#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc + +#define RADEON_BASE_CODE 0x0f0b +#define RADEON_BIOS_0_SCRATCH 0x0010 +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +#define RADEON_BIOS_5_SCRATCH 0x0024 +#define RADEON_BIOS_6_SCRATCH 0x0028 +#define RADEON_BIOS_7_SCRATCH 0x002c +#define RADEON_BIOS_ROM 0x0f30 /* PCI */ +#define RADEON_BIST 0x0f0f /* PCI */ +#define RADEON_BRUSH_DATA0 0x1480 +#define RADEON_BRUSH_DATA1 0x1484 +#define RADEON_BRUSH_DATA10 0x14a8 +#define RADEON_BRUSH_DATA11 0x14ac +#define RADEON_BRUSH_DATA12 0x14b0 +#define RADEON_BRUSH_DATA13 0x14b4 +#define RADEON_BRUSH_DATA14 0x14b8 +#define RADEON_BRUSH_DATA15 0x14bc +#define RADEON_BRUSH_DATA16 0x14c0 +#define RADEON_BRUSH_DATA17 0x14c4 +#define RADEON_BRUSH_DATA18 0x14c8 +#define RADEON_BRUSH_DATA19 0x14cc +#define RADEON_BRUSH_DATA2 0x1488 +#define RADEON_BRUSH_DATA20 0x14d0 +#define RADEON_BRUSH_DATA21 0x14d4 +#define RADEON_BRUSH_DATA22 0x14d8 +#define RADEON_BRUSH_DATA23 0x14dc +#define RADEON_BRUSH_DATA24 0x14e0 +#define RADEON_BRUSH_DATA25 0x14e4 +#define RADEON_BRUSH_DATA26 0x14e8 +#define RADEON_BRUSH_DATA27 0x14ec +#define RADEON_BRUSH_DATA28 0x14f0 +#define RADEON_BRUSH_DATA29 0x14f4 +#define RADEON_BRUSH_DATA3 0x148c +#define RADEON_BRUSH_DATA30 0x14f8 +#define RADEON_BRUSH_DATA31 0x14fc +#define RADEON_BRUSH_DATA32 0x1500 +#define RADEON_BRUSH_DATA33 0x1504 +#define RADEON_BRUSH_DATA34 0x1508 +#define RADEON_BRUSH_DATA35 0x150c +#define RADEON_BRUSH_DATA36 0x1510 +#define RADEON_BRUSH_DATA37 0x1514 +#define RADEON_BRUSH_DATA38 0x1518 +#define RADEON_BRUSH_DATA39 0x151c +#define RADEON_BRUSH_DATA4 0x1490 +#define RADEON_BRUSH_DATA40 0x1520 +#define RADEON_BRUSH_DATA41 0x1524 +#define RADEON_BRUSH_DATA42 0x1528 +#define RADEON_BRUSH_DATA43 0x152c +#define RADEON_BRUSH_DATA44 0x1530 +#define RADEON_BRUSH_DATA45 0x1534 +#define RADEON_BRUSH_DATA46 0x1538 +#define RADEON_BRUSH_DATA47 0x153c +#define RADEON_BRUSH_DATA48 0x1540 +#define RADEON_BRUSH_DATA49 0x1544 +#define RADEON_BRUSH_DATA5 0x1494 +#define RADEON_BRUSH_DATA50 0x1548 +#define RADEON_BRUSH_DATA51 0x154c +#define RADEON_BRUSH_DATA52 0x1550 +#define RADEON_BRUSH_DATA53 0x1554 +#define RADEON_BRUSH_DATA54 0x1558 +#define RADEON_BRUSH_DATA55 0x155c +#define RADEON_BRUSH_DATA56 0x1560 +#define RADEON_BRUSH_DATA57 0x1564 +#define RADEON_BRUSH_DATA58 0x1568 +#define RADEON_BRUSH_DATA59 0x156c +#define RADEON_BRUSH_DATA6 0x1498 +#define RADEON_BRUSH_DATA60 0x1570 +#define RADEON_BRUSH_DATA61 0x1574 +#define RADEON_BRUSH_DATA62 0x1578 +#define RADEON_BRUSH_DATA63 0x157c +#define RADEON_BRUSH_DATA7 0x149c +#define RADEON_BRUSH_DATA8 0x14a0 +#define RADEON_BRUSH_DATA9 0x14a4 +#define RADEON_BRUSH_SCALE 0x1470 +#define RADEON_BRUSH_Y_X 0x1474 +#define RADEON_BUS_CNTL 0x0030 +# define RADEON_BUS_MASTER_DIS (1 << 6) +# define RADEON_BUS_RD_DISCARD_EN (1 << 24) +# define RADEON_BUS_RD_ABORT_EN (1 << 25) +# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) +# define RADEON_BUS_WRT_BURST (1 << 29) +# define RADEON_BUS_READ_BURST (1 << 30) +#define RADEON_BUS_CNTL1 0x0034 +# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) + +#define RADEON_CACHE_CNTL 0x1724 +#define RADEON_CACHE_LINE 0x0f0c /* PCI */ +#define RADEON_CAP0_TRIG_CNTL 0x0950 /* ? */ +#define RADEON_CAP1_TRIG_CNTL 0x09c0 /* ? */ +#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ +#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ +#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ +#define RADEON_CLOCK_CNTL_DATA 0x000c +#define RADEON_CLOCK_CNTL_INDEX 0x0008 +# define RADEON_PLL_WR_EN (1 << 7) +# define RADEON_PLL_DIV_SEL (3 << 8) +# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) +#define RADEON_CLR_CMP_CLR_3D 0x1a24 +#define RADEON_CLR_CMP_CLR_DST 0x15c8 +#define RADEON_CLR_CMP_CLR_SRC 0x15c4 +#define RADEON_CLR_CMP_CNTL 0x15c0 +# define RADEON_SRC_CMP_EQ_COLOR (4 << 0) +# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) +# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) +#define RADEON_CLR_CMP_MASK 0x15cc +# define RADEON_CLR_CMP_MSK 0xffffffff +#define RADEON_CLR_CMP_MASK_3D 0x1A28 +#define RADEON_COMMAND 0x0f04 /* PCI */ +#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c +#define RADEON_CONFIG_APER_0_BASE 0x0100 +#define RADEON_CONFIG_APER_1_BASE 0x0104 +#define RADEON_CONFIG_APER_SIZE 0x0108 +#define RADEON_CONFIG_BONDS 0x00e8 +#define RADEON_CONFIG_CNTL 0x00e0 +# define RADEON_CFG_ATI_REV_A11 (0 << 16) +# define RADEON_CFG_ATI_REV_A12 (1 << 16) +# define RADEON_CFG_ATI_REV_A13 (2 << 16) +# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) +#define RADEON_CONFIG_MEMSIZE 0x00f8 +#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 +#define RADEON_CONFIG_REG_1_BASE 0x010c +#define RADEON_CONFIG_REG_APER_SIZE 0x0110 +#define RADEON_CONFIG_XSTRAP 0x00e4 +#define RADEON_CONSTANT_COLOR_C 0x1d34 +# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff +# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff +# define RADEON_CONSTANT_COLOR_ZERO 0x00000000 +#define RADEON_CRC_CMDFIFO_ADDR 0x0740 +#define RADEON_CRC_CMDFIFO_DOUT 0x0744 +#define RADEON_GRPH_BUFFER_CNTL 0x02f0 +# define RADEON_GRPH_START_REQ_MASK (0x7f) +# define RADEON_GRPH_START_REQ_SHIFT 0 +# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) +# define RADEON_GRPH_STOP_REQ_SHIFT 8 +# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) +# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 +# define RADEON_GRPH_CRITICAL_CNTL (1<<28) +# define RADEON_GRPH_BUFFER_SIZE (1<<29) +# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) +# define RADEON_GRPH_STOP_CNTL (1<<31) +#define RADEON_GRPH2_BUFFER_CNTL 0x03f0 +# define RADEON_GRPH2_START_REQ_MASK (0x7f) +# define RADEON_GRPH2_START_REQ_SHIFT 0 +# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) +# define RADEON_GRPH2_STOP_REQ_SHIFT 8 +# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) +# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 +# define RADEON_GRPH2_CRITICAL_CNTL (1<<28) +# define RADEON_GRPH2_BUFFER_SIZE (1<<29) +# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) +# define RADEON_GRPH2_STOP_CNTL (1<<31) +#define RADEON_CRTC_CRNT_FRAME 0x0214 +#define RADEON_CRTC_EXT_CNTL 0x0054 +# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) +# define RADEON_VGA_ATI_LINEAR (1 << 3) +# define RADEON_XCRT_CNT_EN (1 << 6) +# define RADEON_CRTC_HSYNC_DIS (1 << 8) +# define RADEON_CRTC_VSYNC_DIS (1 << 9) +# define RADEON_CRTC_DISPLAY_DIS (1 << 10) +# define RADEON_CRTC_SYNC_TRISTAT (1 << 11) +# define RADEON_CRTC_CRT_ON (1 << 15) +#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) +# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) +# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define RADEON_CRTC_GEN_CNTL 0x0050 +# define RADEON_CRTC_DBL_SCAN_EN (1 << 0) +# define RADEON_CRTC_INTERLACE_EN (1 << 1) +# define RADEON_CRTC_CSYNC_EN (1 << 4) +# define RADEON_CRTC_CUR_EN (1 << 16) +# define RADEON_CRTC_CUR_MODE_MASK (7 << 17) +# define RADEON_CRTC_ICON_EN (1 << 20) +# define RADEON_CRTC_EXT_DISP_EN (1 << 24) +# define RADEON_CRTC_EN (1 << 25) +# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) +#define RADEON_CRTC2_GEN_CNTL 0x03f8 +# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) +# define RADEON_CRTC2_INTERLACE_EN (1 << 1) +# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) +# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) +# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) +# define RADEON_CRTC2_CRT2_ON (1 << 7) +# define RADEON_CRTC2_ICON_EN (1 << 15) +# define RADEON_CRTC2_CUR_EN (1 << 16) +# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) +# define RADEON_CRTC2_DISP_DIS (1 << 23) +# define RADEON_CRTC2_EN (1 << 25) +# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) +# define RADEON_CRTC2_CSYNC_EN (1 << 27) +# define RADEON_CRTC2_HSYNC_DIS (1 << 28) +# define RADEON_CRTC2_VSYNC_DIS (1 << 29) +#define RADEON_CRTC_MORE_CNTL 0x27c +# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 +#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 +# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) +# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +# define RADEON_CRTC_H_SYNC_WID (0x3f << 16) +# define RADEON_CRTC_H_SYNC_WID_SHIFT 16 +# define RADEON_CRTC_H_SYNC_POL (1 << 23) +#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 +# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) +# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 +# define RADEON_CRTC2_H_SYNC_POL (1 << 23) +#define RADEON_CRTC_H_TOTAL_DISP 0x0200 +# define RADEON_CRTC_H_TOTAL (0x03ff << 0) +# define RADEON_CRTC_H_TOTAL_SHIFT 0 +# define RADEON_CRTC_H_DISP (0x01ff << 16) +# define RADEON_CRTC_H_DISP_SHIFT 16 +#define RADEON_CRTC2_H_TOTAL_DISP 0x0300 +# define RADEON_CRTC2_H_TOTAL (0x03ff << 0) +# define RADEON_CRTC2_H_TOTAL_SHIFT 0 +# define RADEON_CRTC2_H_DISP (0x01ff << 16) +# define RADEON_CRTC2_H_DISP_SHIFT 16 +#define RADEON_CRTC_OFFSET 0x0224 +#define RADEON_CRTC2_OFFSET 0x0324 +#define RADEON_CRTC_OFFSET_CNTL 0x0228 +# define RADEON_CRTC_TILE_EN (1 << 15) +#define RADEON_CRTC2_OFFSET_CNTL 0x0328 +# define RADEON_CRTC2_TILE_EN (1 << 15) +#define RADEON_CRTC_PITCH 0x022c +#define RADEON_CRTC2_PITCH 0x032c +#define RADEON_CRTC_STATUS 0x005c +# define RADEON_CRTC_VBLANK_SAVE (1 << 1) +# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) +#define RADEON_CRTC2_STATUS 0x03fc +# define RADEON_CRTC2_VBLANK_SAVE (1 << 1) +# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) +#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c +# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) +# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 +# define RADEON_CRTC_V_SYNC_WID (0x1f << 16) +# define RADEON_CRTC_V_SYNC_WID_SHIFT 16 +# define RADEON_CRTC_V_SYNC_POL (1 << 23) +#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c +# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) +# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 +# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) +# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 +# define RADEON_CRTC2_V_SYNC_POL (1 << 23) +#define RADEON_CRTC_V_TOTAL_DISP 0x0208 +# define RADEON_CRTC_V_TOTAL (0x07ff << 0) +# define RADEON_CRTC_V_TOTAL_SHIFT 0 +# define RADEON_CRTC_V_DISP (0x07ff << 16) +# define RADEON_CRTC_V_DISP_SHIFT 16 +#define RADEON_CRTC2_V_TOTAL_DISP 0x0308 +# define RADEON_CRTC2_V_TOTAL (0x07ff << 0) +# define RADEON_CRTC2_V_TOTAL_SHIFT 0 +# define RADEON_CRTC2_V_DISP (0x07ff << 16) +# define RADEON_CRTC2_V_DISP_SHIFT 16 +#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 +# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define RADEON_CRTC2_CRNT_FRAME 0x0314 +#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 +#define RADEON_CRTC2_STATUS 0x03fc +#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 +#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ +#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ +#define RADEON_CUR_CLR0 0x026c +#define RADEON_CUR_CLR1 0x0270 +#define RADEON_CUR_HORZ_VERT_OFF 0x0268 +#define RADEON_CUR_HORZ_VERT_POSN 0x0264 +#define RADEON_CUR_OFFSET 0x0260 +# define RADEON_CUR_LOCK (1 << 31) +#define RADEON_CUR2_CLR0 0x036c +#define RADEON_CUR2_CLR1 0x0370 +#define RADEON_CUR2_HORZ_VERT_OFF 0x0368 +#define RADEON_CUR2_HORZ_VERT_POSN 0x0364 +#define RADEON_CUR2_OFFSET 0x0360 +# define RADEON_CUR2_LOCK (1 << 31) + +#define RADEON_DAC_CNTL 0x0058 +# define RADEON_DAC_RANGE_CNTL (3 << 0) +# define RADEON_DAC_RANGE_CNTL_MASK 0x03 +# define RADEON_DAC_BLANKING (1 << 2) +# define RADEON_DAC_CMP_EN (1 << 3) +# define RADEON_DAC_CMP_OUTPUT (1 << 7) +# define RADEON_DAC_8BIT_EN (1 << 8) +# define RADEON_DAC_VGA_ADR_EN (1 << 13) +# define RADEON_DAC_PDWN (1 << 15) +# define RADEON_DAC_MASK_ALL (0xff << 24) +#define RADEON_DAC_CNTL2 0x007c +# define RADEON_DAC2_DAC_CLK_SEL (1 << 0) +# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) +# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) +#define RADEON_DAC_EXT_CNTL 0x0280 +# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) +# define RADEON_DAC_FORCE_DATA_EN (1 << 5) +# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) +# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 +# define RADEON_DAC_FORCE_DATA_SHIFT 8 +#define RADEON_TV_DAC_CNTL 0x088c +# define RADEON_TV_DAC_STD_MASK 0x0300 +# define RADEON_TV_DAC_RDACPD (1 << 24) +# define RADEON_TV_DAC_GDACPD (1 << 25) +# define RADEON_TV_DAC_BDACPD (1 << 26) +#define RADEON_DISP_HW_DEBUG 0x0d14 +# define RADEON_CRT2_DISP1_SEL (1 << 5) +#define RADEON_DISP_OUTPUT_CNTL 0x0d64 +# define RADEON_DISP_DAC_SOURCE_MASK 0x03 +# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c +# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 +# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 +#define RADEON_DAC_CRC_SIG 0x02cc +#define RADEON_DAC_DATA 0x03c9 /* VGA */ +#define RADEON_DAC_MASK 0x03c6 /* VGA */ +#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ +#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ +#define RADEON_DDA_CONFIG 0x02e0 +#define RADEON_DDA_ON_OFF 0x02e4 +#define RADEON_DEFAULT_OFFSET 0x16e0 +#define RADEON_DEFAULT_PITCH 0x16e4 +#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 +# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 +#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 +#define RADEON_DEVICE_ID 0x0f02 /* PCI */ +#define RADEON_DISP_MISC_CNTL 0x0d00 +# define RADEON_SOFT_RESET_GRPH_PP (1 << 0) +#define RADEON_DISP_MERGE_CNTL 0x0d60 +# define RADEON_DISP_ALPHA_MODE_MASK 0x03 +# define RADEON_DISP_ALPHA_MODE_KEY 0 +# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 +# define RADEON_DISP_ALPHA_MODE_GLOBAL 2 +# define RADEON_DISP_RGB_OFFSET_EN (1<<8) +# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) +# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) +# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) +#define RADEON_DISP2_MERGE_CNTL 0x0d68 +# define RADEON_DISP2_RGB_OFFSET_EN (1<<8) +#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 +#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 +#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 +#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c +#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 +#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 +#define RADEON_DP_BRUSH_BKGD_CLR 0x1478 +#define RADEON_DP_BRUSH_FRGD_CLR 0x147c +#define RADEON_DP_CNTL 0x16c0 +# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) +# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) +#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 +# define RADEON_DST_Y_MAJOR (1 << 2) +# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) +# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) +#define RADEON_DP_DATATYPE 0x16c4 +# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) +#define RADEON_DP_GUI_MASTER_CNTL 0x146c +# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define RADEON_GMC_SRC_CLIPPING (1 << 2) +# define RADEON_GMC_DST_CLIPPING (1 << 3) +# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) +# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) +# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) +# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) +# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) +# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) +# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) +# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) +# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) +# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) +# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) +# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define RADEON_GMC_BRUSH_NONE (15 << 4) +# define RADEON_GMC_DST_8BPP_CI (2 << 8) +# define RADEON_GMC_DST_15BPP (3 << 8) +# define RADEON_GMC_DST_16BPP (4 << 8) +# define RADEON_GMC_DST_24BPP (5 << 8) +# define RADEON_GMC_DST_32BPP (6 << 8) +# define RADEON_GMC_DST_8BPP_RGB (7 << 8) +# define RADEON_GMC_DST_Y8 (8 << 8) +# define RADEON_GMC_DST_RGB8 (9 << 8) +# define RADEON_GMC_DST_VYUY (11 << 8) +# define RADEON_GMC_DST_YVYU (12 << 8) +# define RADEON_GMC_DST_AYUV444 (14 << 8) +# define RADEON_GMC_DST_ARGB4444 (15 << 8) +# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) +# define RADEON_GMC_DST_DATATYPE_SHIFT 8 +# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) +# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) +# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) +# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) +# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) +# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) +# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) +# define RADEON_GMC_CONVERSION_TEMP (1 << 15) +# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) +# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) +# define RADEON_GMC_ROP3_MASK (0xff << 16) +# define RADEON_DP_SRC_SOURCE_MASK (7 << 24) +# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) +# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define RADEON_GMC_3D_FCN_EN (1 << 27) +# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define RADEON_GMC_AUX_CLIP_DIS (1 << 29) +# define RADEON_GMC_WR_MSK_DIS (1 << 30) +# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) +# define RADEON_ROP3_ZERO 0x00000000 +# define RADEON_ROP3_DSa 0x00880000 +# define RADEON_ROP3_SDna 0x00440000 +# define RADEON_ROP3_S 0x00cc0000 +# define RADEON_ROP3_DSna 0x00220000 +# define RADEON_ROP3_D 0x00aa0000 +# define RADEON_ROP3_DSx 0x00660000 +# define RADEON_ROP3_DSo 0x00ee0000 +# define RADEON_ROP3_DSon 0x00110000 +# define RADEON_ROP3_DSxn 0x00990000 +# define RADEON_ROP3_Dn 0x00550000 +# define RADEON_ROP3_SDno 0x00dd0000 +# define RADEON_ROP3_Sn 0x00330000 +# define RADEON_ROP3_DSno 0x00bb0000 +# define RADEON_ROP3_DSan 0x00770000 +# define RADEON_ROP3_ONE 0x00ff0000 +# define RADEON_ROP3_DPa 0x00a00000 +# define RADEON_ROP3_PDna 0x00500000 +# define RADEON_ROP3_P 0x00f00000 +# define RADEON_ROP3_DPna 0x000a0000 +# define RADEON_ROP3_D 0x00aa0000 +# define RADEON_ROP3_DPx 0x005a0000 +# define RADEON_ROP3_DPo 0x00fa0000 +# define RADEON_ROP3_DPon 0x00050000 +# define RADEON_ROP3_PDxn 0x00a50000 +# define RADEON_ROP3_PDno 0x00f50000 +# define RADEON_ROP3_Pn 0x000f0000 +# define RADEON_ROP3_DPno 0x00af0000 +# define RADEON_ROP3_DPan 0x005f0000 +#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 +#define RADEON_DP_MIX 0x16c8 +#define RADEON_DP_SRC_BKGD_CLR 0x15dc +#define RADEON_DP_SRC_FRGD_CLR 0x15d8 +#define RADEON_DP_WRITE_MASK 0x16cc +#define RADEON_DST_BRES_DEC 0x1630 +#define RADEON_DST_BRES_ERR 0x1628 +#define RADEON_DST_BRES_INC 0x162c +#define RADEON_DST_BRES_LNTH 0x1634 +#define RADEON_DST_BRES_LNTH_SUB 0x1638 +#define RADEON_DST_HEIGHT 0x1410 +#define RADEON_DST_HEIGHT_WIDTH 0x143c +#define RADEON_DST_HEIGHT_WIDTH_8 0x158c +#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 +#define RADEON_DST_HEIGHT_Y 0x15a0 +#define RADEON_DST_LINE_START 0x1600 +#define RADEON_DST_LINE_END 0x1604 +#define RADEON_DST_LINE_PATCOUNT 0x1608 +# define RADEON_BRES_CNTL_SHIFT 8 +#define RADEON_DST_OFFSET 0x1404 +#define RADEON_DST_PITCH 0x1408 +#define RADEON_DST_PITCH_OFFSET 0x142c +#define RADEON_DST_PITCH_OFFSET_C 0x1c80 +# define RADEON_PITCH_SHIFT 21 +# define RADEON_DST_TILE_LINEAR (0 << 30) +# define RADEON_DST_TILE_MACRO (1 << 30) +# define RADEON_DST_TILE_MICRO (2 << 30) +# define RADEON_DST_TILE_BOTH (3 << 30) +#define RADEON_DST_WIDTH 0x140c +#define RADEON_DST_WIDTH_HEIGHT 0x1598 +#define RADEON_DST_WIDTH_X 0x1588 +#define RADEON_DST_WIDTH_X_INCY 0x159c +#define RADEON_DST_X 0x141c +#define RADEON_DST_X_SUB 0x15a4 +#define RADEON_DST_X_Y 0x1594 +#define RADEON_DST_Y 0x1420 +#define RADEON_DST_Y_SUB 0x15a8 +#define RADEON_DST_Y_X 0x1438 + +#define RADEON_FCP_CNTL 0x0910 +# define RADEON_FCP0_SRC_PCICLK 0 +# define RADEON_FCP0_SRC_PCLK 1 +# define RADEON_FCP0_SRC_PCLKb 2 +# define RADEON_FCP0_SRC_HREF 3 +# define RADEON_FCP0_SRC_GND 4 +# define RADEON_FCP0_SRC_HREFb 5 +#define RADEON_FLUSH_1 0x1704 +#define RADEON_FLUSH_2 0x1708 +#define RADEON_FLUSH_3 0x170c +#define RADEON_FLUSH_4 0x1710 +#define RADEON_FLUSH_5 0x1714 +#define RADEON_FLUSH_6 0x1718 +#define RADEON_FLUSH_7 0x171c +#define RADEON_FOG_3D_TABLE_START 0x1810 +#define RADEON_FOG_3D_TABLE_END 0x1814 +#define RADEON_FOG_3D_TABLE_DENSITY 0x181c +#define RADEON_FOG_TABLE_INDEX 0x1a14 +#define RADEON_FOG_TABLE_DATA 0x1a18 +#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 +#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 +#define RADEON_FP_CRTC2_H_TOTAL_DISP 0x0350 +#define RADEON_FP_CRTC2_V_TOTAL_DISP 0x0354 +# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff +# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 +# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff +# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 +# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 +# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff +# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 +# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 +# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 +# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 +# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 +# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 +# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 +# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 +#define RADEON_FP_GEN_CNTL 0x0284 +# define RADEON_FP_FPON (1 << 0) +# define RADEON_FP_TMDS_EN (1 << 2) +# define RADEON_FP_PANEL_FORMAT (1 << 3) +# define RADEON_FP_EN_TMDS (1 << 7) +# define RADEON_FP_DETECT_SENSE (1 << 8) +# define RADEON_FP_SEL_CRTC2 (1 << 13) +# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) +# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) +# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +# define RADEON_FP_DFP_SYNC_SEL (1 << 21) +# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) +# define RADEON_FP_CRT_SYNC_SEL (1 << 23) +# define RADEON_FP_USE_SHADOW_EN (1 << 24) +# define RADEON_FP_CRT_SYNC_ALT (1 << 26) +#define RADEON_FP2_GEN_CNTL 0x0288 +# define RADEON_FP2_BLANK_EN (1 << 1) +# define RADEON_FP2_ON (1 << 2) +# define RADEON_FP2_PANEL_FORMAT (1 << 3) +# define RADEON_FP2_SOURCE_SEL_MASK (3 << 10) +# define RADEON_FP2_SOURCE_SEL_CRTC2 (1 << 10) +# define RADEON_FP2_SRC_SEL_MASK (3 << 13) +# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) +# define RADEON_FP2_FP_POL (1 << 16) +# define RADEON_FP2_LP_POL (1 << 17) +# define RADEON_FP2_SCK_POL (1 << 18) +# define RADEON_FP2_LCD_CNTL_MASK (7 << 19) +# define RADEON_FP2_PAD_FLOP_EN (1 << 22) +# define RADEON_FP2_CRC_EN (1 << 23) +# define RADEON_FP2_CRC_READ_EN (1 << 24) +# define RADEON_FP2_DV0_EN (1 << 25) +# define RADEON_FP2_DV0_RATE_SEL_SDR (1 << 26) +#define RADEON_FP_H_SYNC_STRT_WID 0x02c4 +#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 +#define RADEON_FP_HORZ_STRETCH 0x028c +#define RADEON_FP_HORZ2_STRETCH 0x038c +# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff +# define RADEON_HORZ_STRETCH_RATIO_MAX 4096 +# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) +# define RADEON_HORZ_PANEL_SHIFT 16 +# define RADEON_HORZ_STRETCH_PIXREP (0 << 25) +# define RADEON_HORZ_STRETCH_BLEND (1 << 26) +# define RADEON_HORZ_STRETCH_ENABLE (1 << 25) +# define RADEON_HORZ_AUTO_RATIO (1 << 27) +# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) +# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) +#define RADEON_FP_V_SYNC_STRT_WID 0x02c8 +#define RADEON_FP_VERT_STRETCH 0x0290 +#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 +#define RADEON_FP_VERT2_STRETCH 0x0390 +# define RADEON_VERT_PANEL_SIZE (0xfff << 12) +# define RADEON_VERT_PANEL_SHIFT 12 +# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff +# define RADEON_VERT_STRETCH_RATIO_SHIFT 0 +# define RADEON_VERT_STRETCH_RATIO_MAX 4096 +# define RADEON_VERT_STRETCH_ENABLE (1 << 25) +# define RADEON_VERT_STRETCH_LINEREP (0 << 26) +# define RADEON_VERT_STRETCH_BLEND (1 << 26) +# define RADEON_VERT_AUTO_RATIO_EN (1 << 27) +# define RADEON_VERT_STRETCH_RESERVED 0xf1000000 + +#define RADEON_GEN_INT_CNTL 0x0040 +#define RADEON_GEN_INT_STATUS 0x0044 +# define RADEON_VSYNC_INT_AK (1 << 2) +# define RADEON_VSYNC_INT (1 << 2) +# define RADEON_VSYNC2_INT_AK (1 << 6) +# define RADEON_VSYNC2_INT (1 << 6) +#define RADEON_GENENB 0x03c3 /* VGA */ +#define RADEON_GENFC_RD 0x03ca /* VGA */ +#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ +#define RADEON_GENMO_RD 0x03cc /* VGA */ +#define RADEON_GENMO_WT 0x03c2 /* VGA */ +#define RADEON_GENS0 0x03c2 /* VGA */ +#define RADEON_GENS1 0x03da /* VGA, 0x03ba */ +#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ +#define RADEON_GPIO_MONIDB 0x006c +#define RADEON_GPIO_CRT2_DDC 0x006c +#define RADEON_GPIO_DVI_DDC 0x0064 +#define RADEON_GPIO_VGA_DDC 0x0060 +# define RADEON_GPIO_A_0 (1 << 0) +# define RADEON_GPIO_A_1 (1 << 1) +# define RADEON_GPIO_Y_0 (1 << 8) +# define RADEON_GPIO_Y_1 (1 << 9) +# define RADEON_GPIO_Y_SHIFT_0 8 +# define RADEON_GPIO_Y_SHIFT_1 9 +# define RADEON_GPIO_EN_0 (1 << 16) +# define RADEON_GPIO_EN_1 (1 << 17) +# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ +# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ +#define RADEON_GRPH8_DATA 0x03cf /* VGA */ +#define RADEON_GRPH8_IDX 0x03ce /* VGA */ +#define RADEON_GUI_SCRATCH_REG0 0x15e0 +#define RADEON_GUI_SCRATCH_REG1 0x15e4 +#define RADEON_GUI_SCRATCH_REG2 0x15e8 +#define RADEON_GUI_SCRATCH_REG3 0x15ec +#define RADEON_GUI_SCRATCH_REG4 0x15f0 +#define RADEON_GUI_SCRATCH_REG5 0x15f4 + +#define RADEON_HEADER 0x0f0e /* PCI */ +#define RADEON_HOST_DATA0 0x17c0 +#define RADEON_HOST_DATA1 0x17c4 +#define RADEON_HOST_DATA2 0x17c8 +#define RADEON_HOST_DATA3 0x17cc +#define RADEON_HOST_DATA4 0x17d0 +#define RADEON_HOST_DATA5 0x17d4 +#define RADEON_HOST_DATA6 0x17d8 +#define RADEON_HOST_DATA7 0x17dc +#define RADEON_HOST_DATA_LAST 0x17e0 +#define RADEON_HOST_PATH_CNTL 0x0130 +# define RADEON_HDP_SOFT_RESET (1 << 26) +#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ +#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ + +#define RADEON_I2C_CNTL_1 0x0094 /* ? */ +#define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */ +#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ +#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ +#define RADEON_IO_BASE 0x0f14 /* PCI */ + +#define RADEON_LATENCY 0x0f0d /* PCI */ +#define RADEON_LEAD_BRES_DEC 0x1608 +#define RADEON_LEAD_BRES_LNTH 0x161c +#define RADEON_LEAD_BRES_LNTH_SUB 0x1624 +#define RADEON_LVDS_GEN_CNTL 0x02d0 +# define RADEON_LVDS_ON (1 << 0) +# define RADEON_LVDS_DISPLAY_DIS (1 << 1) +# define RADEON_LVDS_PANEL_TYPE (1 << 2) +# define RADEON_LVDS_PANEL_FORMAT (1 << 3) +# define RADEON_LVDS_EN (1 << 7) +# define RADEON_LVDS_DIGON (1 << 18) +# define RADEON_LVDS_BLON (1 << 19) +# define RADEON_LVDS_SEL_CRTC2 (1 << 23) +#define RADEON_LVDS_PLL_CNTL 0x02d4 +# define RADEON_HSYNC_DELAY_SHIFT 28 +# define RADEON_HSYNC_DELAY_MASK (0xf << 28) + +#define RADEON_MAX_LATENCY 0x0f3f /* PCI */ +#define RADEON_MC_AGP_LOCATION 0x014c +#define RADEON_MC_FB_LOCATION 0x0148 +#define RADEON_DISPLAY_BASE_ADDR 0x23c +#define RADEON_DISPLAY2_BASE_ADDR 0x33c +#define RADEON_OV0_BASE_ADDR 0x43c +#define RADEON_NB_TOM 0x15c +#define RADEON_MCLK_CNTL 0x0012 /* PLL */ +# define RADEON_FORCEON_MCLKA (1 << 16) +# define RADEON_FORCEON_MCLKB (1 << 17) +# define RADEON_FORCEON_YCLKA (1 << 18) +# define RADEON_FORCEON_YCLKB (1 << 19) +# define RADEON_FORCEON_MC (1 << 20) +# define RADEON_FORCEON_AIC (1 << 21) +#define RADEON_MDGPIO_A_REG 0x01ac +#define RADEON_MDGPIO_EN_REG 0x01b0 +#define RADEON_MDGPIO_MASK 0x0198 +#define RADEON_MDGPIO_Y_REG 0x01b4 +#define RADEON_MEM_ADDR_CONFIG 0x0148 +#define RADEON_MEM_BASE 0x0f10 /* PCI */ +#define RADEON_MEM_CNTL 0x0140 +# define RADEON_MEM_NUM_CHANNELS_MASK 0x01 +# define RADEON_MEM_USE_B_CH_ONLY (1<<1) +# define RV100_HALF_MODE (1<<3) +# define R300_MEM_NUM_CHANNELS_MASK 0x03 +# define R300_MEM_USE_CD_CH_ONLY (1<<2) +#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ +#define RADEON_MEM_INIT_LAT_TIMER 0x0154 +#define RADEON_MEM_INTF_CNTL 0x014c +#define RADEON_MEM_SDRAM_MODE_REG 0x0158 +#define RADEON_MEM_STR_CNTL 0x0150 +#define RADEON_MEM_VGA_RP_SEL 0x003c +#define RADEON_MEM_VGA_WP_SEL 0x0038 +#define RADEON_MIN_GRANT 0x0f3e /* PCI */ +#define RADEON_MM_DATA 0x0004 +#define RADEON_MM_INDEX 0x0000 +#define RADEON_MPLL_CNTL 0x000e /* PLL */ +#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ +#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ +#define R300_MC_IND_INDEX 0x01f8 +# define R300_MC_IND_ADDR_MASK 0x3f +#define R300_MC_IND_DATA 0x01fc +#define R300_MC_READ_CNTL_AB 0x017c +# define R300_MEM_RBS_POSITION_A_MASK 0x03 +#define R300_MC_READ_CNTL_CD_mcind 0x24 +# define R300_MEM_RBS_POSITION_C_MASK 0x03 + +#define RADEON_N_VIF_COUNT 0x0248 + +#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 +#define RADEON_OV0_COLOUR_CNTL 0x04E0 +#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 +#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 +# define RADEON_EXCL_HORZ_START_MASK 0x000000ff +# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 +# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define RADEON_OV0_EXCLUSIVE_VERT 0x040C +# define RADEON_EXCL_VERT_START_MASK 0x000003ff +# define RADEON_EXCL_VERT_END_MASK 0x03ff0000 +#define RADEON_OV0_FILTER_CNTL 0x04A0 +#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 +#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 +#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 +#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC +#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 +#define RADEON_OV0_GAMMA_000_00F 0x0d40 +#define RADEON_OV0_GAMMA_010_01F 0x0d44 +#define RADEON_OV0_GAMMA_020_03F 0x0d48 +#define RADEON_OV0_GAMMA_040_07F 0x0d4c +#define RADEON_OV0_GAMMA_080_0BF 0x0e00 +#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 +#define RADEON_OV0_GAMMA_100_13F 0x0e08 +#define RADEON_OV0_GAMMA_140_17F 0x0e0c +#define RADEON_OV0_GAMMA_180_1BF 0x0e10 +#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 +#define RADEON_OV0_GAMMA_200_23F 0x0e18 +#define RADEON_OV0_GAMMA_240_27F 0x0e1c +#define RADEON_OV0_GAMMA_280_2BF 0x0e20 +#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 +#define RADEON_OV0_GAMMA_300_33F 0x0e28 +#define RADEON_OV0_GAMMA_340_37F 0x0e2c +#define RADEON_OV0_GAMMA_380_3BF 0x0d50 +#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 +#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC +#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 +#define RADEON_OV0_H_INC 0x0480 +#define RADEON_OV0_KEY_CNTL 0x04F4 +# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L +# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L +# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L +# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L +# define RADEON_VIDEO_KEY_FN_NE 0x00000003L +# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L +# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L +# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L +# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L +# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L +# define RADEON_CMP_MIX_MASK 0x00000100L +# define RADEON_CMP_MIX_OR 0x00000000L +# define RADEON_CMP_MIX_AND 0x00000100L +#define RADEON_OV0_LIN_TRANS_A 0x0d20 +#define RADEON_OV0_LIN_TRANS_B 0x0d24 +#define RADEON_OV0_LIN_TRANS_C 0x0d28 +#define RADEON_OV0_LIN_TRANS_D 0x0d2c +#define RADEON_OV0_LIN_TRANS_E 0x0d30 +#define RADEON_OV0_LIN_TRANS_F 0x0d34 +#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L +#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 +#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 +# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define RADEON_OV0_P1_X_START_END 0x0494 +#define RADEON_OV0_P2_X_START_END 0x0498 +#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L +#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C +#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C +#define RADEON_OV0_P3_X_START_END 0x049C +#define RADEON_OV0_REG_LOAD_CNTL 0x0410 +# define RADEON_REG_LD_CTL_LOCK 0x00000001L +# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L +#define RADEON_OV0_SCALE_CNTL 0x0420 +# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L +# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L +# define RADEON_SCALER_SIGNED_UV 0x00000010L +# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L +# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L +# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L +# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L +# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L +# define RADEON_SCALER_SOURCE_15BPP 0x00000300L +# define RADEON_SCALER_SOURCE_16BPP 0x00000400L +# define RADEON_SCALER_SOURCE_32BPP 0x00000600L +# define RADEON_SCALER_SOURCE_YUV9 0x00000900L +# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L +# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L +# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L +# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L +# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L +# define RADEON_SCALER_SMART_SWITCH 0x00008000L +# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L +# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L +# define RADEON_SCALER_DIS_LIMIT 0x08000000L +# define RADEON_SCALER_INT_EMU 0x20000000L +# define RADEON_SCALER_ENABLE 0x40000000L +# define RADEON_SCALER_SOFT_RESET 0x80000000L +# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L +#define RADEON_OV0_STEP_BY 0x0484 +#define RADEON_OV0_TEST 0x04F8 +#define RADEON_OV0_V_INC 0x0424 +#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 +# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 +# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 +# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C +#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 +#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 +#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 +#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 +#define RADEON_OV0_Y_X_START 0x0400 +#define RADEON_OV0_Y_X_END 0x0404 +#define RADEON_OV1_Y_X_START 0x0600 +#define RADEON_OV1_Y_X_END 0x0604 +#define RADEON_OVR_CLR 0x0230 +#define RADEON_OVR_WID_LEFT_RIGHT 0x0234 +#define RADEON_OVR_WID_TOP_BOTTOM 0x0238 + +#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ +# define RADEON_P2PLL_RESET (1 << 0) +# define RADEON_P2PLL_SLEEP (1 << 1) +# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define RADEON_P2PLL_DIV_0 0x002c +# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff +# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 +#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ +# define RADEON_P2PLL_REF_DIV_MASK 0x03ff +# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +# define R300_PPLL_REF_DIV_ACC_SHIFT 18 +#define RADEON_PALETTE_DATA 0x00b4 +#define RADEON_PALETTE_30_DATA 0x00b8 +#define RADEON_PALETTE_INDEX 0x00b0 +#define RADEON_PCI_GART_PAGE 0x017c +#define RADEON_PIXCLKS_CNTL 0x002d +# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 +# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 +# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 +# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 +# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) +# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) +# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) +# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +#define RADEON_PLANE_3D_MASK_C 0x1d44 +#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ +#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ +#define RADEON_PMI_DATA 0x0f63 /* PCI */ +#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ +#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ +#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ +#define RADEON_PMI_REGISTER 0x0f5c /* PCI */ +#define RADEON_PPLL_CNTL 0x0002 /* PLL */ +# define RADEON_PPLL_RESET (1 << 0) +# define RADEON_PPLL_SLEEP (1 << 1) +# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) +# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define RADEON_PPLL_DIV_0 0x0004 /* PLL */ +#define RADEON_PPLL_DIV_1 0x0005 /* PLL */ +#define RADEON_PPLL_DIV_2 0x0006 /* PLL */ +#define RADEON_PPLL_DIV_3 0x0007 /* PLL */ +# define RADEON_PPLL_FB3_DIV_MASK 0x07ff +# define RADEON_PPLL_POST3_DIV_MASK 0x00070000 +#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ +# define RADEON_PPLL_REF_DIV_MASK 0x03ff +# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ + +#define RADEON_RBBM_GUICNTL 0x172c +# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) +# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) +# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) +# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) +#define RADEON_RBBM_SOFT_RESET 0x00f0 +# define RADEON_SOFT_RESET_CP (1 << 0) +# define RADEON_SOFT_RESET_HI (1 << 1) +# define RADEON_SOFT_RESET_SE (1 << 2) +# define RADEON_SOFT_RESET_RE (1 << 3) +# define RADEON_SOFT_RESET_PP (1 << 4) +# define RADEON_SOFT_RESET_E2 (1 << 5) +# define RADEON_SOFT_RESET_RB (1 << 6) +# define RADEON_SOFT_RESET_HDP (1 << 7) +#define RADEON_RBBM_STATUS 0x0e40 +# define RADEON_RBBM_FIFOCNT_MASK 0x007f +# define RADEON_RBBM_ACTIVE (1 << 31) +#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c +# define RADEON_RB2D_DC_FLUSH (3 << 0) +# define RADEON_RB2D_DC_FREE (3 << 2) +# define RADEON_RB2D_DC_FLUSH_ALL 0xf +# define RADEON_RB2D_DC_BUSY (1 << 31) +#define RADEON_RB2D_DSTCACHE_MODE 0x3428 +#define RADEON_REG_BASE 0x0f18 /* PCI */ +#define RADEON_REGPROG_INF 0x0f09 /* PCI */ +#define RADEON_REVISION_ID 0x0f08 /* PCI */ + +#define RADEON_SC_BOTTOM 0x164c +#define RADEON_SC_BOTTOM_RIGHT 0x16f0 +#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c +#define RADEON_SC_LEFT 0x1640 +#define RADEON_SC_RIGHT 0x1644 +#define RADEON_SC_TOP 0x1648 +#define RADEON_SC_TOP_LEFT 0x16ec +#define RADEON_SC_TOP_LEFT_C 0x1c88 +# define RADEON_SC_SIGN_MASK_LO 0x8000 +# define RADEON_SC_SIGN_MASK_HI 0x80000000 +#define RADEON_SCLK_CNTL 0x000d /* PLL */ +# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 +# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 +# define RADEON_SCLK_FORCEON_MASK 0xffff8000 +#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ +# define RADEON_SCLK_MORE_FORCEON 0x0700 +#define RADEON_SDRAM_MODE_REG 0x0158 +#define RADEON_SEQ8_DATA 0x03c5 /* VGA */ +#define RADEON_SEQ8_IDX 0x03c4 /* VGA */ +#define RADEON_SNAPSHOT_F_COUNT 0x0244 +#define RADEON_SNAPSHOT_VH_COUNTS 0x0240 +#define RADEON_SNAPSHOT_VIF_COUNT 0x024c +#define RADEON_SRC_OFFSET 0x15ac +#define RADEON_SRC_PITCH 0x15b0 +#define RADEON_SRC_PITCH_OFFSET 0x1428 +#define RADEON_SRC_SC_BOTTOM 0x165c +#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 +#define RADEON_SRC_SC_RIGHT 0x1654 +#define RADEON_SRC_X 0x1414 +#define RADEON_SRC_X_Y 0x1590 +#define RADEON_SRC_Y 0x1418 +#define RADEON_SRC_Y_X 0x1434 +#define RADEON_STATUS 0x0f06 /* PCI */ +#define RADEON_SUBPIC_CNTL 0x0540 /* ? */ +#define RADEON_SUB_CLASS 0x0f0a /* PCI */ +#define RADEON_SURFACE_CNTL 0x0b00 +# define RADEON_SURF_TRANSLATION_DIS (1 << 8) +# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) +# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) +#define RADEON_SURFACE0_INFO 0x0b0c +# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) +# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) +# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) +# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) +# define R200_SURF_TILE_NONE (0 << 16) +# define R200_SURF_TILE_COLOR_MACRO (1 << 16) +# define R200_SURF_TILE_COLOR_MICRO (2 << 16) +# define R200_SURF_TILE_COLOR_BOTH (3 << 16) +# define R200_SURF_TILE_DEPTH_32BPP (4 << 16) +# define R200_SURF_TILE_DEPTH_16BPP (5 << 16) +# define RADEON_SURF_AP0_SWP_16BPP (1 << 20) +# define RADEON_SURF_AP0_SWP_32BPP (1 << 21) +# define RADEON_SURF_AP1_SWP_16BPP (1 << 22) +# define RADEON_SURF_AP1_SWP_32BPP (1 << 23) +#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 +#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 +#define RADEON_SURFACE1_INFO 0x0b1c +#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 +#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 +#define RADEON_SURFACE2_INFO 0x0b2c +#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 +#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 +#define RADEON_SURFACE3_INFO 0x0b3c +#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 +#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 +#define RADEON_SURFACE4_INFO 0x0b4c +#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 +#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 +#define RADEON_SURFACE5_INFO 0x0b5c +#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 +#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 +#define RADEON_SURFACE6_INFO 0x0b6c +#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 +#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 +#define RADEON_SURFACE7_INFO 0x0b7c +#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 +#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 +#define RADEON_SW_SEMAPHORE 0x013c + +#define RADEON_TEST_DEBUG_CNTL 0x0120 +#define RADEON_TEST_DEBUG_MUX 0x0124 +#define RADEON_TEST_DEBUG_OUT 0x012c +#define RADEON_TMDS_PLL_CNTL 0x02a8 +#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 +# define RADEON_TMDS_TRANSMITTER_PLLEN 1 +# define RADEON_TMDS_TRANSMITTER_PLLRST 2 +#define RADEON_TRAIL_BRES_DEC 0x1614 +#define RADEON_TRAIL_BRES_ERR 0x160c +#define RADEON_TRAIL_BRES_INC 0x1610 +#define RADEON_TRAIL_X 0x1618 +#define RADEON_TRAIL_X_SUB 0x1620 + +#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ +# define RADEON_VCLK_SRC_SEL_MASK 0x03 +# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 +# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 +# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 +# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 +# define RADEON_PIXCLK_ALWAYS_ONb (1<<6) +# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) + +#define RADEON_VENDOR_ID 0x0f00 /* PCI */ +#define RADEON_VGA_DDA_CONFIG 0x02e8 +#define RADEON_VGA_DDA_ON_OFF 0x02ec +#define RADEON_VID_BUFFER_CONTROL 0x0900 +#define RADEON_VIDEOMUX_CNTL 0x0190 +#define RADEON_VIPH_CONTROL 0x0c40 /* ? */ + +#define RADEON_WAIT_UNTIL 0x1720 +# define RADEON_WAIT_CRTC_PFLIP (1 << 0) +# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) +# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) +# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) + +#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ +#define RADEON_XCLK_CNTL 0x000d /* PLL */ +#define RADEON_XDLL_CNTL 0x000c /* PLL */ +#define RADEON_XPLL_CNTL 0x000b /* PLL */ + + + + /* Registers for 3D/TCL */ +#define RADEON_PP_BORDER_COLOR_0 0x1d40 +#define RADEON_PP_BORDER_COLOR_1 0x1d44 +#define RADEON_PP_BORDER_COLOR_2 0x1d48 +#define RADEON_PP_CNTL 0x1c38 +# define RADEON_STIPPLE_ENABLE (1 << 0) +# define RADEON_SCISSOR_ENABLE (1 << 1) +# define RADEON_PATTERN_ENABLE (1 << 2) +# define RADEON_SHADOW_ENABLE (1 << 3) +# define RADEON_TEX_ENABLE_MASK (0xf << 4) +# define RADEON_TEX_0_ENABLE (1 << 4) +# define RADEON_TEX_1_ENABLE (1 << 5) +# define RADEON_TEX_2_ENABLE (1 << 6) +# define RADEON_TEX_3_ENABLE (1 << 7) +# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) +# define RADEON_TEX_BLEND_0_ENABLE (1 << 12) +# define RADEON_TEX_BLEND_1_ENABLE (1 << 13) +# define RADEON_TEX_BLEND_2_ENABLE (1 << 14) +# define RADEON_TEX_BLEND_3_ENABLE (1 << 15) +# define RADEON_PLANAR_YUV_ENABLE (1 << 20) +# define RADEON_SPECULAR_ENABLE (1 << 21) +# define RADEON_FOG_ENABLE (1 << 22) +# define RADEON_ALPHA_TEST_ENABLE (1 << 23) +# define RADEON_ANTI_ALIAS_NONE (0 << 24) +# define RADEON_ANTI_ALIAS_LINE (1 << 24) +# define RADEON_ANTI_ALIAS_POLY (2 << 24) +# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) +# define RADEON_BUMP_MAP_ENABLE (1 << 26) +# define RADEON_BUMPED_MAP_T0 (0 << 27) +# define RADEON_BUMPED_MAP_T1 (1 << 27) +# define RADEON_BUMPED_MAP_T2 (2 << 27) +# define RADEON_TEX_3D_ENABLE_0 (1 << 29) +# define RADEON_TEX_3D_ENABLE_1 (1 << 30) +# define RADEON_MC_ENABLE (1 << 31) +#define RADEON_PP_FOG_COLOR 0x1c18 +# define RADEON_FOG_COLOR_MASK 0x00ffffff +# define RADEON_FOG_VERTEX (0 << 24) +# define RADEON_FOG_TABLE (1 << 24) +# define RADEON_FOG_USE_DEPTH (0 << 25) +# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) +# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) +#define RADEON_PP_LUM_MATRIX 0x1d00 +#define RADEON_PP_MISC 0x1c14 +# define RADEON_REF_ALPHA_MASK 0x000000ff +# define RADEON_ALPHA_TEST_FAIL (0 << 8) +# define RADEON_ALPHA_TEST_LESS (1 << 8) +# define RADEON_ALPHA_TEST_LEQUAL (2 << 8) +# define RADEON_ALPHA_TEST_EQUAL (3 << 8) +# define RADEON_ALPHA_TEST_GEQUAL (4 << 8) +# define RADEON_ALPHA_TEST_GREATER (5 << 8) +# define RADEON_ALPHA_TEST_NEQUAL (6 << 8) +# define RADEON_ALPHA_TEST_PASS (7 << 8) +# define RADEON_ALPHA_TEST_OP_MASK (7 << 8) +# define RADEON_CHROMA_FUNC_FAIL (0 << 16) +# define RADEON_CHROMA_FUNC_PASS (1 << 16) +# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) +# define RADEON_CHROMA_FUNC_EQUAL (3 << 16) +# define RADEON_CHROMA_KEY_NEAREST (0 << 18) +# define RADEON_CHROMA_KEY_ZERO (1 << 18) +# define RADEON_SHADOW_ID_AUTO_INC (1 << 20) +# define RADEON_SHADOW_FUNC_EQUAL (0 << 21) +# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) +# define RADEON_SHADOW_PASS_1 (0 << 22) +# define RADEON_SHADOW_PASS_2 (1 << 22) +# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) +# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) +#define RADEON_PP_ROT_MATRIX_0 0x1d58 +#define RADEON_PP_ROT_MATRIX_1 0x1d5c +#define RADEON_PP_TXFILTER_0 0x1c54 +#define RADEON_PP_TXFILTER_1 0x1c6c +#define RADEON_PP_TXFILTER_2 0x1c84 +# define RADEON_MAG_FILTER_NEAREST (0 << 0) +# define RADEON_MAG_FILTER_LINEAR (1 << 0) +# define RADEON_MAG_FILTER_MASK (1 << 0) +# define RADEON_MIN_FILTER_NEAREST (0 << 1) +# define RADEON_MIN_FILTER_LINEAR (1 << 1) +# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) +# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +# define RADEON_MIN_FILTER_MASK (15 << 1) +# define RADEON_MAX_ANISO_1_TO_1 (0 << 5) +# define RADEON_MAX_ANISO_2_TO_1 (1 << 5) +# define RADEON_MAX_ANISO_4_TO_1 (2 << 5) +# define RADEON_MAX_ANISO_8_TO_1 (3 << 5) +# define RADEON_MAX_ANISO_16_TO_1 (4 << 5) +# define RADEON_MAX_ANISO_MASK (7 << 5) +# define RADEON_LOD_BIAS_MASK (0xff << 8) +# define RADEON_LOD_BIAS_SHIFT 8 +# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) +# define RADEON_MAX_MIP_LEVEL_SHIFT 16 +# define RADEON_YUV_TO_RGB (1 << 20) +# define RADEON_YUV_TEMPERATURE_COOL (0 << 21) +# define RADEON_YUV_TEMPERATURE_HOT (1 << 21) +# define RADEON_YUV_TEMPERATURE_MASK (1 << 21) +# define RADEON_WRAPEN_S (1 << 22) +# define RADEON_CLAMP_S_WRAP (0 << 23) +# define RADEON_CLAMP_S_MIRROR (1 << 23) +# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +# define RADEON_CLAMP_S_CLAMP_GL (6 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +# define RADEON_CLAMP_S_MASK (7 << 23) +# define RADEON_WRAPEN_T (1 << 26) +# define RADEON_CLAMP_T_WRAP (0 << 27) +# define RADEON_CLAMP_T_MIRROR (1 << 27) +# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +# define RADEON_CLAMP_T_CLAMP_GL (6 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +# define RADEON_CLAMP_T_MASK (7 << 27) +# define RADEON_BORDER_MODE_OGL (0 << 31) +# define RADEON_BORDER_MODE_D3D (1 << 31) +#define RADEON_PP_TXFORMAT_0 0x1c58 +#define RADEON_PP_TXFORMAT_1 0x1c70 +#define RADEON_PP_TXFORMAT_2 0x1c88 +# define RADEON_TXFORMAT_I8 (0 << 0) +# define RADEON_TXFORMAT_AI88 (1 << 0) +# define RADEON_TXFORMAT_RGB332 (2 << 0) +# define RADEON_TXFORMAT_ARGB1555 (3 << 0) +# define RADEON_TXFORMAT_RGB565 (4 << 0) +# define RADEON_TXFORMAT_ARGB4444 (5 << 0) +# define RADEON_TXFORMAT_ARGB8888 (6 << 0) +# define RADEON_TXFORMAT_RGBA8888 (7 << 0) +# define RADEON_TXFORMAT_Y8 (8 << 0) +# define RADEON_TXFORMAT_VYUY422 (10 << 0) +# define RADEON_TXFORMAT_YVYU422 (11 << 0) +# define RADEON_TXFORMAT_DXT1 (12 << 0) +# define RADEON_TXFORMAT_DXT23 (14 << 0) +# define RADEON_TXFORMAT_DXT45 (15 << 0) +# define RADEON_TXFORMAT_SHADOW16 (16 << 0) +# define RADEON_TXFORMAT_SHADOW32 (17 << 0) +# define RADEON_TXFORMAT_DUDV88 (18 << 0) +# define RADEON_TXFORMAT_LDUDV655 (19 << 0) +# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0) +# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) +# define RADEON_TXFORMAT_FORMAT_SHIFT 0 +# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) +# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) +# define RADEON_TXFORMAT_NON_POWER2 (1 << 7) +# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) +# define RADEON_TXFORMAT_WIDTH_SHIFT 8 +# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) +# define RADEON_TXFORMAT_HEIGHT_SHIFT 12 +# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) +# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 +# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 +# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) +# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) +# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) +# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) +# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) +#define RADEON_PP_CUBIC_FACES_0 0x1d24 +#define RADEON_PP_CUBIC_FACES_1 0x1d28 +#define RADEON_PP_CUBIC_FACES_2 0x1d2c +# define RADEON_FACE_WIDTH_1_SHIFT 0 +# define RADEON_FACE_HEIGHT_1_SHIFT 4 +# define RADEON_FACE_WIDTH_1_MASK (0xf << 0) +# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) +# define RADEON_FACE_WIDTH_2_SHIFT 8 +# define RADEON_FACE_HEIGHT_2_SHIFT 12 +# define RADEON_FACE_WIDTH_2_MASK (0xf << 8) +# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) +# define RADEON_FACE_WIDTH_3_SHIFT 16 +# define RADEON_FACE_HEIGHT_3_SHIFT 20 +# define RADEON_FACE_WIDTH_3_MASK (0xf << 16) +# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) +# define RADEON_FACE_WIDTH_4_SHIFT 24 +# define RADEON_FACE_HEIGHT_4_SHIFT 28 +# define RADEON_FACE_WIDTH_4_MASK (0xf << 24) +# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) + +#define RADEON_PP_TXOFFSET_0 0x1c5c +#define RADEON_PP_TXOFFSET_1 0x1c74 +#define RADEON_PP_TXOFFSET_2 0x1c8c +# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) +# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) +# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) +# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define RADEON_TXO_MACRO_LINEAR (0 << 2) +# define RADEON_TXO_MACRO_TILE (1 << 2) +# define RADEON_TXO_MICRO_LINEAR (0 << 3) +# define RADEON_TXO_MICRO_TILE_X2 (1 << 3) +# define RADEON_TXO_MICRO_TILE_OPT (2 << 3) +# define RADEON_TXO_OFFSET_MASK 0xffffffe0 +# define RADEON_TXO_OFFSET_SHIFT 5 + +#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ +#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 +#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 +#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc +#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 +#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 +#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 +#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 +#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c +#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 +#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 +#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 +#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c +#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 +#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 + +#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define RADEON_PP_TEX_SIZE_1 0x1d0c +#define RADEON_PP_TEX_SIZE_2 0x1d14 +# define RADEON_TEX_USIZE_MASK (0x7ff << 0) +# define RADEON_TEX_USIZE_SHIFT 0 +# define RADEON_TEX_VSIZE_MASK (0x7ff << 16) +# define RADEON_TEX_VSIZE_SHIFT 16 +# define RADEON_SIGNED_RGB_MASK (1 << 30) +# define RADEON_SIGNED_RGB_SHIFT 30 +# define RADEON_SIGNED_ALPHA_MASK (1 << 31) +# define RADEON_SIGNED_ALPHA_SHIFT 31 +#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ +#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ +#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ +/* note: bits 13-5: 32 byte aligned stride of texture map */ + +#define RADEON_PP_TXCBLEND_0 0x1c60 +#define RADEON_PP_TXCBLEND_1 0x1c78 +#define RADEON_PP_TXCBLEND_2 0x1c90 +# define RADEON_COLOR_ARG_A_SHIFT 0 +# define RADEON_COLOR_ARG_A_MASK (0x1f << 0) +# define RADEON_COLOR_ARG_A_ZERO (0 << 0) +# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) +# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) +# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) +# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) +# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) +# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) +# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) +# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) +# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) +# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) +# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) +# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) +# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) +# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) +# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) +# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) +# define RADEON_COLOR_ARG_B_SHIFT 5 +# define RADEON_COLOR_ARG_B_MASK (0x1f << 5) +# define RADEON_COLOR_ARG_B_ZERO (0 << 5) +# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) +# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) +# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) +# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) +# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) +# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) +# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) +# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) +# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) +# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) +# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) +# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) +# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) +# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) +# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) +# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) +# define RADEON_COLOR_ARG_C_SHIFT 10 +# define RADEON_COLOR_ARG_C_MASK (0x1f << 10) +# define RADEON_COLOR_ARG_C_ZERO (0 << 10) +# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) +# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) +# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) +# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) +# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) +# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) +# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) +# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) +# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) +# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) +# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) +# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) +# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) +# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) +# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) +# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) +# define RADEON_COMP_ARG_A (1 << 15) +# define RADEON_COMP_ARG_A_SHIFT 15 +# define RADEON_COMP_ARG_B (1 << 16) +# define RADEON_COMP_ARG_B_SHIFT 16 +# define RADEON_COMP_ARG_C (1 << 17) +# define RADEON_COMP_ARG_C_SHIFT 17 +# define RADEON_BLEND_CTL_MASK (7 << 18) +# define RADEON_BLEND_CTL_ADD (0 << 18) +# define RADEON_BLEND_CTL_SUBTRACT (1 << 18) +# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) +# define RADEON_BLEND_CTL_BLEND (3 << 18) +# define RADEON_BLEND_CTL_DOT3 (4 << 18) +# define RADEON_SCALE_SHIFT 21 +# define RADEON_SCALE_MASK (3 << 21) +# define RADEON_SCALE_1X (0 << 21) +# define RADEON_SCALE_2X (1 << 21) +# define RADEON_SCALE_4X (2 << 21) +# define RADEON_CLAMP_TX (1 << 23) +# define RADEON_T0_EQ_TCUR (1 << 24) +# define RADEON_T1_EQ_TCUR (1 << 25) +# define RADEON_T2_EQ_TCUR (1 << 26) +# define RADEON_T3_EQ_TCUR (1 << 27) +# define RADEON_COLOR_ARG_MASK 0x1f +# define RADEON_COMP_ARG_SHIFT 15 +#define RADEON_PP_TXABLEND_0 0x1c64 +#define RADEON_PP_TXABLEND_1 0x1c7c +#define RADEON_PP_TXABLEND_2 0x1c94 +# define RADEON_ALPHA_ARG_A_SHIFT 0 +# define RADEON_ALPHA_ARG_A_MASK (0xf << 0) +# define RADEON_ALPHA_ARG_A_ZERO (0 << 0) +# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) +# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) +# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) +# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) +# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) +# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) +# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) +# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) +# define RADEON_ALPHA_ARG_B_SHIFT 4 +# define RADEON_ALPHA_ARG_B_MASK (0xf << 4) +# define RADEON_ALPHA_ARG_B_ZERO (0 << 4) +# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) +# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) +# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) +# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) +# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) +# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) +# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) +# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) +# define RADEON_ALPHA_ARG_C_SHIFT 8 +# define RADEON_ALPHA_ARG_C_MASK (0xf << 8) +# define RADEON_ALPHA_ARG_C_ZERO (0 << 8) +# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) +# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) +# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) +# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) +# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) +# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) +# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) +# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) +# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) +# define RADEON_ALPHA_ARG_MASK 0xf + +#define RADEON_PP_TFACTOR_0 0x1c68 +#define RADEON_PP_TFACTOR_1 0x1c80 +#define RADEON_PP_TFACTOR_2 0x1c98 + +#define RADEON_RB3D_BLENDCNTL 0x1c20 +# define RADEON_COMB_FCN_MASK (3 << 12) +# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) +# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) +# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) +# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) +# define RADEON_SRC_BLEND_GL_ZERO (32 << 16) +# define RADEON_SRC_BLEND_GL_ONE (33 << 16) +# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) +# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) +# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) +# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) +# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) +# define RADEON_SRC_BLEND_MASK (63 << 16) +# define RADEON_DST_BLEND_GL_ZERO (32 << 24) +# define RADEON_DST_BLEND_GL_ONE (33 << 24) +# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) +# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) +# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) +# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) +# define RADEON_DST_BLEND_MASK (63 << 24) +#define RADEON_RB3D_CNTL 0x1c3c +# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) +# define RADEON_PLANE_MASK_ENABLE (1 << 1) +# define RADEON_DITHER_ENABLE (1 << 2) +# define RADEON_ROUND_ENABLE (1 << 3) +# define RADEON_SCALE_DITHER_ENABLE (1 << 4) +# define RADEON_DITHER_INIT (1 << 5) +# define RADEON_ROP_ENABLE (1 << 6) +# define RADEON_STENCIL_ENABLE (1 << 7) +# define RADEON_Z_ENABLE (1 << 8) +# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) +# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) +# define RADEON_COLOR_FORMAT_RGB565 (4 << 10) +# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) +# define RADEON_COLOR_FORMAT_RGB332 (7 << 10) +# define RADEON_COLOR_FORMAT_Y8 (8 << 10) +# define RADEON_COLOR_FORMAT_RGB8 (9 << 10) +# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) +# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) +# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) +# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) +# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) +# define RADEON_ZBLOCK16 (1 << 15) +#define RADEON_RB3D_COLOROFFSET 0x1c40 +# define RADEON_COLOROFFSET_MASK 0xfffffff0 +#define RADEON_RB3D_COLORPITCH 0x1c48 +# define RADEON_COLORPITCH_MASK 0x000001ff8 +# define RADEON_COLOR_TILE_ENABLE (1 << 16) +# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) +# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) +# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) +# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) +#define RADEON_RB3D_DEPTHOFFSET 0x1c24 +#define RADEON_RB3D_DEPTHPITCH 0x1c28 +# define RADEON_DEPTHPITCH_MASK 0x00001ff8 +# define RADEON_DEPTH_HYPERZ (3 << 16) +# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) +# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) +# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) +#define RADEON_RB3D_PLANEMASK 0x1d84 +#define RADEON_RB3D_ROPCNTL 0x1d80 +# define RADEON_ROP_MASK (15 << 8) +# define RADEON_ROP_CLEAR (0 << 8) +# define RADEON_ROP_NOR (1 << 8) +# define RADEON_ROP_AND_INVERTED (2 << 8) +# define RADEON_ROP_COPY_INVERTED (3 << 8) +# define RADEON_ROP_AND_REVERSE (4 << 8) +# define RADEON_ROP_INVERT (5 << 8) +# define RADEON_ROP_XOR (6 << 8) +# define RADEON_ROP_NAND (7 << 8) +# define RADEON_ROP_AND (8 << 8) +# define RADEON_ROP_EQUIV (9 << 8) +# define RADEON_ROP_NOOP (10 << 8) +# define RADEON_ROP_OR_INVERTED (11 << 8) +# define RADEON_ROP_COPY (12 << 8) +# define RADEON_ROP_OR_REVERSE (13 << 8) +# define RADEON_ROP_OR (14 << 8) +# define RADEON_ROP_SET (15 << 8) +#define RADEON_RB3D_STENCILREFMASK 0x1d7c +# define RADEON_STENCIL_REF_SHIFT 0 +# define RADEON_STENCIL_REF_MASK (0xff << 0) +# define RADEON_STENCIL_MASK_SHIFT 16 +# define RADEON_STENCIL_VALUE_MASK (0xff << 16) +# define RADEON_STENCIL_WRITEMASK_SHIFT 24 +# define RADEON_STENCIL_WRITE_MASK (0xff << 24) +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +# define RADEON_DEPTH_FORMAT_MASK (0xf << 0) +# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) +# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) +# define RADEON_Z_TEST_NEVER (0 << 4) +# define RADEON_Z_TEST_LESS (1 << 4) +# define RADEON_Z_TEST_LEQUAL (2 << 4) +# define RADEON_Z_TEST_EQUAL (3 << 4) +# define RADEON_Z_TEST_GEQUAL (4 << 4) +# define RADEON_Z_TEST_GREATER (5 << 4) +# define RADEON_Z_TEST_NEQUAL (6 << 4) +# define RADEON_Z_TEST_ALWAYS (7 << 4) +# define RADEON_Z_TEST_MASK (7 << 4) +# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) +# define RADEON_STENCIL_TEST_NEVER (0 << 12) +# define RADEON_STENCIL_TEST_LESS (1 << 12) +# define RADEON_STENCIL_TEST_LEQUAL (2 << 12) +# define RADEON_STENCIL_TEST_EQUAL (3 << 12) +# define RADEON_STENCIL_TEST_GEQUAL (4 << 12) +# define RADEON_STENCIL_TEST_GREATER (5 << 12) +# define RADEON_STENCIL_TEST_NEQUAL (6 << 12) +# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) +# define RADEON_STENCIL_TEST_MASK (0x7 << 12) +# define RADEON_STENCIL_FAIL_KEEP (0 << 16) +# define RADEON_STENCIL_FAIL_ZERO (1 << 16) +# define RADEON_STENCIL_FAIL_REPLACE (2 << 16) +# define RADEON_STENCIL_FAIL_INC (3 << 16) +# define RADEON_STENCIL_FAIL_DEC (4 << 16) +# define RADEON_STENCIL_FAIL_INVERT (5 << 16) +# define RADEON_STENCIL_FAIL_INC_WRAP (6 << 16) +# define RADEON_STENCIL_FAIL_DEC_WRAP (7 << 16) +# define RADEON_STENCIL_FAIL_MASK (0x7 << 16) +# define RADEON_STENCIL_ZPASS_KEEP (0 << 20) +# define RADEON_STENCIL_ZPASS_ZERO (1 << 20) +# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) +# define RADEON_STENCIL_ZPASS_INC (3 << 20) +# define RADEON_STENCIL_ZPASS_DEC (4 << 20) +# define RADEON_STENCIL_ZPASS_INVERT (5 << 20) +# define RADEON_STENCIL_ZPASS_INC_WRAP (6 << 20) +# define RADEON_STENCIL_ZPASS_DEC_WRAP (7 << 20) +# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) +# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) +# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) +# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) +# define RADEON_STENCIL_ZFAIL_INC (3 << 24) +# define RADEON_STENCIL_ZFAIL_DEC (4 << 24) +# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) +# define RADEON_STENCIL_ZFAIL_INC_WRAP (6 << 24) +# define RADEON_STENCIL_ZFAIL_DEC_WRAP (7 << 24) +# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) +# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) +# define RADEON_FORCE_Z_DIRTY (1 << 29) +# define RADEON_Z_WRITE_ENABLE (1 << 30) +# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) +#define RADEON_RE_LINE_PATTERN 0x1cd0 +# define RADEON_LINE_PATTERN_MASK 0x0000ffff +# define RADEON_LINE_REPEAT_COUNT_SHIFT 16 +# define RADEON_LINE_PATTERN_START_SHIFT 24 +# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) +# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) +# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) +#define RADEON_RE_LINE_STATE 0x1cd4 +# define RADEON_LINE_CURRENT_PTR_SHIFT 0 +# define RADEON_LINE_CURRENT_COUNT_SHIFT 8 +#define RADEON_RE_MISC 0x26c4 +# define RADEON_STIPPLE_COORD_MASK 0x1f +# define RADEON_STIPPLE_X_OFFSET_SHIFT 0 +# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) +# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 +# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) +# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) +# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) +#define RADEON_RE_SOLID_COLOR 0x1c1c +#define RADEON_RE_TOP_LEFT 0x26c0 +# define RADEON_RE_LEFT_SHIFT 0 +# define RADEON_RE_TOP_SHIFT 16 +#define RADEON_RE_WIDTH_HEIGHT 0x1c44 +# define RADEON_RE_WIDTH_SHIFT 0 +# define RADEON_RE_HEIGHT_SHIFT 16 + +#define RADEON_SE_CNTL 0x1c4c +# define RADEON_FFACE_CULL_CW (0 << 0) +# define RADEON_FFACE_CULL_CCW (1 << 0) +# define RADEON_FFACE_CULL_DIR_MASK (1 << 0) +# define RADEON_BFACE_CULL (0 << 1) +# define RADEON_BFACE_SOLID (3 << 1) +# define RADEON_FFACE_CULL (0 << 3) +# define RADEON_FFACE_SOLID (3 << 3) +# define RADEON_FFACE_CULL_MASK (3 << 3) +# define RADEON_BADVTX_CULL_DISABLE (1 << 5) +# define RADEON_FLAT_SHADE_VTX_0 (0 << 6) +# define RADEON_FLAT_SHADE_VTX_1 (1 << 6) +# define RADEON_FLAT_SHADE_VTX_2 (2 << 6) +# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) +# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) +# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) +# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) +# define RADEON_DIFFUSE_SHADE_MASK (3 << 8) +# define RADEON_ALPHA_SHADE_SOLID (0 << 10) +# define RADEON_ALPHA_SHADE_FLAT (1 << 10) +# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) +# define RADEON_ALPHA_SHADE_MASK (3 << 10) +# define RADEON_SPECULAR_SHADE_SOLID (0 << 12) +# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) +# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) +# define RADEON_SPECULAR_SHADE_MASK (3 << 12) +# define RADEON_FOG_SHADE_SOLID (0 << 14) +# define RADEON_FOG_SHADE_FLAT (1 << 14) +# define RADEON_FOG_SHADE_GOURAUD (2 << 14) +# define RADEON_FOG_SHADE_MASK (3 << 14) +# define RADEON_ZBIAS_ENABLE_POINT (1 << 16) +# define RADEON_ZBIAS_ENABLE_LINE (1 << 17) +# define RADEON_ZBIAS_ENABLE_TRI (1 << 18) +# define RADEON_WIDELINE_ENABLE (1 << 20) +# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) +# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) +# define RADEON_VTX_PIX_CENTER_D3D (0 << 27) +# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) +# define RADEON_ROUND_MODE_TRUNC (0 << 28) +# define RADEON_ROUND_MODE_ROUND (1 << 28) +# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) +# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) +# define RADEON_ROUND_PREC_16TH_PIX (0 << 30) +# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) +# define RADEON_ROUND_PREC_4TH_PIX (2 << 30) +# define RADEON_ROUND_PREC_HALF_PIX (3 << 30) +#define RADEON_SE_CNTL_STATUS 0x2140 +# define RADEON_VC_NO_SWAP (0 << 0) +# define RADEON_VC_16BIT_SWAP (1 << 0) +# define RADEON_VC_32BIT_SWAP (2 << 0) +# define RADEON_VC_HALF_DWORD_SWAP (3 << 0) +# define RADEON_TCL_BYPASS (1 << 8) +#define RADEON_SE_COORD_FMT 0x1c50 +# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) +# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) +# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) +# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) +# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) +# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) +# define RADEON_VTX_W0_NORMALIZE (1 << 12) +# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) +# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) +# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) +# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) +# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) +# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) +# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) +#define RADEON_SE_LINE_WIDTH 0x1db8 +#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c +# define RADEON_LIGHTING_ENABLE (1 << 0) +# define RADEON_LIGHT_IN_MODELSPACE (1 << 1) +# define RADEON_LOCAL_VIEWER (1 << 2) +# define RADEON_NORMALIZE_NORMALS (1 << 3) +# define RADEON_RESCALE_NORMALS (1 << 4) +# define RADEON_SPECULAR_LIGHTS (1 << 5) +# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) +# define RADEON_LIGHT_ALPHA (1 << 7) +# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) +# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) +# define RADEON_LM_SOURCE_STATE_PREMULT 0 +# define RADEON_LM_SOURCE_STATE_MULT 1 +# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 +# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 +# define RADEON_EMISSIVE_SOURCE_SHIFT 16 +# define RADEON_AMBIENT_SOURCE_SHIFT 18 +# define RADEON_DIFFUSE_SOURCE_SHIFT 20 +# define RADEON_SPECULAR_SOURCE_SHIFT 22 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c +#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c +#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c +# define RADEON_MODELVIEW_0_SHIFT 0 +# define RADEON_MODELVIEW_1_SHIFT 4 +# define RADEON_MODELVIEW_2_SHIFT 8 +# define RADEON_MODELVIEW_3_SHIFT 12 +# define RADEON_IT_MODELVIEW_0_SHIFT 16 +# define RADEON_IT_MODELVIEW_1_SHIFT 20 +# define RADEON_IT_MODELVIEW_2_SHIFT 24 +# define RADEON_IT_MODELVIEW_3_SHIFT 28 +#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 +# define RADEON_MODELPROJECT_0_SHIFT 0 +# define RADEON_MODELPROJECT_1_SHIFT 4 +# define RADEON_MODELPROJECT_2_SHIFT 8 +# define RADEON_MODELPROJECT_3_SHIFT 12 +# define RADEON_TEXMAT_0_SHIFT 16 +# define RADEON_TEXMAT_1_SHIFT 20 +# define RADEON_TEXMAT_2_SHIFT 24 +# define RADEON_TEXMAT_3_SHIFT 28 + + +#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 +# define RADEON_TCL_VTX_W0 (1 << 0) +# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) +# define RADEON_TCL_VTX_FP_ALPHA (1 << 2) +# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) +# define RADEON_TCL_VTX_FP_SPEC (1 << 4) +# define RADEON_TCL_VTX_FP_FOG (1 << 5) +# define RADEON_TCL_VTX_PK_SPEC (1 << 6) +# define RADEON_TCL_VTX_ST0 (1 << 7) +# define RADEON_TCL_VTX_ST1 (1 << 8) +# define RADEON_TCL_VTX_Q1 (1 << 9) +# define RADEON_TCL_VTX_ST2 (1 << 10) +# define RADEON_TCL_VTX_Q2 (1 << 11) +# define RADEON_TCL_VTX_ST3 (1 << 12) +# define RADEON_TCL_VTX_Q3 (1 << 13) +# define RADEON_TCL_VTX_Q0 (1 << 14) +# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 +# define RADEON_TCL_VTX_NORM0 (1 << 18) +# define RADEON_TCL_VTX_XY1 (1 << 27) +# define RADEON_TCL_VTX_Z1 (1 << 28) +# define RADEON_TCL_VTX_W1 (1 << 29) +# define RADEON_TCL_VTX_NORM1 (1 << 30) +# define RADEON_TCL_VTX_Z0 (1 << 31) + +#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 +# define RADEON_TCL_COMPUTE_XYZW (1 << 0) +# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) +# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) +# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) +# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) +# define RADEON_TCL_TEX_INPUT_TEX_0 0 +# define RADEON_TCL_TEX_INPUT_TEX_1 1 +# define RADEON_TCL_TEX_INPUT_TEX_2 2 +# define RADEON_TCL_TEX_INPUT_TEX_3 3 +# define RADEON_TCL_TEX_COMPUTED_TEX_0 8 +# define RADEON_TCL_TEX_COMPUTED_TEX_1 9 +# define RADEON_TCL_TEX_COMPUTED_TEX_2 10 +# define RADEON_TCL_TEX_COMPUTED_TEX_3 11 +# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 +# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 +# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 +# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 + +#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 +# define RADEON_LIGHT_0_ENABLE (1 << 0) +# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) +# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) +# define RADEON_LIGHT_0_IS_LOCAL (1 << 3) +# define RADEON_LIGHT_0_IS_SPOT (1 << 4) +# define RADEON_LIGHT_0_DUAL_CONE (1 << 5) +# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) +# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) +# define RADEON_LIGHT_0_SHIFT 0 +# define RADEON_LIGHT_1_ENABLE (1 << 16) +# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) +# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) +# define RADEON_LIGHT_1_IS_LOCAL (1 << 19) +# define RADEON_LIGHT_1_IS_SPOT (1 << 20) +# define RADEON_LIGHT_1_DUAL_CONE (1 << 21) +# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) +# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) +# define RADEON_LIGHT_1_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 +# define RADEON_LIGHT_2_SHIFT 0 +# define RADEON_LIGHT_3_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 +# define RADEON_LIGHT_4_SHIFT 0 +# define RADEON_LIGHT_5_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c +# define RADEON_LIGHT_6_SHIFT 0 +# define RADEON_LIGHT_7_SHIFT 16 + +#define RADEON_SE_TCL_STATE_FLUSH 0x2284 + +#define RADEON_SE_TCL_SHININESS 0x2250 + +#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 +# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) +# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) +# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) +# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) +# define RADEON_TEXMAT_0_ENABLE (1 << 4) +# define RADEON_TEXMAT_1_ENABLE (1 << 5) +# define RADEON_TEXMAT_2_ENABLE (1 << 6) +# define RADEON_TEXMAT_3_ENABLE (1 << 7) +# define RADEON_TEXGEN_INPUT_MASK 0xf +# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 +# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 +# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 +# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 +# define RADEON_TEXGEN_INPUT_OBJ 4 +# define RADEON_TEXGEN_INPUT_EYE 5 +# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 +# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 +# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 +# define RADEON_TEXGEN_0_INPUT_SHIFT 16 +# define RADEON_TEXGEN_1_INPUT_SHIFT 20 +# define RADEON_TEXGEN_2_INPUT_SHIFT 24 +# define RADEON_TEXGEN_3_INPUT_SHIFT 28 + +#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 +# define RADEON_UCP_IN_CLIP_SPACE (1 << 0) +# define RADEON_UCP_IN_MODEL_SPACE (1 << 1) +# define RADEON_UCP_ENABLE_0 (1 << 2) +# define RADEON_UCP_ENABLE_1 (1 << 3) +# define RADEON_UCP_ENABLE_2 (1 << 4) +# define RADEON_UCP_ENABLE_3 (1 << 5) +# define RADEON_UCP_ENABLE_4 (1 << 6) +# define RADEON_UCP_ENABLE_5 (1 << 7) +# define RADEON_TCL_FOG_MASK (3 << 8) +# define RADEON_TCL_FOG_DISABLE (0 << 8) +# define RADEON_TCL_FOG_EXP (1 << 8) +# define RADEON_TCL_FOG_EXP2 (2 << 8) +# define RADEON_TCL_FOG_LINEAR (3 << 8) +# define RADEON_RNG_BASED_FOG (1 << 10) +# define RADEON_LIGHT_TWOSIDE (1 << 11) +# define RADEON_BLEND_OP_COUNT_MASK (7 << 12) +# define RADEON_BLEND_OP_COUNT_SHIFT 12 +# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) +# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) +# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (0 << 18) +# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) +# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (0 << 19) +# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) +# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (0 << 20) +# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) +# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (0 << 21) +# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) +# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) +# define RADEON_CULL_FRONT_IS_CW (0 << 28) +# define RADEON_CULL_FRONT_IS_CCW (1 << 28) +# define RADEON_CULL_FRONT (1 << 29) +# define RADEON_CULL_BACK (1 << 30) +# define RADEON_FORCE_W_TO_ONE (1 << 31) + +#define RADEON_SE_VPORT_XSCALE 0x1d98 +#define RADEON_SE_VPORT_XOFFSET 0x1d9c +#define RADEON_SE_VPORT_YSCALE 0x1da0 +#define RADEON_SE_VPORT_YOFFSET 0x1da4 +#define RADEON_SE_VPORT_ZSCALE 0x1da8 +#define RADEON_SE_VPORT_ZOFFSET 0x1dac +#define RADEON_SE_ZBIAS_FACTOR 0x1db0 +#define RADEON_SE_ZBIAS_CONSTANT 0x1db4 + + + + /* Registers for CP and Microcode Engine */ +#define RADEON_CP_ME_RAM_ADDR 0x07d4 +#define RADEON_CP_ME_RAM_RADDR 0x07d8 +#define RADEON_CP_ME_RAM_DATAH 0x07dc +#define RADEON_CP_ME_RAM_DATAL 0x07e0 + +#define RADEON_CP_RB_BASE 0x0700 +#define RADEON_CP_RB_CNTL 0x0704 +#define RADEON_CP_RB_RPTR_ADDR 0x070c +#define RADEON_CP_RB_RPTR 0x0710 +#define RADEON_CP_RB_WPTR 0x0714 + +#define RADEON_CP_IB_BASE 0x0738 +#define RADEON_CP_IB_BUFSZ 0x073c + +#define RADEON_CP_CSQ_CNTL 0x0740 +# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) +# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) +# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) +# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) +# define RADEON_CSQ_PRIBM_INDBM (4 << 28) +# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) +#define RADEON_CP_CSQ_STAT 0x07f8 +# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) +# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) +# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) +#define RADEON_CP_CSQ_ADDR 0x07f0 +#define RADEON_CP_CSQ_DATA 0x07f4 +#define RADEON_CP_CSQ_APER_PRIMARY 0x1000 +#define RADEON_CP_CSQ_APER_INDIRECT 0x1300 + +#define RADEON_CP_RB_WPTR_DELAY 0x0718 +# define RADEON_PRE_WRITE_TIMER_SHIFT 0 +# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 + +#define RADEON_AIC_CNTL 0x01d0 +# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) +#define RADEON_AIC_LO_ADDR 0x01dc + + + + /* Constants */ +#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 +#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 + + + + /* CP packet types */ +#define RADEON_CP_PACKET0 0x00000000 +#define RADEON_CP_PACKET1 0x40000000 +#define RADEON_CP_PACKET2 0x80000000 +#define RADEON_CP_PACKET3 0xC0000000 +# define RADEON_CP_PACKET_MASK 0xC0000000 +# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 +# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) +# define RADEON_CP_PACKET0_REG_MASK 0x000007ff +# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff +# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 + +#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 + +#define RADEON_CP_PACKET3_NOP 0xC0001000 +#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 +#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 +#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 +#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 +#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 +#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 +#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 +#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 +#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 +#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 +#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 +#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 +#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 +#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 +#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 +#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 +#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 +#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 +#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 + + +#define RADEON_CP_VC_FRMT_XY 0x00000000 +#define RADEON_CP_VC_FRMT_W0 0x00000001 +#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 +#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 +#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 +#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 +#define RADEON_CP_VC_FRMT_FPFOG 0x00000020 +#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 +#define RADEON_CP_VC_FRMT_ST0 0x00000080 +#define RADEON_CP_VC_FRMT_ST1 0x00000100 +#define RADEON_CP_VC_FRMT_Q1 0x00000200 +#define RADEON_CP_VC_FRMT_ST2 0x00000400 +#define RADEON_CP_VC_FRMT_Q2 0x00000800 +#define RADEON_CP_VC_FRMT_ST3 0x00001000 +#define RADEON_CP_VC_FRMT_Q3 0x00002000 +#define RADEON_CP_VC_FRMT_Q0 0x00004000 +#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 +#define RADEON_CP_VC_FRMT_N0 0x00040000 +#define RADEON_CP_VC_FRMT_XY1 0x08000000 +#define RADEON_CP_VC_FRMT_Z1 0x10000000 +#define RADEON_CP_VC_FRMT_W1 0x20000000 +#define RADEON_CP_VC_FRMT_N1 0x40000000 +#define RADEON_CP_VC_FRMT_Z 0x80000000 + +#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a +#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 +#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 +#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 +#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 +#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 +#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 +#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 +#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 +#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 + +#define RADEON_VS_MATRIX_0_ADDR 0 +#define RADEON_VS_MATRIX_1_ADDR 4 +#define RADEON_VS_MATRIX_2_ADDR 8 +#define RADEON_VS_MATRIX_3_ADDR 12 +#define RADEON_VS_MATRIX_4_ADDR 16 +#define RADEON_VS_MATRIX_5_ADDR 20 +#define RADEON_VS_MATRIX_6_ADDR 24 +#define RADEON_VS_MATRIX_7_ADDR 28 +#define RADEON_VS_MATRIX_8_ADDR 32 +#define RADEON_VS_MATRIX_9_ADDR 36 +#define RADEON_VS_MATRIX_10_ADDR 40 +#define RADEON_VS_MATRIX_11_ADDR 44 +#define RADEON_VS_MATRIX_12_ADDR 48 +#define RADEON_VS_MATRIX_13_ADDR 52 +#define RADEON_VS_MATRIX_14_ADDR 56 +#define RADEON_VS_MATRIX_15_ADDR 60 +#define RADEON_VS_LIGHT_AMBIENT_ADDR 64 +#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 +#define RADEON_VS_LIGHT_SPECULAR_ADDR 80 +#define RADEON_VS_LIGHT_DIRPOS_ADDR 88 +#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 +#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 +#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 +#define RADEON_VS_UCP_ADDR 116 +#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 +#define RADEON_VS_FOG_PARAM_ADDR 123 +#define RADEON_VS_EYE_VECTOR_ADDR 124 + +#define RADEON_SS_LIGHT_DCD_ADDR 0 +#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 +#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 +#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 +#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 +#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 +#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 +#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 +#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 +#define RADEON_SS_SHININESS 60 + +#define RADEON_TV_MASTER_CNTL 0x0800 +# define RADEON_TVCLK_ALWAYS_ONb (1 << 30) +#define RADEON_TV_DAC_CNTL 0x088c +# define RADEON_TV_DAC_CMPOUT (1 << 5) +#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 +# define RADEON_Y_RED_EN (1 << 0) +# define RADEON_C_GRN_EN (1 << 1) +# define RADEON_CMP_BLU_EN (1 << 2) +# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) +# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) +# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) +# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 +#endif diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_chipset.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_chipset.h new file mode 100644 index 00000000000..7318099093a --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_chipset.h @@ -0,0 +1,181 @@ +#ifndef _RADEON_CHIPSET_H +#define _RADEON_CHIPSET_H +/* Including xf86PciInfo.h introduces a bunch of errors... + */ + +/* General chip classes: + * r100 includes R100, RV100, RV200, RS100, RS200, RS250. + * r200 includes R200, RV250, RV280, RS300. + * r300 includes R300, RV350, RV370. + * (RS* denotes IGP) + */ +#define PCI_CHIP_RV380_3150 0x3150 +#define PCI_CHIP_RV380_3152 0x3152 +#define PCI_CHIP_RV380_3154 0x3154 +#define PCI_CHIP_RV380_3E50 0x3E50 +#define PCI_CHIP_RV380_3E54 0x3E54 +#define PCI_CHIP_RS100_4136 0x4136 +#define PCI_CHIP_RS200_4137 0x4137 +#define PCI_CHIP_R300_AD 0x4144 +#define PCI_CHIP_R300_AE 0x4145 +#define PCI_CHIP_R300_AF 0x4146 +#define PCI_CHIP_R300_AG 0x4147 +#define PCI_CHIP_R350_AH 0x4148 +#define PCI_CHIP_R350_AI 0x4149 +#define PCI_CHIP_R350_AJ 0x414A +#define PCI_CHIP_R350_AK 0x414B +#define PCI_CHIP_RV350_AP 0x4150 +#define PCI_CHIP_RV350_AQ 0x4151 +#define PCI_CHIP_RV350_AR 0x4152 +#define PCI_CHIP_RV350_AS 0x4153 +#define PCI_CHIP_RV350_AT 0x4154 +#define PCI_CHIP_RV350_AU 0x4155 +#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_RS250_4237 0x4237 +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_R200_BC 0x4243 +#define PCI_CHIP_RS100_4336 0x4336 +#define PCI_CHIP_RS200_4337 0x4337 +#define PCI_CHIP_RS250_4437 0x4437 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_R420_JH 0x4A48 +#define PCI_CHIP_R420_JI 0x4A49 +#define PCI_CHIP_R420_JJ 0x4A4A +#define PCI_CHIP_R420_JK 0x4A4B +#define PCI_CHIP_R420_JL 0x4A4C +#define PCI_CHIP_R420_JM 0x4A4D +#define PCI_CHIP_R420_JN 0x4A4E +#define PCI_CHIP_R420_JO 0x4A4F +#define PCI_CHIP_R420_JP 0x4A50 +#define PCI_CHIP_R420_JT 0x4A54 +#define PCI_CHIP_R481_4B49 0x4B49 +#define PCI_CHIP_R481_4B4A 0x4B4A +#define PCI_CHIP_R481_4B4B 0x4B4B +#define PCI_CHIP_R481_4B4C 0x4B4C +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_R350_NH 0x4E48 +#define PCI_CHIP_R350_NI 0x4E49 +#define PCI_CHIP_R360_NJ 0x4E4A +#define PCI_CHIP_R350_NK 0x4E4B +#define PCI_CHIP_RV350_NP 0x4E50 +#define PCI_CHIP_RV350_NQ 0x4E51 +#define PCI_CHIP_RV350_NR 0x4E52 +#define PCI_CHIP_RV350_NS 0x4E53 +#define PCI_CHIP_RV350_NT 0x4E54 +#define PCI_CHIP_RV350_NV 0x4E56 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_R200_QH 0x5148 +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QM 0x514D +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RADEON_QY 0x5159 +#define PCI_CHIP_RADEON_QZ 0x515A +#define PCI_CHIP_RN50_515E 0x515E +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV370_5462 0x5462 +#define PCI_CHIP_RV370_5464 0x5464 +#define PCI_CHIP_R423_UH 0x5548 +#define PCI_CHIP_R423_UI 0x5549 +#define PCI_CHIP_R423_UJ 0x554A +#define PCI_CHIP_R423_UK 0x554B +#define PCI_CHIP_R430_554C 0x554C +#define PCI_CHIP_R430_554D 0x554D +#define PCI_CHIP_R430_554E 0x554E +#define PCI_CHIP_R430_554F 0x554F +#define PCI_CHIP_R423_5550 0x5550 +#define PCI_CHIP_R423_UQ 0x5551 +#define PCI_CHIP_R423_UR 0x5552 +#define PCI_CHIP_R423_UT 0x5554 +#define PCI_CHIP_RV410_564A 0x564A +#define PCI_CHIP_RV410_564B 0x564B +#define PCI_CHIP_RV410_564F 0x564F +#define PCI_CHIP_RV410_5652 0x5652 +#define PCI_CHIP_RV410_5653 0x5653 +#define PCI_CHIP_RS300_5834 0x5834 +#define PCI_CHIP_RS300_5835 0x5835 +#define PCI_CHIP_RS480_5954 0x5954 +#define PCI_CHIP_RS480_5955 0x5955 +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5965 0x5965 +#define PCI_CHIP_RN50_5969 0x5969 +#define PCI_CHIP_RS482_5974 0x5974 +#define PCI_CHIP_RS482_5975 0x5975 +#define PCI_CHIP_RS400_5A41 0x5A41 +#define PCI_CHIP_RS400_5A42 0x5A42 +#define PCI_CHIP_RC410_5A61 0x5A61 +#define PCI_CHIP_RC410_5A62 0x5A62 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV370_5B62 0x5B62 +#define PCI_CHIP_RV370_5B63 0x5B63 +#define PCI_CHIP_RV370_5B64 0x5B64 +#define PCI_CHIP_RV370_5B65 0x5B65 +#define PCI_CHIP_RV280_5C61 0x5C61 +#define PCI_CHIP_RV280_5C63 0x5C63 +#define PCI_CHIP_R430_5D48 0x5D48 +#define PCI_CHIP_R430_5D49 0x5D49 +#define PCI_CHIP_R430_5D4A 0x5D4A +#define PCI_CHIP_R480_5D4C 0x5D4C +#define PCI_CHIP_R480_5D4D 0x5D4D +#define PCI_CHIP_R480_5D4E 0x5D4E +#define PCI_CHIP_R480_5D4F 0x5D4F +#define PCI_CHIP_R480_5D50 0x5D50 +#define PCI_CHIP_R480_5D52 0x5D52 +#define PCI_CHIP_R423_5D57 0x5D57 +#define PCI_CHIP_RV410_5E48 0x5E48 +#define PCI_CHIP_RV410_5E4A 0x5E4A +#define PCI_CHIP_RV410_5E4B 0x5E4B +#define PCI_CHIP_RV410_5E4C 0x5E4C +#define PCI_CHIP_RV410_5E4D 0x5E4D +#define PCI_CHIP_RV410_5E4F 0x5E4F +#define PCI_CHIP_RS350_7834 0x7834 +#define PCI_CHIP_RS350_7835 0x7835 + +enum { + CHIP_FAMILY_R100, + CHIP_FAMILY_RV100, + CHIP_FAMILY_RS100, + CHIP_FAMILY_RV200, + CHIP_FAMILY_RS200, + CHIP_FAMILY_R200, + CHIP_FAMILY_RV250, + CHIP_FAMILY_RS300, + CHIP_FAMILY_RV280, + CHIP_FAMILY_R300, + CHIP_FAMILY_R350, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, + CHIP_FAMILY_R420, + CHIP_FAMILY_RV410, + CHIP_FAMILY_RS400, + CHIP_FAMILY_LAST +}; + +/* General classes of Radeons, as described above the device ID section */ +#define RADEON_CLASS_R100 (0 << 0) +#define RADEON_CLASS_R200 (1 << 0) +#define RADEON_CLASS_R300 (2 << 0) +#define RADEON_CLASS_MASK (3 << 0) + +#define RADEON_CHIPSET_TCL (1 << 2) /* tcl support - any radeon */ +#define RADEON_CHIPSET_BROKEN_STENCIL (1 << 3) /* r100 stencil bug */ +#define R200_CHIPSET_YCBCR_BROKEN (1 << 4) /* r200 ycbcr bug */ + +#endif /* _RADEON_CHIPSET_H */ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_screen.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_screen.c new file mode 100644 index 00000000000..682cf3a5ee5 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_screen.c @@ -0,0 +1,1104 @@ +/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and + VA Linux Systems Inc., Fremont, California. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/** + * \file radeon_screen.c + * Screen initialization functions for the Radeon driver. + * + * \author Kevin E. Martin + * \author Gareth Hughes + */ + +#include "glheader.h" +#include "imports.h" +#include "mtypes.h" +#include "framebuffer.h" +#include "renderbuffer.h" + +#define STANDALONE_MMIO +#include "radeon_chipset.h" +#include "radeon_macros.h" +#include "radeon_screen.h" +#if !RADEON_COMMON +#include "radeon_context.h" +#include "radeon_span.h" +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) +#include "r200_context.h" +#include "r200_ioctl.h" +#include "r200_span.h" +#include "r200_tex.h" +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) +#include "r300_context.h" +#include "r300_fragprog.h" +#include "r300_tex.h" +#include "radeon_span.h" +#endif + +#include "utils.h" +#include "context.h" +#include "vblank.h" +#include "drirenderbuffer.h" + +#include "GL/internal/dri_interface.h" + +/* Radeon configuration + */ +#include "xmlpool.h" + +#if !RADEON_COMMON /* R100 */ +PUBLIC const char __driConfigOptions[] = +DRI_CONF_BEGIN + DRI_CONF_SECTION_PERFORMANCE + DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) + DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) + DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) + DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) + DRI_CONF_HYPERZ(false) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_QUALITY + DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) + DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") + DRI_CONF_NO_NEG_LOD_BIAS(false) + DRI_CONF_FORCE_S3TC_ENABLE(false) + DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) + DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) + DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) + DRI_CONF_ALLOW_LARGE_TEXTURES(1) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_DEBUG + DRI_CONF_NO_RAST(false) + DRI_CONF_SECTION_END +DRI_CONF_END; +static const GLuint __driNConfigOptions = 14; + +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + +PUBLIC const char __driConfigOptions[] = +DRI_CONF_BEGIN + DRI_CONF_SECTION_PERFORMANCE + DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) + DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) + DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) + DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) + DRI_CONF_HYPERZ(false) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_QUALITY + DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) + DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") + DRI_CONF_NO_NEG_LOD_BIAS(false) + DRI_CONF_FORCE_S3TC_ENABLE(false) + DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) + DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) + DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) + DRI_CONF_ALLOW_LARGE_TEXTURES(1) + DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") + DRI_CONF_SECTION_END + DRI_CONF_SECTION_DEBUG + DRI_CONF_NO_RAST(false) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_SOFTWARE + DRI_CONF_NV_VERTEX_PROGRAM(false) + DRI_CONF_SECTION_END +DRI_CONF_END; +static const GLuint __driNConfigOptions = 16; + +extern const struct dri_extension blend_extensions[]; +extern const struct dri_extension ARB_vp_extension[]; +extern const struct dri_extension NV_vp_extension[]; +extern const struct dri_extension ATI_fs_extension[]; +extern const struct dri_extension point_extensions[]; + +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + +/* TODO: integrate these into xmlpool.h! */ +#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Number of texture image units") \ + DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ +DRI_CONF_OPT_END + +#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Number of texture coordinate units") \ + DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ +DRI_CONF_OPT_END + +#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ + DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_S3TC(def) \ +DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ + DRI_CONF_DESC(en,"Disable S3TC compression") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_FALLBACK(def) \ +DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ + DRI_CONF_DESC(en,"Disable Low-impact fallback") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ +DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ + DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ +DRI_CONF_OPT_END + +#define DRI_CONF_FP_OPTIMIZATION(def) \ +DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ + DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ + DRI_CONF_ENUM(0,"Optimize for Speed") \ + DRI_CONF_ENUM(1,"Optimize for Quality") \ + DRI_CONF_DESC_END \ +DRI_CONF_OPT_END + +const char __driConfigOptions[] = +DRI_CONF_BEGIN + DRI_CONF_SECTION_PERFORMANCE + DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) + DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) + DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) + DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) + DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) + DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) + DRI_CONF_DISABLE_FALLBACK(false) + DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_QUALITY + DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) + DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") + DRI_CONF_NO_NEG_LOD_BIAS(false) + DRI_CONF_FORCE_S3TC_ENABLE(false) + DRI_CONF_DISABLE_S3TC(false) + DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) + DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) + DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) + DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) + DRI_CONF_SECTION_END + DRI_CONF_SECTION_DEBUG + DRI_CONF_NO_RAST(false) + DRI_CONF_SECTION_END +DRI_CONF_END; +static const GLuint __driNConfigOptions = 18; + +#ifndef RADEON_DEBUG +int RADEON_DEBUG = 0; + +static const struct dri_debug_control debug_control[] = { + {"fall", DEBUG_FALLBACKS}, + {"tex", DEBUG_TEXTURE}, + {"ioctl", DEBUG_IOCTL}, + {"prim", DEBUG_PRIMS}, + {"vert", DEBUG_VERTS}, + {"state", DEBUG_STATE}, + {"code", DEBUG_CODEGEN}, + {"vfmt", DEBUG_VFMT}, + {"vtxf", DEBUG_VFMT}, + {"verb", DEBUG_VERBOSE}, + {"dri", DEBUG_DRI}, + {"dma", DEBUG_DMA}, + {"san", DEBUG_SANITY}, + {"sync", DEBUG_SYNC}, + {"pix", DEBUG_PIXEL}, + {"mem", DEBUG_MEMORY}, + {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ + {NULL, 0} +}; +#endif /* RADEON_DEBUG */ + +#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ + +extern const struct dri_extension card_extensions[]; + +static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); + +static int +radeonGetParam(int fd, int param, void *value) +{ + int ret; + drm_radeon_getparam_t gp; + + gp.param = param; + gp.value = value; + + ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); + return ret; +} + +static __GLcontextModes * +radeonFillInModes( unsigned pixel_bits, unsigned depth_bits, + unsigned stencil_bits, GLboolean have_back_buffer ) +{ + __GLcontextModes * modes; + __GLcontextModes * m; + unsigned num_modes; + unsigned depth_buffer_factor; + unsigned back_buffer_factor; + GLenum fb_format; + GLenum fb_type; + + /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy + * enough to add support. Basically, if a context is created with an + * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping + * will never be used. + */ + static const GLenum back_buffer_modes[] = { + GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ + }; + + u_int8_t depth_bits_array[2]; + u_int8_t stencil_bits_array[2]; + + + depth_bits_array[0] = depth_bits; + depth_bits_array[1] = depth_bits; + + /* Just like with the accumulation buffer, always provide some modes + * with a stencil buffer. It will be a sw fallback, but some apps won't + * care about that. + */ + stencil_bits_array[0] = 0; + stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; + + depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; + back_buffer_factor = (have_back_buffer) ? 2 : 1; + + num_modes = depth_buffer_factor * back_buffer_factor * 4; + + if ( pixel_bits == 16 ) { + fb_format = GL_RGB; + fb_type = GL_UNSIGNED_SHORT_5_6_5; + } + else { + fb_format = GL_BGRA; + fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; + } + + modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) ); + m = modes; + if ( ! driFillInModes( & m, fb_format, fb_type, + depth_bits_array, stencil_bits_array, depth_buffer_factor, + back_buffer_modes, back_buffer_factor, + GLX_TRUE_COLOR ) ) { + fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", + __func__, __LINE__ ); + return NULL; + } + + if ( ! driFillInModes( & m, fb_format, fb_type, + depth_bits_array, stencil_bits_array, depth_buffer_factor, + back_buffer_modes, back_buffer_factor, + GLX_DIRECT_COLOR ) ) { + fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", + __func__, __LINE__ ); + return NULL; + } + + /* Mark the visual as slow if there are "fake" stencil bits. + */ + for ( m = modes ; m != NULL ; m = m->next ) { + if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) { + m->visualRating = GLX_SLOW_CONFIG; + } + } + + return modes; +} + + +/* Create the device specific screen private data struct. + */ +static radeonScreenPtr +radeonCreateScreen( __DRIscreenPrivate *sPriv ) +{ + radeonScreenPtr screen; + RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; + unsigned char *RADEONMMIO; + PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension = + (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension")); + void * const psc = sPriv->psc->screenConfigs; + + if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { + fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); + return GL_FALSE; + } + + /* Allocate the private area */ + screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); + if ( !screen ) { + __driUtilMessage("%s: Could not allocate memory for screen structure", + __FUNCTION__); + return NULL; + } + +#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); +#endif + + /* parse information in __driConfigOptions */ + driParseOptionInfo (&screen->optionCache, + __driConfigOptions, __driNConfigOptions); + + /* This is first since which regions we map depends on whether or + * not we are using a PCI card. + */ + screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); + { + int ret; + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, + &screen->gart_buffer_offset); + + if (ret) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); + return NULL; + } + + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, + &screen->gart_base); + if (ret) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); + return NULL; + } + + ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, + &screen->irq); + if (ret) { + FREE( screen ); + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); + return NULL; + } + screen->drmSupportsCubeMapsR200 = (sPriv->drmMinor >= 7); + screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11); + screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16); + screen->drmSupportsFragShader = (sPriv->drmMinor >= 18); + screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13); + screen->drmSupportsCubeMapsR100 = (sPriv->drmMinor >= 15); + screen->drmSupportsVertexProgram = (sPriv->drmMinor >= 25); + } + + screen->mmio.handle = dri_priv->registerHandle; + screen->mmio.size = dri_priv->registerSize; + if ( drmMap( sPriv->fd, + screen->mmio.handle, + screen->mmio.size, + &screen->mmio.map ) ) { + FREE( screen ); + __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); + return NULL; + } + + RADEONMMIO = screen->mmio.map; + + screen->status.handle = dri_priv->statusHandle; + screen->status.size = dri_priv->statusSize; + if ( drmMap( sPriv->fd, + screen->status.handle, + screen->status.size, + &screen->status.map ) ) { + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); + return NULL; + } + screen->scratch = (__volatile__ u_int32_t *) + ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); + + screen->buffers = drmMapBufs( sPriv->fd ); + if ( !screen->buffers ) { + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); + return NULL; + } + + if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { + screen->gartTextures.handle = dri_priv->gartTexHandle; + screen->gartTextures.size = dri_priv->gartTexMapSize; + if ( drmMap( sPriv->fd, + screen->gartTextures.handle, + screen->gartTextures.size, + (drmAddressPtr)&screen->gartTextures.map ) ) { + drmUnmapBufs( screen->buffers ); + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + FREE( screen ); + __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); + return NULL; + } + + screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; + } + + screen->chip_flags = 0; + /* XXX: add more chipsets */ + switch ( dri_priv->deviceID ) { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + case PCI_CHIP_RADEON_QY: + case PCI_CHIP_RADEON_QZ: + case PCI_CHIP_RN50_515E: + case PCI_CHIP_RN50_5969: + screen->chip_family = CHIP_FAMILY_RV100; + break; + + case PCI_CHIP_RS100_4136: + case PCI_CHIP_RS100_4336: + screen->chip_family = CHIP_FAMILY_RS100; + break; + + case PCI_CHIP_RS200_4137: + case PCI_CHIP_RS200_4337: + case PCI_CHIP_RS250_4237: + case PCI_CHIP_RS250_4437: + screen->chip_family = CHIP_FAMILY_RS200; + break; + + case PCI_CHIP_RADEON_QD: + case PCI_CHIP_RADEON_QE: + case PCI_CHIP_RADEON_QF: + case PCI_CHIP_RADEON_QG: + /* all original radeons (7200) presumably have a stencil op bug */ + screen->chip_family = CHIP_FAMILY_R100; + screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; + break; + + case PCI_CHIP_RV200_QW: + case PCI_CHIP_RV200_QX: + case PCI_CHIP_RADEON_LW: + case PCI_CHIP_RADEON_LX: + screen->chip_family = CHIP_FAMILY_RV200; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_R200_BB: + case PCI_CHIP_R200_BC: + case PCI_CHIP_R200_QH: + case PCI_CHIP_R200_QL: + case PCI_CHIP_R200_QM: + screen->chip_family = CHIP_FAMILY_R200; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV250_If: + case PCI_CHIP_RV250_Ig: + case PCI_CHIP_RV250_Ld: + case PCI_CHIP_RV250_Lf: + case PCI_CHIP_RV250_Lg: + screen->chip_family = CHIP_FAMILY_RV250; + screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV280_5960: + case PCI_CHIP_RV280_5961: + case PCI_CHIP_RV280_5962: + case PCI_CHIP_RV280_5964: + case PCI_CHIP_RV280_5965: + case PCI_CHIP_RV280_5C61: + case PCI_CHIP_RV280_5C63: + screen->chip_family = CHIP_FAMILY_RV280; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RS300_5834: + case PCI_CHIP_RS300_5835: + case PCI_CHIP_RS350_7834: + case PCI_CHIP_RS350_7835: + screen->chip_family = CHIP_FAMILY_RS300; + break; + + case PCI_CHIP_R300_AD: + case PCI_CHIP_R300_AE: + case PCI_CHIP_R300_AF: + case PCI_CHIP_R300_AG: + case PCI_CHIP_R300_ND: + case PCI_CHIP_R300_NE: + case PCI_CHIP_R300_NF: + case PCI_CHIP_R300_NG: + screen->chip_family = CHIP_FAMILY_R300; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV350_AP: + case PCI_CHIP_RV350_AQ: + case PCI_CHIP_RV350_AR: + case PCI_CHIP_RV350_AS: + case PCI_CHIP_RV350_AT: + case PCI_CHIP_RV350_AV: + case PCI_CHIP_RV350_AU: + case PCI_CHIP_RV350_NP: + case PCI_CHIP_RV350_NQ: + case PCI_CHIP_RV350_NR: + case PCI_CHIP_RV350_NS: + case PCI_CHIP_RV350_NT: + case PCI_CHIP_RV350_NV: + screen->chip_family = CHIP_FAMILY_RV350; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_R350_AH: + case PCI_CHIP_R350_AI: + case PCI_CHIP_R350_AJ: + case PCI_CHIP_R350_AK: + case PCI_CHIP_R350_NH: + case PCI_CHIP_R350_NI: + case PCI_CHIP_R360_NJ: + case PCI_CHIP_R350_NK: + screen->chip_family = CHIP_FAMILY_R350; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV370_5460: + case PCI_CHIP_RV370_5462: + case PCI_CHIP_RV370_5464: + case PCI_CHIP_RV370_5B60: + case PCI_CHIP_RV370_5B62: + case PCI_CHIP_RV370_5B63: + case PCI_CHIP_RV370_5B64: + case PCI_CHIP_RV370_5B65: + case PCI_CHIP_RV380_3150: + case PCI_CHIP_RV380_3152: + case PCI_CHIP_RV380_3154: + case PCI_CHIP_RV380_3E50: + case PCI_CHIP_RV380_3E54: + screen->chip_family = CHIP_FAMILY_RV380; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_R420_JN: + case PCI_CHIP_R420_JH: + case PCI_CHIP_R420_JI: + case PCI_CHIP_R420_JJ: + case PCI_CHIP_R420_JK: + case PCI_CHIP_R420_JL: + case PCI_CHIP_R420_JM: + case PCI_CHIP_R420_JO: + case PCI_CHIP_R420_JP: + case PCI_CHIP_R420_JT: + case PCI_CHIP_R481_4B49: + case PCI_CHIP_R481_4B4A: + case PCI_CHIP_R481_4B4B: + case PCI_CHIP_R481_4B4C: + case PCI_CHIP_R423_UH: + case PCI_CHIP_R423_UI: + case PCI_CHIP_R423_UJ: + case PCI_CHIP_R423_UK: + case PCI_CHIP_R430_554C: + case PCI_CHIP_R430_554D: + case PCI_CHIP_R430_554E: + case PCI_CHIP_R430_554F: + case PCI_CHIP_R423_5550: + case PCI_CHIP_R423_UQ: + case PCI_CHIP_R423_UR: + case PCI_CHIP_R423_UT: + case PCI_CHIP_R430_5D48: + case PCI_CHIP_R430_5D49: + case PCI_CHIP_R430_5D4A: + case PCI_CHIP_R480_5D4C: + case PCI_CHIP_R480_5D4D: + case PCI_CHIP_R480_5D4E: + case PCI_CHIP_R480_5D4F: + case PCI_CHIP_R480_5D50: + case PCI_CHIP_R480_5D52: + case PCI_CHIP_R423_5D57: + screen->chip_family = CHIP_FAMILY_R420; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RV410_564A: + case PCI_CHIP_RV410_564B: + case PCI_CHIP_RV410_564F: + case PCI_CHIP_RV410_5652: + case PCI_CHIP_RV410_5653: + case PCI_CHIP_RV410_5E48: + case PCI_CHIP_RV410_5E4A: + case PCI_CHIP_RV410_5E4B: + case PCI_CHIP_RV410_5E4C: + case PCI_CHIP_RV410_5E4D: + case PCI_CHIP_RV410_5E4F: + screen->chip_family = CHIP_FAMILY_RV410; + screen->chip_flags = RADEON_CHIPSET_TCL; + break; + + case PCI_CHIP_RS480_5954: + case PCI_CHIP_RS480_5955: + case PCI_CHIP_RS482_5974: + case PCI_CHIP_RS482_5975: + case PCI_CHIP_RS400_5A41: + case PCI_CHIP_RS400_5A42: + case PCI_CHIP_RC410_5A61: + case PCI_CHIP_RC410_5A62: + screen->chip_family = CHIP_FAMILY_RS400; + fprintf(stderr, "Warning, xpress200 detected.\n"); + break; + + default: + fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", + dri_priv->deviceID); + return NULL; + } + if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && + sPriv->ddxMinor < 2) { + fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); + return NULL; + } + + if (screen->chip_family <= CHIP_FAMILY_RS200) + screen->chip_flags |= RADEON_CLASS_R100; + else if (screen->chip_family <= CHIP_FAMILY_RV280) + screen->chip_flags |= RADEON_CLASS_R200; + else + screen->chip_flags |= RADEON_CLASS_R300; + + screen->cpp = dri_priv->bpp / 8; + screen->AGPMode = dri_priv->AGPMode; + + screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16; + + if ( sPriv->drmMinor >= 10 ) { + drm_radeon_setparam_t sp; + + sp.param = RADEON_SETPARAM_FB_LOCATION; + sp.value = screen->fbLocation; + + drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, + &sp, sizeof( sp ) ); + } + + screen->frontOffset = dri_priv->frontOffset; + screen->frontPitch = dri_priv->frontPitch; + screen->backOffset = dri_priv->backOffset; + screen->backPitch = dri_priv->backPitch; + screen->depthOffset = dri_priv->depthOffset; + screen->depthPitch = dri_priv->depthPitch; + + /* Check if ddx has set up a surface reg to cover depth buffer */ + screen->depthHasSurface = ((sPriv->ddxMajor > 4) && + (screen->chip_flags & RADEON_CHIPSET_TCL)); + + if ( dri_priv->textureSize == 0 ) { + screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; + screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; + screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = + dri_priv->log2GARTTexGran; + } else { + screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset + + screen->fbLocation; + screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; + screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = + dri_priv->log2TexGran; + } + + if ( !screen->gartTextures.map || dri_priv->textureSize == 0 + || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { + screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; + screen->texOffset[RADEON_GART_TEX_HEAP] = 0; + screen->texSize[RADEON_GART_TEX_HEAP] = 0; + screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; + } else { + screen->numTexHeaps = RADEON_NR_TEX_HEAPS; + screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; + screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; + screen->logTexGranularity[RADEON_GART_TEX_HEAP] = + dri_priv->log2GARTTexGran; + } + + if ( glx_enable_extension != NULL ) { + if ( screen->irq != 0 ) { + (*glx_enable_extension)( psc, "GLX_SGI_swap_control" ); + (*glx_enable_extension)( psc, "GLX_SGI_video_sync" ); + (*glx_enable_extension)( psc, "GLX_MESA_swap_control" ); + } + + (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" ); + if (IS_R200_CLASS(screen)) + (*glx_enable_extension)( psc, "GLX_MESA_allocate_memory" ); + + (*glx_enable_extension)( psc, "GLX_MESA_copy_sub_buffer" ); + (*glx_enable_extension)( psc, "GLX_SGI_make_current_read" ); + } + +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + if (IS_R200_CLASS(screen)) { + sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA; + sPriv->psc->freeMemory = (void *) r200FreeMemoryMESA; + sPriv->psc->memoryOffset = (void *) r200GetMemoryOffsetMESA; + } +#endif + + screen->driScreen = sPriv; + screen->sarea_priv_offset = dri_priv->sarea_priv_offset; + return screen; +} + +/* Destroy the device specific screen private data struct. + */ +static void +radeonDestroyScreen( __DRIscreenPrivate *sPriv ) +{ + radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; + + if (!screen) + return; + + if ( screen->gartTextures.map ) { + drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); + } + drmUnmapBufs( screen->buffers ); + drmUnmap( screen->status.map, screen->status.size ); + drmUnmap( screen->mmio.map, screen->mmio.size ); + + /* free all option information */ + driDestroyOptionInfo (&screen->optionCache); + + FREE( screen ); + sPriv->private = NULL; +} + + +/* Initialize the driver specific screen private data. + */ +static GLboolean +radeonInitDriver( __DRIscreenPrivate *sPriv ) +{ + sPriv->private = (void *) radeonCreateScreen( sPriv ); + if ( !sPriv->private ) { + radeonDestroyScreen( sPriv ); + return GL_FALSE; + } + + return GL_TRUE; +} + + +/** + * Create the Mesa framebuffer and renderbuffers for a given window/drawable. + * + * \todo This function (and its interface) will need to be updated to support + * pbuffers. + */ +static GLboolean +radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, + __DRIdrawablePrivate *driDrawPriv, + const __GLcontextModes *mesaVis, + GLboolean isPixmap ) +{ + radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; + + if (isPixmap) { + return GL_FALSE; /* not implemented */ + } + else { + const GLboolean swDepth = GL_FALSE; + const GLboolean swAlpha = GL_FALSE; + const GLboolean swAccum = mesaVis->accumRedBits > 0; + const GLboolean swStencil = mesaVis->stencilBits > 0 && + mesaVis->depthBits != 24; + struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); + + /* front color renderbuffer */ + { + driRenderbuffer *frontRb + = driNewRenderbuffer(GL_RGBA, + driScrnPriv->pFB + screen->frontOffset, + screen->cpp, + screen->frontOffset, screen->frontPitch, + driDrawPriv); + radeonSetSpanFunctions(frontRb, mesaVis); + _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base); + } + + /* back color renderbuffer */ + if (mesaVis->doubleBufferMode) { + driRenderbuffer *backRb + = driNewRenderbuffer(GL_RGBA, + driScrnPriv->pFB + screen->backOffset, + screen->cpp, + screen->backOffset, screen->backPitch, + driDrawPriv); + radeonSetSpanFunctions(backRb, mesaVis); + _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base); + } + + /* depth renderbuffer */ + if (mesaVis->depthBits == 16) { + driRenderbuffer *depthRb + = driNewRenderbuffer(GL_DEPTH_COMPONENT16, + driScrnPriv->pFB + screen->depthOffset, + screen->cpp, + screen->depthOffset, screen->depthPitch, + driDrawPriv); + radeonSetSpanFunctions(depthRb, mesaVis); + _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); + depthRb->depthHasSurface = screen->depthHasSurface; + } + else if (mesaVis->depthBits == 24) { + driRenderbuffer *depthRb + = driNewRenderbuffer(GL_DEPTH_COMPONENT24, + driScrnPriv->pFB + screen->depthOffset, + screen->cpp, + screen->depthOffset, screen->depthPitch, + driDrawPriv); + radeonSetSpanFunctions(depthRb, mesaVis); + _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); + depthRb->depthHasSurface = screen->depthHasSurface; + } + + /* stencil renderbuffer */ + if (mesaVis->stencilBits > 0 && !swStencil) { + driRenderbuffer *stencilRb + = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT, + driScrnPriv->pFB + screen->depthOffset, + screen->cpp, + screen->depthOffset, screen->depthPitch, + driDrawPriv); + radeonSetSpanFunctions(stencilRb, mesaVis); + _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); + stencilRb->depthHasSurface = screen->depthHasSurface; + } + + _mesa_add_soft_renderbuffers(fb, + GL_FALSE, /* color */ + swDepth, + swStencil, + swAccum, + swAlpha, + GL_FALSE /* aux */); + driDrawPriv->driverPrivate = (void *) fb; + + return (driDrawPriv->driverPrivate != NULL); + } +} + + +static void +radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +{ + _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); +} + +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) +/** + * Choose the appropriate CreateContext function based on the chipset. + * Eventually, all drivers will go through this process. + */ +static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, + __DRIcontextPrivate * driContextPriv, + void *sharedContextPriv) +{ + __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); + + if (IS_R300_CLASS(screen)) + return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); + return GL_FALSE; +} + +/** + * Choose the appropriate DestroyContext function based on the chipset. + */ +static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) +{ + radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; + + if (IS_R300_CLASS(radeon->radeonScreen)) + return r300DestroyContext(driContextPriv); +} + + +#endif + +#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) +static struct __DriverAPIRec radeonAPI = { + .InitDriver = radeonInitDriver, + .DestroyScreen = radeonDestroyScreen, + .CreateContext = radeonCreateContext, + .DestroyContext = radeonDestroyContext, + .CreateBuffer = radeonCreateBuffer, + .DestroyBuffer = radeonDestroyBuffer, + .SwapBuffers = radeonSwapBuffers, + .MakeCurrent = radeonMakeCurrent, + .UnbindContext = radeonUnbindContext, + .GetSwapInfo = getSwapInfo, + .GetMSC = driGetMSC32, + .WaitForMSC = driWaitForMSC32, + .WaitForSBC = NULL, + .SwapBuffersMSC = NULL, + .CopySubBuffer = radeonCopySubBuffer, +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + .setTexOffset = r300SetTexOffset, +#endif +}; +#else +static const struct __DriverAPIRec r200API = { + .InitDriver = radeonInitDriver, + .DestroyScreen = radeonDestroyScreen, + .CreateContext = r200CreateContext, + .DestroyContext = r200DestroyContext, + .CreateBuffer = radeonCreateBuffer, + .DestroyBuffer = radeonDestroyBuffer, + .SwapBuffers = r200SwapBuffers, + .MakeCurrent = r200MakeCurrent, + .UnbindContext = r200UnbindContext, + .GetSwapInfo = getSwapInfo, + .GetMSC = driGetMSC32, + .WaitForMSC = driWaitForMSC32, + .WaitForSBC = NULL, + .SwapBuffersMSC = NULL, + .CopySubBuffer = r200CopySubBuffer, + .setTexOffset = r200SetTexOffset +}; +#endif + +/** + * This is the bootstrap function for the driver. libGL supplies all of the + * requisite information about the system, and the driver initializes itself. + * This routine also fills in the linked list pointed to by \c driver_modes + * with the \c __GLcontextModes that the driver can support for windows or + * pbuffers. + * + * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on + * failure. + */ +PUBLIC void * +__driCreateNewScreen_20050727( __DRInativeDisplay *dpy, + int scrn, __DRIscreen *psc, + const __GLcontextModes * modes, + const __DRIversion * ddx_version, + const __DRIversion * dri_version, + const __DRIversion * drm_version, + const __DRIframebuffer * frame_buffer, + drmAddress pSAREA, int fd, + int internal_api_version, + const __DRIinterfaceMethods * interface, + __GLcontextModes ** driver_modes ) +{ + __DRIscreenPrivate *psp; +#if !RADEON_COMMON + static const char *driver_name = "Radeon"; + static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; + static const __DRIversion dri_expected = { 4, 0, 0 }; + static const __DRIversion drm_expected = { 1, 6, 0 }; +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + static const char *driver_name = "R200"; + static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; + static const __DRIversion dri_expected = { 4, 0, 0 }; + static const __DRIversion drm_expected = { 1, 6, 0 }; +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) + static const char *driver_name = "R300"; + static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; + static const __DRIversion dri_expected = { 4, 0, 0 }; + static const __DRIversion drm_expected = { 1, 24, 0 }; +#endif + + dri_interface = interface; + + if ( ! driCheckDriDdxDrmVersions3( driver_name, + dri_version, & dri_expected, + ddx_version, & ddx_expected, + drm_version, & drm_expected ) ) { + return NULL; + } +#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) + psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL, + ddx_version, dri_version, drm_version, + frame_buffer, pSAREA, fd, + internal_api_version, &radeonAPI); +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL, + ddx_version, dri_version, drm_version, + frame_buffer, pSAREA, fd, + internal_api_version, &r200API); +#endif + + if ( psp != NULL ) { + RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; + if (driver_modes) { + *driver_modes = radeonFillInModes( dri_priv->bpp, + (dri_priv->bpp == 16) ? 16 : 24, + (dri_priv->bpp == 16) ? 0 : 8, + (dri_priv->backOffset != dri_priv->depthOffset) ); + } + + /* Calling driInitExtensions here, with a NULL context pointer, + * does not actually enable the extensions. It just makes sure + * that all the dispatch offsets for all the extensions that + * *might* be enables are known. This is needed because the + * dispatch offsets need to be known when _mesa_context_create + * is called, but we can't enable the extensions until we have a + * context pointer. + * + * Hello chicken. Hello egg. How are you two today? + */ + driInitExtensions( NULL, card_extensions, GL_FALSE ); +#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + driInitExtensions( NULL, blend_extensions, GL_FALSE ); + driInitSingleExtension( NULL, ARB_vp_extension ); + driInitSingleExtension( NULL, NV_vp_extension ); + driInitSingleExtension( NULL, ATI_fs_extension ); + driInitExtensions( NULL, point_extensions, GL_FALSE ); +#endif + } + + return (void *) psp; +} + + +/** + * Get information about previous buffer swaps. + */ +static int +getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) +{ +#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) + radeonContextPtr rmesa; +#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) + r200ContextPtr rmesa; +#endif + + if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) + || (dPriv->driContextPriv->driverPrivate == NULL) + || (sInfo == NULL) ) { + return -1; + } + + rmesa = dPriv->driContextPriv->driverPrivate; + sInfo->swap_count = rmesa->swap_count; + sInfo->swap_ust = rmesa->swap_ust; + sInfo->swap_missed_count = rmesa->swap_missed_count; + + sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) + ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) + : 0.0; + + return 0; +} diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_screen.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_screen.h new file mode 100644 index 00000000000..25e6fcf399a --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_screen.h @@ -0,0 +1,115 @@ +/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.h,v 1.5 2002/12/16 16:18:58 dawes Exp $ */ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and + VA Linux Systems Inc., Fremont, California. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin + * Gareth Hughes + */ + +#ifndef __RADEON_SCREEN_H__ +#define __RADEON_SCREEN_H__ + +/* + * IMPORTS: these headers contain all the DRI, X and kernel-related + * definitions that we need. + */ +#include "dri_util.h" +#include "radeon_dri.h" +#include "radeon_chipset.h" +#include "radeon_reg.h" +#include "drm_sarea.h" +#include "xmlconfig.h" + + +typedef struct { + drm_handle_t handle; /* Handle to the DRM region */ + drmSize size; /* Size of the DRM region */ + drmAddress map; /* Mapping of the DRM region */ +} radeonRegionRec, *radeonRegionPtr; + +typedef struct { + int chip_family; + int chip_flags; + int cpp; + int card_type; + int AGPMode; + unsigned int irq; /* IRQ number (0 means none) */ + + unsigned int fbLocation; + unsigned int frontOffset; + unsigned int frontPitch; + unsigned int backOffset; + unsigned int backPitch; + + unsigned int depthOffset; + unsigned int depthPitch; + + /* Shared texture data */ + int numTexHeaps; + int texOffset[RADEON_NR_TEX_HEAPS]; + int texSize[RADEON_NR_TEX_HEAPS]; + int logTexGranularity[RADEON_NR_TEX_HEAPS]; + + radeonRegionRec mmio; + radeonRegionRec status; + radeonRegionRec gartTextures; + + drmBufMapPtr buffers; + + __volatile__ u_int32_t *scratch; + + __DRIscreenPrivate *driScreen; + unsigned int sarea_priv_offset; + unsigned int gart_buffer_offset; /* offset in card memory space */ + unsigned int gart_texture_offset; /* offset in card memory space */ + unsigned int gart_base; + + GLboolean drmSupportsCubeMapsR200; /* need radeon kernel module >= 1.7 */ + GLboolean drmSupportsBlendColor; /* need radeon kernel module >= 1.11 */ + GLboolean drmSupportsTriPerf; /* need radeon kernel module >= 1.16 */ + GLboolean drmSupportsFragShader; /* need radeon kernel module >= 1.18 */ + GLboolean drmSupportsPointSprites; /* need radeon kernel module >= 1.13 */ + GLboolean drmSupportsCubeMapsR100; /* need radeon kernel module >= 1.15 */ + GLboolean drmSupportsVertexProgram; /* need radeon kernel module >= 1.25 */ + GLboolean depthHasSurface; + + /* Configuration cache with default values for all contexts */ + driOptionCache optionCache; +} radeonScreenRec, *radeonScreenPtr; + +#define IS_R100_CLASS(screen) \ + ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R100) +#define IS_R200_CLASS(screen) \ + ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R200) +#define IS_R300_CLASS(screen) \ + ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R300) + +#endif /* __RADEON_SCREEN_H__ */ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_span.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_span.h new file mode 100644 index 00000000000..9abe0864b17 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/radeon_span.h @@ -0,0 +1,50 @@ +/************************************************************************** + +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and + VA Linux Systems Inc., Fremont, California. +Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + +The Weather Channel (TM) funded Tungsten Graphics to develop the +initial release of the Radeon 8500 driver under the XFree86 license. +This notice must be preserved. + +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Gareth Hughes + * Keith Whitwell + * Kevin E. Martin + */ + +#ifndef __RADEON_SPAN_H__ +#define __RADEON_SPAN_H__ + +#include "drirenderbuffer.h" + +extern void radeonInitSpanFuncs(GLcontext * ctx); +extern void radeonSetSpanFunctions(driRenderbuffer * rb, const GLvisual * vis); + +#endif diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon.h new file mode 100644 index 00000000000..6f6c2e6d257 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon.h @@ -0,0 +1,209 @@ +/** + * \file server/radeon.h + * \brief Radeon 2D driver data structures. + */ + +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.29 2002/10/12 01:38:07 martin Exp $ */ + +#ifndef _RADEON_H_ +#define _RADEON_H_ + +#include "xf86drm.h" /* drm_handle_t, etc */ + +# define RADEON_AGP_1X_MODE 0x01 +# define RADEON_AGP_2X_MODE 0x02 +# define RADEON_AGP_4X_MODE 0x04 +# define RADEON_AGP_FW_MODE 0x10 +# define RADEON_AGP_MODE_MASK 0x17 +#define RADEON_CP_CSQ_CNTL 0x0740 +# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) +# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) +# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) +# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) +# define RADEON_CSQ_PRIBM_INDBM (4 << 28) +# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) + +#define RADEON_PCIGART_TABLE_SIZE 32768 + +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_RV250_Id 0x4964 +#define PCI_CHIP_RV250_Ie 0x4965 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Le 0x4C65 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QN 0x514E +#define PCI_CHIP_R200_QO 0x514F +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RADEON_QY 0x5159 +#define PCI_CHIP_RADEON_QZ 0x515A +#define PCI_CHIP_R200_Ql 0x516C +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV280_Y_ 0x5960 +#define PCI_CHIP_RV280_Ya 0x5961 +#define PCI_CHIP_RV280_Yb 0x5962 +#define PCI_CHIP_RV280_Yc 0x5963 + +/** + * \brief Chip families. + */ +typedef enum { + CHIP_FAMILY_UNKNOW, + CHIP_FAMILY_LEGACY, + CHIP_FAMILY_R128, + CHIP_FAMILY_M3, + CHIP_FAMILY_RADEON, + CHIP_FAMILY_VE, + CHIP_FAMILY_M6, + CHIP_FAMILY_RV200, + CHIP_FAMILY_M7, + CHIP_FAMILY_R200, + CHIP_FAMILY_RV250, + CHIP_FAMILY_M9, + CHIP_FAMILY_RV280, + CHIP_FAMILY_R300, + CHIP_FAMILY_R350, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ + CHIP_FAMILY_R420, /* R420/R423/M18 */ +} RADEONChipFamily; + + +typedef unsigned long memType; + + +/** + * \brief Radeon DDX driver private data. + */ +typedef struct { + int Chipset; /**< \brief Chipset number */ + RADEONChipFamily ChipFamily; /**< \brief Chip family */ + + unsigned long LinearAddr; /**< \brief Frame buffer physical address */ + + + drmSize registerSize; /**< \brief MMIO register map size */ + drm_handle_t registerHandle; /**< \brief MMIO register map handle */ + + int IsPCI; /* Current card is a PCI card */ + + /** + * \name AGP + */ + /*@{*/ + drmSize gartSize; /**< \brief AGP map size */ + drm_handle_t gartMemHandle; /**< \brief AGP map handle */ + unsigned long gartOffset; /**< \brief AGP offset */ + int gartMode; /**< \brief AGP mode */ + int gartFastWrite; + /*@}*/ + + /** + * \name CP ring buffer data + */ + /*@{*/ + unsigned long ringStart; /**< \brief Offset into AGP space */ + drm_handle_t ringHandle; /**< \brief Handle from drmAddMap() */ + drmSize ringMapSize; /**< \brief Size of map */ + int ringSize; /**< \brief Size of ring (in MB) */ + + unsigned long ringReadOffset; /**< \brief Read offset into AGP space */ + drm_handle_t ringReadPtrHandle;/**< \brief Handle from drmAddMap() */ + drmSize ringReadMapSize; /**< \brief Size of map */ + /*@}*/ + + /** + * \name CP vertex/indirect buffer data + */ + /*@{*/ + unsigned long bufStart; /**< \brief Offset into AGP space */ + drm_handle_t bufHandle; /**< \brief Handle from drmAddMap() */ + drmSize bufMapSize; /**< \brief Size of map */ + int bufSize; /**< \brief Size of buffers (in MB) */ + int bufNumBufs; /**< \brief Number of buffers */ + /*@}*/ + + /** + * \name CP AGP Texture data + */ + /*@{*/ + unsigned long gartTexStart; /**< \brief Offset into AGP space */ + drm_handle_t gartTexHandle; /**< \brief Handle from drmAddMap() */ + drmSize gartTexMapSize; /**< \brief Size of map */ + int gartTexSize; /**< \brief Size of AGP tex space (in MB) */ + int log2GARTTexGran; + /*@}*/ + + int drmMinor; /**< \brief DRM device minor number */ + + int frontOffset; /**< \brief Front color buffer offset */ + int frontPitch; /**< \brief Front color buffer pitch */ + int backOffset; /**< \brief Back color buffer offset */ + int backPitch; /**< \brief Back color buffer pitch */ + int depthOffset; /**< \brief Depth buffer offset */ + int depthPitch; /**< \brief Depth buffer pitch */ + int textureOffset; /**< \brief Texture area offset */ + int textureSize; /**< \brief Texture area size */ + int log2TexGran; /**< \brief Texture granularity in base 2 log */ + + unsigned int frontPitchOffset; + unsigned int backPitchOffset; + unsigned int depthPitchOffset; + + int colorTiling; /**< \brief Enable color tiling */ + + int irq; /**< \brief IRQ number */ + int page_flip_enable; /**< \brief Page Flip enable */ + unsigned int gen_int_cntl; + unsigned int crtc_offset_cntl; + + unsigned long pcieGartTableOffset; +} RADEONInfoRec, *RADEONInfoPtr; + + +#endif /* _RADEON_H_ */ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_dri.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_dri.c new file mode 100644 index 00000000000..7ead588dac8 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_dri.c @@ -0,0 +1,1337 @@ +/** + * \file server/radeon_dri.c + * \brief File to perform the device-specific initialization tasks typically + * done in the X server. + * + * Here they are converted to run in the client (or perhaps a standalone + * process), and to work with the frame buffer device rather than the X + * server infrastructure. + */ + +#include +#include +#include +#include +#include + +#include "driver.h" +#include "drm.h" +#include "memops.h" + +#include "radeon.h" +#include "radeon_dri.h" +#include "radeon_macros.h" +#include "radeon_reg.h" +#include "drm_sarea.h" + +static size_t radeon_drm_page_size; + +static int RadeonSetParam(const DRIDriverContext *ctx, int param, int value) +{ + drm_radeon_setparam_t sp; + + memset(&sp, 0, sizeof(sp)); + sp.param = param; + sp.value = value; + + if (drmCommandWrite(ctx->drmFD, DRM_RADEON_SETPARAM, &sp, sizeof(sp))) { + return -1; + } + + return 0; +} + +/** + * \brief Wait for free FIFO entries. + * + * \param ctx display handle. + * \param entries number of free entries to wait. + * + * It polls the free entries from the chip until it reaches the requested value + * or a timeout (3000 tries) occurs. Aborts the program if the FIFO times out. + */ +static void RADEONWaitForFifo( const DRIDriverContext *ctx, + int entries ) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + int i; + + for (i = 0; i < 3000; i++) { + int fifo_slots = + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; + if (fifo_slots >= entries) return; + } + + /* There are recoveries possible, but I haven't seen them work + * in practice: + */ + fprintf(stderr, "FIFO timed out: %d entries, stat=0x%08x\n", + INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK, + INREG(RADEON_RBBM_STATUS)); + exit(1); +} + +/** + * \brief Read a PLL register. + * + * \param ctx display handle. + * \param addr PLL register index. + * + * \return value of the PLL register. + */ +static unsigned int RADEONINPLL( const DRIDriverContext *ctx, int addr) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + unsigned int data; + + OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); + data = INREG(RADEON_CLOCK_CNTL_DATA); + + return data; +} + +/** + * \brief Reset graphics card to known state. + * + * \param ctx display handle. + * + * Resets the values of several Radeon registers. + */ +static void RADEONEngineReset( const DRIDriverContext *ctx ) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + unsigned int clock_cntl_index; + unsigned int mclk_cntl; + unsigned int rbbm_soft_reset; + unsigned int host_path_cntl; + int i; + + OUTREGP(RADEON_RB2D_DSTCACHE_CTLSTAT, + RADEON_RB2D_DC_FLUSH_ALL, + ~RADEON_RB2D_DC_FLUSH_ALL); + for (i = 0; i < 512; i++) { + if (!(INREG(RADEON_RB2D_DSTCACHE_CTLSTAT) & RADEON_RB2D_DC_BUSY)) + break; + } + + clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); + + mclk_cntl = INPLL(ctx, RADEON_MCLK_CNTL); + OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl | + RADEON_FORCEON_MCLKA | + RADEON_FORCEON_MCLKB | + RADEON_FORCEON_YCLKA | + RADEON_FORCEON_YCLKB | + RADEON_FORCEON_MC | + RADEON_FORCEON_AIC)); + + /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some + * unexpected behaviour on some machines. Here we use + * RADEON_HOST_PATH_CNTL to reset it. + */ + host_path_cntl = INREG(RADEON_HOST_PATH_CNTL); + rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); + + OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | + RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB)); + INREG(RADEON_RBBM_SOFT_RESET); + OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & + (unsigned int) ~(RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB))); + INREG(RADEON_RBBM_SOFT_RESET); + + OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET); + INREG(RADEON_HOST_PATH_CNTL); + OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl); + + OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); + + OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); + OUTPLL(RADEON_MCLK_CNTL, mclk_cntl); +} + +/** + * \brief Restore the drawing engine. + * + * \param ctx display handle + * + * Resets the graphics card and sets initial values for several registers of + * the card's drawing engine. + * + * Turns on the radeon command processor engine (i.e., the ringbuffer). + */ +static int RADEONEngineRestore( const DRIDriverContext *ctx ) +{ + RADEONInfoPtr info = ctx->driverPrivate; + unsigned char *RADEONMMIO = ctx->MMIOAddress; + int pitch64, datatype, dp_gui_master_cntl, err; + + fprintf(stderr, "%s\n", __FUNCTION__); + + OUTREG(RADEON_RB3D_CNTL, 0); + RADEONEngineReset( ctx ); + + switch (ctx->bpp) { + case 16: datatype = 4; break; + case 32: datatype = 6; break; + default: return 0; + } + + dp_gui_master_cntl = + ((datatype << RADEON_GMC_DST_DATATYPE_SHIFT) + | RADEON_GMC_CLR_CMP_CNTL_DIS); + + pitch64 = ((ctx->shared.virtualWidth * (ctx->bpp / 8) + 0x3f)) >> 6; + + RADEONWaitForFifo(ctx, 1); + OUTREG(RADEON_DEFAULT_OFFSET, ((INREG(RADEON_DEFAULT_OFFSET) & 0xC0000000) + | (pitch64 << 22))); + + RADEONWaitForFifo(ctx, 1); + OUTREG(RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); + + RADEONWaitForFifo(ctx, 1); + OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX + | RADEON_DEFAULT_SC_BOTTOM_MAX)); + + RADEONWaitForFifo(ctx, 1); + OUTREG(RADEON_DP_GUI_MASTER_CNTL, (dp_gui_master_cntl + | RADEON_GMC_BRUSH_SOLID_COLOR + | RADEON_GMC_SRC_DATATYPE_COLOR)); + + RADEONWaitForFifo(ctx, 7); + OUTREG(RADEON_DST_LINE_START, 0); + OUTREG(RADEON_DST_LINE_END, 0); + OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); + OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0); + OUTREG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff); + OUTREG(RADEON_DP_SRC_BKGD_CLR, 0); + OUTREG(RADEON_DP_WRITE_MASK, 0xffffffff); + OUTREG(RADEON_AUX_SC_CNTL, 0); + +/* RADEONWaitForIdleMMIO(ctx); */ + usleep(100); + + + OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl); + if (info->colorTiling) + info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; + OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl); + + /* Initialize and start the CP if required */ + if ((err = drmCommandNone(ctx->drmFD, DRM_RADEON_CP_START)) != 0) { + fprintf(stderr, "%s: CP start %d\n", __FUNCTION__, err); + return 0; + } + + return 1; +} + + +/** + * \brief Shutdown the drawing engine. + * + * \param ctx display handle + * + * Turns off the command processor engine & restores the graphics card + * to a state that fbdev understands. + */ +static int RADEONEngineShutdown( const DRIDriverContext *ctx ) +{ + drm_radeon_cp_stop_t stop; + int ret, i; + + stop.flush = 1; + stop.idle = 1; + + ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop, + sizeof(drm_radeon_cp_stop_t)); + + if (ret == 0) { + return 0; + } else if (errno != EBUSY) { + return -errno; + } + + stop.flush = 0; + + i = 0; + do { + ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop, + sizeof(drm_radeon_cp_stop_t)); + } while (ret && errno == EBUSY && i++ < 10); + + if (ret == 0) { + return 0; + } else if (errno != EBUSY) { + return -errno; + } + + stop.idle = 0; + + if (drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, + &stop, sizeof(drm_radeon_cp_stop_t))) { + return -errno; + } else { + return 0; + } +} + +/** + * \brief Compute base 2 logarithm. + * + * \param val value. + * + * \return base 2 logarithm of \p val. + */ +static int RADEONMinBits(int val) +{ + int bits; + + if (!val) return 1; + for (bits = 0; val; val >>= 1, ++bits); + return bits; +} + +/** + * \brief Initialize the AGP state + * + * \param ctx display handle. + * \param info driver private data. + * + * \return one on success, or zero on failure. + * + * Acquires and enables the AGP device. Reserves memory in the AGP space for + * the ring buffer, vertex buffers and textures. Initialize the Radeon + * registers to point to that memory and add client mappings. + */ +static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + unsigned long mode; + int ret; + int s, l; + + if (drmAgpAcquire(ctx->drmFD) < 0) { + fprintf(stderr, "[gart] AGP not available\n"); + return 0; + } + + /* Modify the mode if the default mode is not appropriate for this + * particular combination of graphics card and AGP chipset. + */ + mode = drmAgpGetMode(ctx->drmFD); /* Default mode */ + + /* Disable fast write entirely - too many lockups. + */ + mode &= ~RADEON_AGP_MODE_MASK; + switch (ctx->agpmode) { + case 4: mode |= RADEON_AGP_4X_MODE; + case 2: mode |= RADEON_AGP_2X_MODE; + case 1: default: mode |= RADEON_AGP_1X_MODE; + } + + if (drmAgpEnable(ctx->drmFD, mode) < 0) { + fprintf(stderr, "[gart] AGP not enabled\n"); + drmAgpRelease(ctx->drmFD); + return 0; + } + else + fprintf(stderr, "[gart] AGP enabled at %dx\n", ctx->agpmode); + + /* Workaround for some hardware bugs */ + if (info->ChipFamily < CHIP_FAMILY_R200) + OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000); + + info->gartOffset = 0; + + if ((ret = drmAgpAlloc(ctx->drmFD, info->gartSize*1024*1024, 0, NULL, + &info->gartMemHandle)) < 0) { + fprintf(stderr, "[gart] Out of memory (%d)\n", ret); + drmAgpRelease(ctx->drmFD); + return 0; + } + fprintf(stderr, + "[gart] %d kB allocated with handle 0x%08x\n", + info->gartSize*1024, (unsigned)info->gartMemHandle); + + if (drmAgpBind(ctx->drmFD, + info->gartMemHandle, info->gartOffset) < 0) { + fprintf(stderr, "[gart] Could not bind\n"); + drmAgpFree(ctx->drmFD, info->gartMemHandle); + drmAgpRelease(ctx->drmFD); + return 0; + } + + /* Initialize the CP ring buffer data */ + info->ringStart = info->gartOffset; + info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size; + + info->ringReadOffset = info->ringStart + info->ringMapSize; + info->ringReadMapSize = radeon_drm_page_size; + + /* Reserve space for vertex/indirect buffers */ + info->bufStart = info->ringReadOffset + info->ringReadMapSize; + info->bufMapSize = info->bufSize*1024*1024; + + /* Reserve the rest for AGP textures */ + info->gartTexStart = info->bufStart + info->bufMapSize; + s = (info->gartSize*1024*1024 - info->gartTexStart); + l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + info->gartTexMapSize = (s >> l) << l; + info->log2GARTTexGran = l; + + if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize, + DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) { + fprintf(stderr, "[gart] Could not add ring mapping\n"); + return 0; + } + fprintf(stderr, "[gart] ring handle = 0x%08x\n", info->ringHandle); + + + if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize, + DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) { + fprintf(stderr, + "[gart] Could not add ring read ptr mapping\n"); + return 0; + } + + fprintf(stderr, + "[gart] ring read ptr handle = 0x%08lx\n", + info->ringReadPtrHandle); + + if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize, + DRM_AGP, 0, &info->bufHandle) < 0) { + fprintf(stderr, + "[gart] Could not add vertex/indirect buffers mapping\n"); + return 0; + } + fprintf(stderr, + "[gart] vertex/indirect buffers handle = 0x%08x\n", + info->bufHandle); + + if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize, + DRM_AGP, 0, &info->gartTexHandle) < 0) { + fprintf(stderr, + "[gart] Could not add AGP texture map mapping\n"); + return 0; + } + fprintf(stderr, + "[gart] AGP texture map handle = 0x%08lx\n", + info->gartTexHandle); + + /* Initialize Radeon's AGP registers */ + /* Ring buffer is at AGP offset 0 */ + OUTREG(RADEON_AGP_BASE, info->ringHandle); + + return 1; +} + +/* Initialize the PCI GART state. Request memory for use in PCI space, + * and initialize the Radeon registers to point to that memory. + */ +static int RADEONDRIPciInit(const DRIDriverContext *ctx, RADEONInfoPtr info) +{ + int ret; + int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL; + int s, l; + + ret = drmScatterGatherAlloc(ctx->drmFD, info->gartSize*1024*1024, + &info->gartMemHandle); + if (ret < 0) { + fprintf(stderr, "[pci] Out of memory (%d)\n", ret); + return 0; + } + fprintf(stderr, + "[pci] %d kB allocated with handle 0x%08lx\n", + info->gartSize*1024, info->gartMemHandle); + + info->gartOffset = 0; + + /* Initialize the CP ring buffer data */ + info->ringStart = info->gartOffset; + info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size; + + info->ringReadOffset = info->ringStart + info->ringMapSize; + info->ringReadMapSize = radeon_drm_page_size; + + /* Reserve space for vertex/indirect buffers */ + info->bufStart = info->ringReadOffset + info->ringReadMapSize; + info->bufMapSize = info->bufSize*1024*1024; + + /* Reserve the rest for AGP textures */ + info->gartTexStart = info->bufStart + info->bufMapSize; + s = (info->gartSize*1024*1024 - info->gartTexStart); + l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + info->gartTexMapSize = (s >> l) << l; + info->log2GARTTexGran = l; + + if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize, + DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) { + fprintf(stderr, + "[pci] Could not add ring mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] ring handle = 0x%08x\n", info->ringHandle); + + if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize, + DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) { + fprintf(stderr, + "[pci] Could not add ring read ptr mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] ring read ptr handle = 0x%08lx\n", + info->ringReadPtrHandle); + + if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize, + DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) { + fprintf(stderr, + "[pci] Could not add vertex/indirect buffers mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] vertex/indirect buffers handle = 0x%08lx\n", + info->bufHandle); + + if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize, + DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) { + fprintf(stderr, + "[pci] Could not add GART texture map mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] GART texture map handle = 0x%08x\n", + info->gartTexHandle); + + return 1; +} + + +/** + * \brief Initialize the kernel data structures and enable the CP engine. + * + * \param ctx display handle. + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * This function is a wrapper around the DRM_RADEON_CP_INIT command, passing + * all the parameters in a drm_radeon_init_t structure. + */ +static int RADEONDRIKernelInit( const DRIDriverContext *ctx, + RADEONInfoPtr info) +{ + int cpp = ctx->bpp / 8; + drm_radeon_init_t drmInfo; + int ret; + + memset(&drmInfo, 0, sizeof(drm_radeon_init_t)); + + if ( (info->ChipFamily == CHIP_FAMILY_R200) || + (info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_M9) || + (info->ChipFamily == CHIP_FAMILY_RV280) ) + drmInfo.func = RADEON_INIT_R200_CP; + else + drmInfo.func = RADEON_INIT_CP; + + /* This is the struct passed to the kernel module for its initialization */ + drmInfo.sarea_priv_offset = sizeof(drm_sarea_t); + drmInfo.is_pci = ctx->isPCI; + drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE; + drmInfo.gart_size = info->gartSize*1024*1024; + drmInfo.ring_size = info->ringSize*1024*1024; + drmInfo.usec_timeout = 1000; + drmInfo.fb_bpp = ctx->bpp; + drmInfo.depth_bpp = ctx->bpp; + drmInfo.front_offset = info->frontOffset; + drmInfo.front_pitch = info->frontPitch * cpp; + drmInfo.back_offset = info->backOffset; + drmInfo.back_pitch = info->backPitch * cpp; + drmInfo.depth_offset = info->depthOffset; + drmInfo.depth_pitch = info->depthPitch * cpp; + drmInfo.fb_offset = info->LinearAddr; + drmInfo.mmio_offset = info->registerHandle; + drmInfo.ring_offset = info->ringHandle; + drmInfo.ring_rptr_offset = info->ringReadPtrHandle; + drmInfo.buffers_offset = info->bufHandle; + drmInfo.gart_textures_offset = info->gartTexHandle; + + ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_INIT, &drmInfo, + sizeof(drm_radeon_init_t)); + + return ret >= 0; +} + + +/** + * \brief Initialize the AGP heap. + * + * \param ctx display handle. + * \param info driver private data. + * + * This function is a wrapper around the DRM_RADEON_INIT_HEAP command, passing + * all the parameters in a drm_radeon_mem_init_heap structure. + */ +static void RADEONDRIAgpHeapInit(const DRIDriverContext *ctx, + RADEONInfoPtr info) +{ + drm_radeon_mem_init_heap_t drmHeap; + + /* Start up the simple memory manager for gart space */ + drmHeap.region = RADEON_MEM_REGION_GART; + drmHeap.start = 0; + drmHeap.size = info->gartTexMapSize; + + if (drmCommandWrite(ctx->drmFD, DRM_RADEON_INIT_HEAP, + &drmHeap, sizeof(drmHeap))) { + fprintf(stderr, + "[drm] Failed to initialized gart heap manager\n"); + } else { + fprintf(stderr, + "[drm] Initialized kernel gart heap manager, %d\n", + info->gartTexMapSize); + } +} + +/** + * \brief Add a map for the vertex buffers that will be accessed by any + * DRI-based clients. + * + * \param ctx display handle. + * \param info driver private data. + * + * \return one on success, or zero on failure. + * + * Calls drmAddBufs() with the previously allocated vertex buffers. + */ +static int RADEONDRIBufInit( const DRIDriverContext *ctx, RADEONInfoPtr info ) +{ + /* Initialize vertex buffers */ + info->bufNumBufs = drmAddBufs(ctx->drmFD, + info->bufMapSize / RADEON_BUFFER_SIZE, + RADEON_BUFFER_SIZE, + ctx->isPCI ? DRM_SG_BUFFER : DRM_AGP_BUFFER, + info->bufStart); + + if (info->bufNumBufs <= 0) { + fprintf(stderr, + "[drm] Could not create vertex/indirect buffers list\n"); + return 0; + } + fprintf(stderr, + "[drm] Added %d %d byte vertex/indirect buffers\n", + info->bufNumBufs, RADEON_BUFFER_SIZE); + + return 1; +} + +/** + * \brief Install an IRQ handler. + * + * \param ctx display handle. + * \param info driver private data. + * + * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to + * IRQ-free operation on failure. + */ +static void RADEONDRIIrqInit(const DRIDriverContext *ctx, + RADEONInfoPtr info) +{ + if (!info->irq) { + info->irq = drmGetInterruptFromBusID(ctx->drmFD, + ctx->pciBus, + ctx->pciDevice, + ctx->pciFunc); + + if ((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) { + fprintf(stderr, + "[drm] failure adding irq handler, " + "there is a device already using that irq\n" + "[drm] falling back to irq-free operation\n"); + info->irq = 0; + } + } + + if (info->irq) + fprintf(stderr, + "[drm] dma control initialized, using IRQ %d\n", + info->irq); +} + +static int RADEONCheckDRMVersion( const DRIDriverContext *ctx, + RADEONInfoPtr info ) +{ + drmVersionPtr version; + + version = drmGetVersion(ctx->drmFD); + if (version) { + int req_minor, req_patch; + + /* Need 1.8.x for proper cleanup-on-client-exit behaviour. + */ + req_minor = 8; + req_patch = 0; + + if (version->version_major != 1 || + version->version_minor < req_minor || + (version->version_minor == req_minor && + version->version_patchlevel < req_patch)) { + /* Incompatible drm version */ + fprintf(stderr, + "[dri] RADEONDRIScreenInit failed because of a version " + "mismatch.\n" + "[dri] radeon.o kernel module version is %d.%d.%d " + "but version 1.%d.%d or newer is needed.\n" + "[dri] Disabling DRI.\n", + version->version_major, + version->version_minor, + version->version_patchlevel, + req_minor, + req_patch); + drmFreeVersion(version); + return 0; + } + + info->drmMinor = version->version_minor; + drmFreeVersion(version); + } + + return 1; +} + +static int RADEONMemoryInit( const DRIDriverContext *ctx, RADEONInfoPtr info ) +{ + int width_bytes = ctx->shared.virtualWidth * ctx->cpp; + int cpp = ctx->cpp; + int bufferSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); + int depthSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); + int l; + + info->frontOffset = 0; + info->frontPitch = ctx->shared.virtualWidth; + + fprintf(stderr, + "Using %d MB AGP aperture\n", info->gartSize); + fprintf(stderr, + "Using %d MB for the ring buffer\n", info->ringSize); + fprintf(stderr, + "Using %d MB for vertex/indirect buffers\n", info->bufSize); + fprintf(stderr, + "Using %d MB for AGP textures\n", info->gartTexSize); + + /* Front, back and depth buffers - everything else texture?? + */ + info->textureSize = ctx->shared.fbSize - 2 * bufferSize - depthSize; + + if (ctx->colorTiling==1) + { + info->textureSize = ctx->shared.fbSize - ((ctx->shared.fbSize - info->textureSize + width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes*16); + } + + if (info->textureSize < 0) + return 0; + + l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + + /* Round the texture size up to the nearest whole number of + * texture regions. Again, be greedy about this, don't + * round down. + */ + info->log2TexGran = l; + info->textureSize = (info->textureSize >> l) << l; + + /* Set a minimum usable local texture heap size. This will fit + * two 256x256x32bpp textures. + */ + if (info->textureSize < 512 * 1024) { + info->textureOffset = 0; + info->textureSize = 0; + } + + /* Reserve space for textures */ + if (ctx->colorTiling==1) + { + info->textureOffset = ((ctx->shared.fbSize - info->textureSize) / + (width_bytes * 16)) * (width_bytes*16); + } + else + { + info->textureOffset = ((ctx->shared.fbSize - info->textureSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + } + /* Reserve space for the shared depth + * buffer. + */ + info->depthOffset = ((info->textureOffset - depthSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + info->depthPitch = ctx->shared.virtualWidth; + + info->backOffset = ((info->depthOffset - bufferSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + info->backPitch = ctx->shared.virtualWidth; + + + fprintf(stderr, + "Will use back buffer at offset 0x%x\n", + info->backOffset); + fprintf(stderr, + "Will use depth buffer at offset 0x%x\n", + info->depthOffset); + fprintf(stderr, + "Will use %d kb for textures at offset 0x%x\n", + info->textureSize/1024, info->textureOffset); + + info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) | + (info->frontOffset >> 10)); + + info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) | + (info->backOffset >> 10)); + + info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) | + (info->depthOffset >> 10)); + + return 1; +} + +static int RADEONColorTilingInit( const DRIDriverContext *ctx, RADEONInfoPtr info ) +{ + int width_bytes = ctx->shared.virtualWidth * ctx->cpp; + int bufferSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + RADEON_BUFFER_ALIGN) + & ~RADEON_BUFFER_ALIGN); + /* Setup color tiling */ + if (info->drmMinor<14) + info->colorTiling=0; + + if (info->colorTiling) + { + + int colorTilingFlag; + drm_radeon_surface_alloc_t front,back; + + RadeonSetParam(ctx, RADEON_SETPARAM_SWITCH_TILING, info->colorTiling ? 1 : 0); + + /* Setup the surfaces */ + if (info->ChipFamily < CHIP_FAMILY_R200) + colorTilingFlag=RADEON_SURF_TILE_COLOR_MACRO; + else + colorTilingFlag=R200_SURF_TILE_COLOR_MACRO; + + front.address = info->frontOffset; + front.size = bufferSize; + front.flags = (width_bytes) | colorTilingFlag; + drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &front,sizeof(front)); + + back.address = info->backOffset; + back.size = bufferSize; + back.flags = (width_bytes) | colorTilingFlag; + drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &back,sizeof(back)); + + } + return 1; +} + + + +/** + * Called at the start of each server generation. + * + * \param ctx display handle. + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * Performs static frame buffer allocation. Opens the DRM device and add maps + * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more + * information. Creates a \e server context to grab the lock for the + * initialization ioctls and calls the other initilization functions in this + * file. Starts the CP engine via the DRM_RADEON_CP_START command. + * + * Setups a RADEONDRIRec structure to be passed to radeon_dri.so for its + * initialization. + */ +static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info ) +{ + RADEONDRIPtr pRADEONDRI; + int err; + + usleep(100); + /*assert(!ctx->IsClient);*/ + + { + int width_bytes = (ctx->shared.virtualWidth * ctx->cpp); + int maxy = ctx->shared.fbSize / width_bytes; + + + if (maxy <= ctx->shared.virtualHeight * 3) { + fprintf(stderr, + "Static buffer allocation failed -- " + "need at least %d kB video memory (have %d kB)\n", + (ctx->shared.virtualWidth * ctx->shared.virtualHeight * + ctx->cpp * 3 + 1023) / 1024, + ctx->shared.fbSize / 1024); + return 0; + } + } + + + if (info->ChipFamily >= CHIP_FAMILY_R300) { + fprintf(stderr, + "Direct rendering not yet supported on " + "Radeon 9700 and newer cards\n"); + return 0; + } + + radeon_drm_page_size = getpagesize(); + + info->registerSize = ctx->MMIOSize; + ctx->shared.SAREASize = SAREA_MAX; + + /* Note that drmOpen will try to load the kernel module, if needed. */ + ctx->drmFD = drmOpen("radeon", NULL ); + if (ctx->drmFD < 0) { + fprintf(stderr, "[drm] drmOpen failed\n"); + return 0; + } + + if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) { + fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n", + ctx->drmFD, ctx->pciBusID, strerror(-err)); + return 0; + } + + if (drmAddMap( ctx->drmFD, + 0, + ctx->shared.SAREASize, + DRM_SHM, + DRM_CONTAINS_LOCK, + &ctx->shared.hSAREA) < 0) + { + fprintf(stderr, "[drm] drmAddMap failed\n"); + return 0; + } + fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n", + ctx->shared.SAREASize, ctx->shared.hSAREA); + + if (drmMap( ctx->drmFD, + ctx->shared.hSAREA, + ctx->shared.SAREASize, + (drmAddressPtr)(&ctx->pSAREA)) < 0) + { + fprintf(stderr, "[drm] drmMap failed\n"); + return 0; + } + memset(ctx->pSAREA, 0, ctx->shared.SAREASize); + fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n", + ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize); + + /* Need to AddMap the framebuffer and mmio regions here: + */ + if (drmAddMap( ctx->drmFD, + (drm_handle_t)ctx->FBStart, + ctx->FBSize, + DRM_FRAME_BUFFER, +#ifndef _EMBEDDED + 0, +#else + DRM_READ_ONLY, +#endif + &ctx->shared.hFrameBuffer) < 0) + { + fprintf(stderr, "[drm] drmAddMap framebuffer failed\n"); + return 0; + } + + fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n", + ctx->shared.hFrameBuffer); + + + + if (drmAddMap(ctx->drmFD, + ctx->MMIOStart, + ctx->MMIOSize, + DRM_REGISTERS, + DRM_READ_ONLY, + &info->registerHandle) < 0) { + fprintf(stderr, "[drm] drmAddMap mmio failed\n"); + return 0; + } + fprintf(stderr, + "[drm] register handle = 0x%08lx\n", info->registerHandle); + + /* Check the radeon DRM version */ + if (!RADEONCheckDRMVersion(ctx, info)) { + return 0; + } + + if (ctx->isPCI) { + /* Initialize PCI */ + if (!RADEONDRIPciInit(ctx, info)) + return 0; + } + else { + /* Initialize AGP */ + if (!RADEONDRIAgpInit(ctx, info)) + return 0; + } + + /* Memory manager setup */ + if (!RADEONMemoryInit(ctx, info)) { + return 0; + } + + /* Create a 'server' context so we can grab the lock for + * initialization ioctls. + */ + if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) { + fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err); + return 0; + } + + DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); + + /* Initialize the kernel data structures */ + if (!RADEONDRIKernelInit(ctx, info)) { + fprintf(stderr, "RADEONDRIKernelInit failed\n"); + DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext); + return 0; + } + + /* Initialize the vertex buffers list */ + if (!RADEONDRIBufInit(ctx, info)) { + fprintf(stderr, "RADEONDRIBufInit failed\n"); + DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext); + return 0; + } + + RADEONColorTilingInit(ctx, info); + + /* Initialize IRQ */ + RADEONDRIIrqInit(ctx, info); + + /* Initialize kernel gart memory manager */ + RADEONDRIAgpHeapInit(ctx, info); + + fprintf(stderr,"color tiling %sabled\n", info->colorTiling?"en":"dis"); + fprintf(stderr,"page flipping %sabled\n", info->page_flip_enable?"en":"dis"); + /* Initialize the SAREA private data structure */ + { + drm_radeon_sarea_t *pSAREAPriv; + pSAREAPriv = (drm_radeon_sarea_t *)(((char*)ctx->pSAREA) + + sizeof(drm_sarea_t)); + memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); + pSAREAPriv->pfState = info->page_flip_enable; + } + + + /* Quick hack to clear the front & back buffers. Could also use + * the clear ioctl to do this, but would need to setup hw state + * first. + */ + drimemsetio((char *)ctx->FBAddress + info->frontOffset, + 0, + info->frontPitch * ctx->cpp * ctx->shared.virtualHeight ); + + drimemsetio((char *)ctx->FBAddress + info->backOffset, + 0, + info->backPitch * ctx->cpp * ctx->shared.virtualHeight ); + + /* This is the struct passed to radeon_dri.so for its initialization */ + ctx->driverClientMsg = malloc(sizeof(RADEONDRIRec)); + ctx->driverClientMsgSize = sizeof(RADEONDRIRec); + pRADEONDRI = (RADEONDRIPtr)ctx->driverClientMsg; + pRADEONDRI->deviceID = info->Chipset; + pRADEONDRI->width = ctx->shared.virtualWidth; + pRADEONDRI->height = ctx->shared.virtualHeight; + pRADEONDRI->depth = ctx->bpp; /* XXX: depth */ + pRADEONDRI->bpp = ctx->bpp; + pRADEONDRI->IsPCI = ctx->isPCI; + pRADEONDRI->AGPMode = ctx->agpmode; + pRADEONDRI->frontOffset = info->frontOffset; + pRADEONDRI->frontPitch = info->frontPitch; + pRADEONDRI->backOffset = info->backOffset; + pRADEONDRI->backPitch = info->backPitch; + pRADEONDRI->depthOffset = info->depthOffset; + pRADEONDRI->depthPitch = info->depthPitch; + pRADEONDRI->textureOffset = info->textureOffset; + pRADEONDRI->textureSize = info->textureSize; + pRADEONDRI->log2TexGran = info->log2TexGran; + pRADEONDRI->registerHandle = info->registerHandle; + pRADEONDRI->registerSize = info->registerSize; + pRADEONDRI->statusHandle = info->ringReadPtrHandle; + pRADEONDRI->statusSize = info->ringReadMapSize; + pRADEONDRI->gartTexHandle = info->gartTexHandle; + pRADEONDRI->gartTexMapSize = info->gartTexMapSize; + pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran; + pRADEONDRI->gartTexOffset = info->gartTexStart; + pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t); + + /* Don't release the lock now - let the VT switch handler do it. */ + + return 1; +} + + +/** + * \brief Get Radeon chip family from chipset number. + * + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * Called by radeonInitFBDev() to set RADEONInfoRec::ChipFamily + * according to the value of RADEONInfoRec::Chipset. Fails if the + * chipset is unrecognized or not appropriate for this driver (i.e., not + * an r100 style radeon) + */ +static int get_chipfamily_from_chipset( RADEONInfoPtr info ) +{ + switch (info->Chipset) { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + info->ChipFamily = CHIP_FAMILY_M6; + break; + + case PCI_CHIP_RADEON_QY: + case PCI_CHIP_RADEON_QZ: + info->ChipFamily = CHIP_FAMILY_VE; + break; + + case PCI_CHIP_R200_QL: + case PCI_CHIP_R200_QN: + case PCI_CHIP_R200_QO: + case PCI_CHIP_R200_Ql: + case PCI_CHIP_R200_BB: + info->ChipFamily = CHIP_FAMILY_R200; + break; + + case PCI_CHIP_RV200_QW: /* RV200 desktop */ + case PCI_CHIP_RV200_QX: + info->ChipFamily = CHIP_FAMILY_RV200; + break; + + case PCI_CHIP_RADEON_LW: + case PCI_CHIP_RADEON_LX: + info->ChipFamily = CHIP_FAMILY_M7; + break; + + case PCI_CHIP_RV250_Id: + case PCI_CHIP_RV250_Ie: + case PCI_CHIP_RV250_If: + case PCI_CHIP_RV250_Ig: + info->ChipFamily = CHIP_FAMILY_RV250; + break; + + case PCI_CHIP_RV250_Ld: + case PCI_CHIP_RV250_Le: + case PCI_CHIP_RV250_Lf: + case PCI_CHIP_RV250_Lg: + info->ChipFamily = CHIP_FAMILY_M9; + break; + + case PCI_CHIP_RV280_Y_: + case PCI_CHIP_RV280_Ya: + case PCI_CHIP_RV280_Yb: + case PCI_CHIP_RV280_Yc: + info->ChipFamily = CHIP_FAMILY_RV280; + break; + + case PCI_CHIP_R300_ND: + case PCI_CHIP_R300_NE: + case PCI_CHIP_R300_NF: + case PCI_CHIP_R300_NG: + info->ChipFamily = CHIP_FAMILY_R300; + break; + + default: + /* Original Radeon/7200 */ + info->ChipFamily = CHIP_FAMILY_RADEON; + } + + return 1; +} + + +/** + * \brief Validate the fbdev mode. + * + * \param ctx display handle. + * + * \return one on success, or zero on failure. + * + * Saves some registers and returns 1. + * + * \sa radeonValidateMode(). + */ +static int radeonValidateMode( const DRIDriverContext *ctx ) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + RADEONInfoPtr info = ctx->driverPrivate; + + info->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL); + info->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); + + if (info->colorTiling) + info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; + return 1; +} + + +/** + * \brief Examine mode returned by fbdev. + * + * \param ctx display handle. + * + * \return one on success, or zero on failure. + * + * Restores registers that fbdev has clobbered and returns 1. + * + * \sa radeonValidateMode(). + */ +static int radeonPostValidateMode( const DRIDriverContext *ctx ) +{ + unsigned char *RADEONMMIO = ctx->MMIOAddress; + RADEONInfoPtr info = ctx->driverPrivate; + + RADEONColorTilingInit( ctx, info); + OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl); + if (info->colorTiling) + info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; + OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl); + + return 1; +} + + +/** + * \brief Initialize the framebuffer device mode + * + * \param ctx display handle. + * + * \return one on success, or zero on failure. + * + * Fills in \p info with some default values and some information from \p ctx + * and then calls RADEONScreenInit() for the screen initialization. + * + * Before exiting clears the framebuffer memory accessing it directly. + */ +static int radeonInitFBDev( DRIDriverContext *ctx ) +{ + RADEONInfoPtr info = calloc(1, sizeof(*info)); + + { + int dummy = ctx->shared.virtualWidth; + + if (ctx->colorTiling==1) + { + switch (ctx->bpp / 8) { + case 1: dummy = (ctx->shared.virtualWidth + 255) & ~255; break; + case 2: dummy = (ctx->shared.virtualWidth + 127) & ~127; break; + case 3: + case 4: dummy = (ctx->shared.virtualWidth + 63) & ~63; break; + } + } else { + switch (ctx->bpp / 8) { + case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break; + case 2: dummy = (ctx->shared.virtualWidth + 31) & ~31; break; + case 3: + case 4: dummy = (ctx->shared.virtualWidth + 15) & ~15; break; + } + } + + ctx->shared.virtualWidth = dummy; + ctx->shared.Width = dummy; + } + + fprintf(stderr,"shared virtual width is %d\n", ctx->shared.virtualWidth); + ctx->driverPrivate = (void *)info; + + info->gartFastWrite = RADEON_DEFAULT_AGP_FAST_WRITE; + info->gartSize = RADEON_DEFAULT_AGP_SIZE; + info->gartTexSize = RADEON_DEFAULT_AGP_TEX_SIZE; + info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; + info->ringSize = RADEON_DEFAULT_RING_SIZE; + info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP; + info->colorTiling = ctx->colorTiling; + + info->Chipset = ctx->chipset; + + if (!get_chipfamily_from_chipset( info )) { + fprintf(stderr, "Unknown or non-radeon chipset -- cannot continue\n"); + fprintf(stderr, "==> Verify PCI BusID is correct in miniglx.conf\n"); + return 0; + } + + info->frontPitch = ctx->shared.virtualWidth; + info->LinearAddr = ctx->FBStart & 0xfc000000; + + + if (!RADEONScreenInit( ctx, info )) + return 0; + + + return 1; +} + + +/** + * \brief The screen is being closed, so clean up any state and free any + * resources used by the DRI. + * + * \param ctx display handle. + * + * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver + * private data. + */ +static void radeonHaltFBDev( DRIDriverContext *ctx ) +{ + drmUnmap( ctx->pSAREA, ctx->shared.SAREASize ); + drmClose(ctx->drmFD); + + if (ctx->driverPrivate) { + free(ctx->driverPrivate); + ctx->driverPrivate = 0; + } +} + + +extern void radeonNotifyFocus( int ); + +/** + * \brief Exported driver interface for Mini GLX. + * + * \sa DRIDriverRec. + */ +const struct DRIDriverRec __driDriver = { + radeonValidateMode, + radeonPostValidateMode, + radeonInitFBDev, + radeonHaltFBDev, + RADEONEngineShutdown, + RADEONEngineRestore, +#ifndef _EMBEDDED + 0, +#else + radeonNotifyFocus, +#endif +}; diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_dri.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_dri.h new file mode 100644 index 00000000000..ecd53233394 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_dri.h @@ -0,0 +1,116 @@ +/** + * \file server/radeon_dri.h + * \brief Radeon server-side structures. + * + * \author Kevin E. Martin + * \author Rickard E. Faith + */ + +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h,v 1.3 2002/04/24 16:20:40 martin Exp $ */ + +#ifndef _RADEON_DRI_ +#define _RADEON_DRI_ + +#include "xf86drm.h" +#include "drm.h" +#include "radeon_drm.h" + +/* DRI Driver defaults */ +#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO +#define RADEON_DEFAULT_CP_BM_MODE RADEON_CSQ_PRIBM_INDBM +#define RADEON_DEFAULT_AGP_MODE 1 +#define RADEON_DEFAULT_AGP_FAST_WRITE 0 +#define RADEON_DEFAULT_AGP_SIZE 8 /* MB (must be 2^n and > 4MB) */ +#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */ +#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */ +#define RADEON_DEFAULT_AGP_TEX_SIZE 1 /* MB (must be page aligned) */ +#define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */ +#define RADEON_DEFAULT_PAGE_FLIP 0 /* page flipping diabled */ +#define RADEON_BUFFER_ALIGN 0x00000fff + +/** + * \brief Radeon DRI driver private data. + */ +typedef struct { + /** + * \name DRI screen private data + */ + /*@{*/ + int deviceID; /**< \brief PCI device ID */ + int width; /**< \brief width in pixels of display */ + int height; /**< \brief height in scanlines of display */ + int depth; /**< \brief depth of display (8, 15, 16, 24) */ + int bpp; /**< \brief bit depth of display (8, 16, 24, 32) */ + + int IsPCI; /**< \brief is current card a PCI card? */ + int AGPMode; /**< \brief AGP mode */ + + int frontOffset; /**< \brief front buffer offset */ + int frontPitch; /**< \brief front buffer pitch */ + int backOffset; /**< \brief shared back buffer offset */ + int backPitch; /**< \brief shared back buffer pitch */ + int depthOffset; /**< \brief shared depth buffer offset */ + int depthPitch; /**< \brief shared depth buffer pitch */ + int textureOffset; /**< \brief start of texture data in frame buffer */ + int textureSize; /**< \brief size of texture date */ + int log2TexGran; /**< \brief log2 texture granularity */ + /*@}*/ + + /** + * \name MMIO register data + */ + /*@{*/ + drm_handle_t registerHandle; /**< \brief MMIO register map size */ + drmSize registerSize; /**< \brief MMIO register map handle */ + /*@}*/ + + /** + * \name CP in-memory status information + */ + /*@{*/ + drm_handle_t statusHandle; /**< \brief status map handle */ + drmSize statusSize; /**< \brief status map size */ + /*@}*/ + + /** + * \name CP AGP Texture data + */ + /*@{*/ + drm_handle_t gartTexHandle; /**< \brief AGP texture area map handle */ + drmSize gartTexMapSize; /**< \brief AGP texture area map size */ + int log2GARTTexGran; /**< \brief AGP texture granularity in log base 2 */ + int gartTexOffset; /**< \brief AGP texture area offset in AGP space */ + /*@}*/ + + unsigned int sarea_priv_offset; /**< \brief offset of the private SAREA data*/ +} RADEONDRIRec, *RADEONDRIPtr; + +#endif diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_egl.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_egl.c new file mode 100644 index 00000000000..2f6ea559032 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_egl.c @@ -0,0 +1,1088 @@ +/* + * EGL driver for radeon_dri.so + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "eglconfig.h" +#include "eglcontext.h" +#include "egldisplay.h" +#include "egldriver.h" +#include "eglglobals.h" +#include "egllog.h" +#include "eglmode.h" +#include "eglscreen.h" +#include "eglsurface.h" +#include "egldri.h" + +#include "mtypes.h" +#include "memops.h" +#include "drm.h" +#include "drm_sarea.h" +#include "radeon_drm.h" +#include "radeon_dri.h" +#include "radeon.h" + +static size_t radeon_drm_page_size; + +/** + * radeon driver-specific driver class derived from _EGLDriver + */ +typedef struct radeon_driver +{ + _EGLDriver Base; /* base class/object */ + GLuint radeonStuff; +} radeonDriver; + +static int +RADEONSetParam(driDisplay *disp, int param, int value) +{ + drm_radeon_setparam_t sp; + int ret; + + memset(&sp, 0, sizeof(sp)); + sp.param = param; + sp.value = value; + + if ((ret=drmCommandWrite(disp->drmFD, DRM_RADEON_SETPARAM, &sp, sizeof(sp)))) { + fprintf(stderr,"Set param failed\n", ret); + return -1; + } + + return 0; +} + +static int +RADEONCheckDRMVersion(driDisplay *disp, RADEONInfoPtr info) +{ + drmVersionPtr version; + + version = drmGetVersion(disp->drmFD); + if (version) { + int req_minor, req_patch; + + /* Need 1.21.x for card type detection getparam + */ + req_minor = 21; + req_patch = 0; + + if (version->version_major != 1 || + version->version_minor < req_minor || + (version->version_minor == req_minor && + version->version_patchlevel < req_patch)) { + /* Incompatible drm version */ + fprintf(stderr, + "[dri] RADEONDRIScreenInit failed because of a version " + "mismatch.\n" + "[dri] radeon.o kernel module version is %d.%d.%d " + "but version 1.%d.%d or newer is needed.\n" + "[dri] Disabling DRI.\n", + version->version_major, + version->version_minor, + version->version_patchlevel, + req_minor, + req_patch); + drmFreeVersion(version); + return 0; + } + + info->drmMinor = version->version_minor; + drmFreeVersion(version); + } + + return 1; +} + + +/** + * \brief Compute base 2 logarithm. + * + * \param val value. + * + * \return base 2 logarithm of \p val. + */ +static int RADEONMinBits(int val) +{ + int bits; + + if (!val) return 1; + for (bits = 0; val; val >>= 1, ++bits); + return bits; +} + + +/* Initialize the PCI GART state. Request memory for use in PCI space, + * and initialize the Radeon registers to point to that memory. + */ +static int RADEONDRIPciInit(driDisplay *disp, RADEONInfoPtr info) +{ + int ret; + int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL; + int s, l; + + ret = drmScatterGatherAlloc(disp->drmFD, info->gartSize*1024*1024, + &info->gartMemHandle); + if (ret < 0) { + fprintf(stderr, "[pci] Out of memory (%d)\n", ret); + return 0; + } + fprintf(stderr, + "[pci] %d kB allocated with handle 0x%04lx\n", + info->gartSize*1024, (long) info->gartMemHandle); + + info->gartOffset = 0; + + /* Initialize the CP ring buffer data */ + info->ringStart = info->gartOffset; + info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size; + + info->ringReadOffset = info->ringStart + info->ringMapSize; + info->ringReadMapSize = radeon_drm_page_size; + + /* Reserve space for vertex/indirect buffers */ + info->bufStart = info->ringReadOffset + info->ringReadMapSize; + info->bufMapSize = info->bufSize*1024*1024; + + /* Reserve the rest for AGP textures */ + info->gartTexStart = info->bufStart + info->bufMapSize; + s = (info->gartSize*1024*1024 - info->gartTexStart); + l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + info->gartTexMapSize = (s >> l) << l; + info->log2GARTTexGran = l; + + if (drmAddMap(disp->drmFD, info->ringStart, info->ringMapSize, + DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) { + fprintf(stderr, + "[pci] Could not add ring mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] ring handle = 0x%08lx\n", info->ringHandle); + + if (drmAddMap(disp->drmFD, info->ringReadOffset, info->ringReadMapSize, + DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) { + fprintf(stderr, + "[pci] Could not add ring read ptr mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] ring read ptr handle = 0x%08lx\n", + info->ringReadPtrHandle); + + if (drmAddMap(disp->drmFD, info->bufStart, info->bufMapSize, + DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) { + fprintf(stderr, + "[pci] Could not add vertex/indirect buffers mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] vertex/indirect buffers handle = 0x%08lx\n", + info->bufHandle); + + if (drmAddMap(disp->drmFD, info->gartTexStart, info->gartTexMapSize, + DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) { + fprintf(stderr, + "[pci] Could not add GART texture map mapping\n"); + return 0; + } + fprintf(stderr, + "[pci] GART texture map handle = 0x%08lx\n", + info->gartTexHandle); + + return 1; +} + + +/** + * \brief Initialize the AGP state + * + * \param ctx display handle. + * \param info driver private data. + * + * \return one on success, or zero on failure. + * + * Acquires and enables the AGP device. Reserves memory in the AGP space for + * the ring buffer, vertex buffers and textures. Initialize the Radeon + * registers to point to that memory and add client mappings. + */ +static int RADEONDRIAgpInit( driDisplay *disp, RADEONInfoPtr info) +{ + int mode, ret; + int s, l; + int agpmode = 1; + + if (drmAgpAcquire(disp->drmFD) < 0) { + fprintf(stderr, "[gart] AGP not available\n"); + return 0; + } + + mode = drmAgpGetMode(disp->drmFD); /* Default mode */ + /* Disable fast write entirely - too many lockups. + */ + mode &= ~RADEON_AGP_MODE_MASK; + switch (agpmode) { + case 4: mode |= RADEON_AGP_4X_MODE; + case 2: mode |= RADEON_AGP_2X_MODE; + case 1: default: mode |= RADEON_AGP_1X_MODE; + } + + if (drmAgpEnable(disp->drmFD, mode) < 0) { + fprintf(stderr, "[gart] AGP not enabled\n"); + drmAgpRelease(disp->drmFD); + return 0; + } + +#if 0 + /* Workaround for some hardware bugs */ + if (info->ChipFamily < CHIP_FAMILY_R200) + OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000); +#endif + info->gartOffset = 0; + + if ((ret = drmAgpAlloc(disp->drmFD, info->gartSize*1024*1024, 0, NULL, + &info->gartMemHandle)) < 0) { + fprintf(stderr, "[gart] Out of memory (%d)\n", ret); + drmAgpRelease(disp->drmFD); + return 0; + } + fprintf(stderr, + "[gart] %d kB allocated with handle 0x%08x\n", + info->gartSize*1024, (unsigned)info->gartMemHandle); + + if (drmAgpBind(disp->drmFD, + info->gartMemHandle, info->gartOffset) < 0) { + fprintf(stderr, "[gart] Could not bind\n"); + drmAgpFree(disp->drmFD, info->gartMemHandle); + drmAgpRelease(disp->drmFD); + return 0; + } + + /* Initialize the CP ring buffer data */ + info->ringStart = info->gartOffset; + info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size; + + info->ringReadOffset = info->ringStart + info->ringMapSize; + info->ringReadMapSize = radeon_drm_page_size; + + /* Reserve space for vertex/indirect buffers */ + info->bufStart = info->ringReadOffset + info->ringReadMapSize; + info->bufMapSize = info->bufSize*1024*1024; + + /* Reserve the rest for AGP textures */ + info->gartTexStart = info->bufStart + info->bufMapSize; + s = (info->gartSize*1024*1024 - info->gartTexStart); + l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + info->gartTexMapSize = (s >> l) << l; + info->log2GARTTexGran = l; + + if (drmAddMap(disp->drmFD, info->ringStart, info->ringMapSize, + DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) { + fprintf(stderr, "[gart] Could not add ring mapping\n"); + return 0; + } + fprintf(stderr, "[gart] ring handle = 0x%08lx\n", info->ringHandle); + + + if (drmAddMap(disp->drmFD, info->ringReadOffset, info->ringReadMapSize, + DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) { + fprintf(stderr, + "[gart] Could not add ring read ptr mapping\n"); + return 0; + } + + fprintf(stderr, + "[gart] ring read ptr handle = 0x%08lx\n", + info->ringReadPtrHandle); + + if (drmAddMap(disp->drmFD, info->bufStart, info->bufMapSize, + DRM_AGP, 0, &info->bufHandle) < 0) { + fprintf(stderr, + "[gart] Could not add vertex/indirect buffers mapping\n"); + return 0; + } + fprintf(stderr, + "[gart] vertex/indirect buffers handle = 0x%08lx\n", + info->bufHandle); + + if (drmAddMap(disp->drmFD, info->gartTexStart, info->gartTexMapSize, + DRM_AGP, 0, &info->gartTexHandle) < 0) { + fprintf(stderr, + "[gart] Could not add AGP texture map mapping\n"); + return 0; + } + fprintf(stderr, + "[gart] AGP texture map handle = 0x%08lx\n", + info->gartTexHandle); + + return 1; +} + + +/** + * Initialize all the memory-related fields of the RADEONInfo object. + * This includes the various 'offset' and 'size' fields. + */ +static int +RADEONMemoryInit(driDisplay *disp, RADEONInfoPtr info) +{ + int width_bytes = disp->virtualWidth * disp->cpp; + int cpp = disp->cpp; + int bufferSize = ((disp->virtualHeight * width_bytes + + RADEON_BUFFER_ALIGN) + & ~RADEON_BUFFER_ALIGN); + int depthSize = ((((disp->virtualHeight+15) & ~15) * width_bytes + + RADEON_BUFFER_ALIGN) + & ~RADEON_BUFFER_ALIGN); + int l; + int pcie_gart_table_size = 0; + + info->frontOffset = 0; + info->frontPitch = disp->virtualWidth; + + if (disp->card_type==RADEON_CARD_PCIE) + pcie_gart_table_size = RADEON_PCIGART_TABLE_SIZE; + + /* Front, back and depth buffers - everything else texture?? + */ + info->textureSize = disp->fbSize - pcie_gart_table_size - 2 * bufferSize - depthSize; + + if (info->textureSize < 0) + return 0; + + l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS); + if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY; + + /* Round the texture size up to the nearest whole number of + * texture regions. Again, be greedy about this, don't + * round down. + */ + info->log2TexGran = l; + info->textureSize = (info->textureSize >> l) << l; + + /* Set a minimum usable local texture heap size. This will fit + * two 256x256x32bpp textures. + */ + if (info->textureSize < 512 * 1024) { + info->textureOffset = 0; + info->textureSize = 0; + } + + /* Reserve space for textures */ + info->textureOffset = ((disp->fbSize - pcie_gart_table_size - info->textureSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + + /* Reserve space for the shared depth + * buffer. + */ + info->depthOffset = ((info->textureOffset - depthSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + info->depthPitch = disp->virtualWidth; + + info->backOffset = ((info->depthOffset - bufferSize + + RADEON_BUFFER_ALIGN) & + ~RADEON_BUFFER_ALIGN); + info->backPitch = disp->virtualWidth; + + if (pcie_gart_table_size) + info->pcieGartTableOffset = disp->fbSize - pcie_gart_table_size; + + fprintf(stderr, + "Will use back buffer at offset 0x%x, pitch %d\n", + info->backOffset, info->backPitch); + fprintf(stderr, + "Will use depth buffer at offset 0x%x, pitch %d\n", + info->depthOffset, info->depthPitch); + fprintf(stderr, + "Will use %d kb for textures at offset 0x%x\n", + info->textureSize/1024, info->textureOffset); + if (pcie_gart_table_size) + { + fprintf(stderr, + "Will use %d kb for PCIE GART Table at offset 0x%x\n", + pcie_gart_table_size/1024, info->pcieGartTableOffset); + } + + /* XXX I don't think these are needed. */ +#if 0 + info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) | + (info->frontOffset >> 10)); + + info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) | + (info->backOffset >> 10)); + + info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) | + (info->depthOffset >> 10)); +#endif + + if (pcie_gart_table_size) + RADEONSetParam(disp, RADEON_SETPARAM_PCIGART_LOCATION, info->pcieGartTableOffset); + + return 1; +} + + +/** + * \brief Initialize the kernel data structures and enable the CP engine. + * + * \param ctx display handle. + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * This function is a wrapper around the DRM_RADEON_CP_INIT command, passing + * all the parameters in a drm_radeon_init_t structure. + */ +static int RADEONDRIKernelInit( driDisplay *disp, + RADEONInfoPtr info) +{ + int cpp = disp->bpp / 8; + drm_radeon_init_t drmInfo; + int ret; + + memset(&drmInfo, 0, sizeof(drmInfo)); + + if ( (info->ChipFamily >= CHIP_FAMILY_R300) ) + drmInfo.func = RADEON_INIT_R300_CP; + else if ( (info->ChipFamily == CHIP_FAMILY_R200) || + (info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_M9) || + (info->ChipFamily == CHIP_FAMILY_RV280) ) + drmInfo.func = RADEON_INIT_R200_CP; + else + drmInfo.func = RADEON_INIT_CP; + + /* This is the struct passed to the kernel module for its initialization */ + /* XXX problem here: + * The front/back/depth_offset/pitch fields may change depending upon + * which drawing surface we're using!!! They can't be set just once + * during initialization. + * Looks like we'll need a new ioctl to update these fields for drawing + * to other surfaces... + */ + drmInfo.sarea_priv_offset = sizeof(drm_sarea_t); + drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE; + drmInfo.gart_size = info->gartSize*1024*1024; + drmInfo.ring_size = info->ringSize*1024*1024; + drmInfo.usec_timeout = 1000; + drmInfo.fb_bpp = disp->bpp; + drmInfo.depth_bpp = disp->bpp; + drmInfo.front_offset = info->frontOffset; + drmInfo.front_pitch = info->frontPitch * cpp; + drmInfo.back_offset = info->backOffset; + drmInfo.back_pitch = info->backPitch * cpp; + drmInfo.depth_offset = info->depthOffset; + drmInfo.depth_pitch = info->depthPitch * cpp; + drmInfo.ring_offset = info->ringHandle; + drmInfo.ring_rptr_offset = info->ringReadPtrHandle; + drmInfo.buffers_offset = info->bufHandle; + drmInfo.gart_textures_offset = info->gartTexHandle; + + ret = drmCommandWrite(disp->drmFD, DRM_RADEON_CP_INIT, &drmInfo, + sizeof(drm_radeon_init_t)); + + return ret >= 0; +} + + +/** + * \brief Add a map for the vertex buffers that will be accessed by any + * DRI-based clients. + * + * \param ctx display handle. + * \param info driver private data. + * + * \return one on success, or zero on failure. + * + * Calls drmAddBufs() with the previously allocated vertex buffers. + */ +static int RADEONDRIBufInit( driDisplay *disp, RADEONInfoPtr info ) +{ + /* Initialize vertex buffers */ + info->bufNumBufs = drmAddBufs(disp->drmFD, + info->bufMapSize / RADEON_BUFFER_SIZE, + RADEON_BUFFER_SIZE, + (disp->card_type!=RADEON_CARD_AGP) ? DRM_SG_BUFFER : DRM_AGP_BUFFER, + info->bufStart); + + if (info->bufNumBufs <= 0) { + fprintf(stderr, + "[drm] Could not create vertex/indirect buffers list\n"); + return 0; + } + fprintf(stderr, + "[drm] Added %d %d byte vertex/indirect buffers\n", + info->bufNumBufs, RADEON_BUFFER_SIZE); + + return 1; +} + + +/** + * \brief Install an IRQ handler. + * + * \param disp display handle. + * \param info driver private data. + * + * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to + * IRQ-free operation on failure. + */ +static void RADEONDRIIrqInit(driDisplay *disp, RADEONInfoPtr info) +{ + if ((drmCtlInstHandler(disp->drmFD, 0)) != 0) + fprintf(stderr, "[drm] failure adding irq handler, " + "there is a device already using that irq\n" + "[drm] falling back to irq-free operation\n"); +} + + +/** + * \brief Initialize the AGP heap. + * + * \param disp display handle. + * \param info driver private data. + * + * This function is a wrapper around the DRM_RADEON_INIT_HEAP command, passing + * all the parameters in a drm_radeon_mem_init_heap structure. + */ +static void RADEONDRIAgpHeapInit(driDisplay *disp, + RADEONInfoPtr info) +{ + drm_radeon_mem_init_heap_t drmHeap; + + /* Start up the simple memory manager for gart space */ + drmHeap.region = RADEON_MEM_REGION_GART; + drmHeap.start = 0; + drmHeap.size = info->gartTexMapSize; + + if (drmCommandWrite(disp->drmFD, DRM_RADEON_INIT_HEAP, + &drmHeap, sizeof(drmHeap))) { + fprintf(stderr, + "[drm] Failed to initialized gart heap manager\n"); + } else { + fprintf(stderr, + "[drm] Initialized kernel gart heap manager, %d\n", + info->gartTexMapSize); + } +} + +static int RADEONGetCardType(driDisplay *disp, RADEONInfoPtr info) +{ + drm_radeon_getparam_t gp; + int ret; + + gp.param = RADEON_PARAM_CARD_TYPE; + gp.value = &disp->card_type; + + ret=drmCommandWriteRead(disp->drmFD, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); + if (ret) { + fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_CARD_TYPE) : %d\n", ret); + return -1; + } + + return disp->card_type; +} + +/** + * Called at the start of each server generation. + * + * \param disp display handle. + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * Performs static frame buffer allocation. Opens the DRM device and add maps + * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more + * information. Creates a \e server context to grab the lock for the + * initialization ioctls and calls the other initilization functions in this + * file. Starts the CP engine via the DRM_RADEON_CP_START command. + * + * Setups a RADEONDRIRec structure to be passed to radeon_dri.so for its + * initialization. + */ +static int +RADEONScreenInit( driDisplay *disp, RADEONInfoPtr info, + RADEONDRIPtr pRADEONDRI) +{ + int i, err; + + /* XXX this probably isn't needed here */ + { + int width_bytes = (disp->virtualWidth * disp->cpp); + int maxy = disp->fbSize / width_bytes; + + if (maxy <= disp->virtualHeight * 3) { + _eglLog(_EGL_WARNING, + "Static buffer allocation failed -- " + "need at least %d kB video memory (have %d kB)\n", + (disp->virtualWidth * disp->virtualHeight * + disp->cpp * 3 + 1023) / 1024, + disp->fbSize / 1024); + return 0; + } + } + + /* Memory manager setup */ + if (!RADEONMemoryInit(disp, info)) { + return 0; + } + + /* Create a 'server' context so we can grab the lock for + * initialization ioctls. + */ + if ((err = drmCreateContext(disp->drmFD, &disp->serverContext)) != 0) { + _eglLog(_EGL_WARNING, "%s: drmCreateContext failed %d\n", + __FUNCTION__, err); + return 0; + } + + DRM_LOCK(disp->drmFD, disp->pSAREA, disp->serverContext, 0); + + /* Initialize the kernel data structures */ + if (!RADEONDRIKernelInit(disp, info)) { + _eglLog(_EGL_WARNING, "RADEONDRIKernelInit failed\n"); + DRM_UNLOCK(disp->drmFD, disp->pSAREA, disp->serverContext); + return 0; + } + + /* Initialize the vertex buffers list */ + if (!RADEONDRIBufInit(disp, info)) { + fprintf(stderr, "RADEONDRIBufInit failed\n"); + DRM_UNLOCK(disp->drmFD, disp->pSAREA, disp->serverContext); + return 0; + } + + /* Initialize IRQ */ + RADEONDRIIrqInit(disp, info); + + /* Initialize kernel gart memory manager */ + RADEONDRIAgpHeapInit(disp, info); + + /* Initialize the SAREA private data structure */ + { + drm_radeon_sarea_t *pSAREAPriv; + pSAREAPriv = (drm_radeon_sarea_t *)(((char*)disp->pSAREA) + + sizeof(drm_sarea_t)); + memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); + pSAREAPriv->pfState = info->page_flip_enable; + } + + for ( i = 0;; i++ ) { + drmMapType type; + drmMapFlags flags; + drm_handle_t handle, offset; + drmSize size; + int rc, mtrr; + + if ( ( rc = drmGetMap( disp->drmFD, i, &offset, &size, &type, &flags, &handle, &mtrr ) ) != 0 ) + break; + if ( type == DRM_REGISTERS ) { + pRADEONDRI->registerHandle = offset; + pRADEONDRI->registerSize = size; + break; + } + } + /* Quick hack to clear the front & back buffers. Could also use + * the clear ioctl to do this, but would need to setup hw state + * first. + */ + drimemsetio((char *)disp->pFB + info->frontOffset, + 0xEE, + info->frontPitch * disp->cpp * disp->virtualHeight ); + + drimemsetio((char *)disp->pFB + info->backOffset, + 0x30, + info->backPitch * disp->cpp * disp->virtualHeight ); + + + /* This is the struct passed to radeon_dri.so for its initialization */ + pRADEONDRI->deviceID = info->Chipset; + pRADEONDRI->width = disp->virtualWidth; + pRADEONDRI->height = disp->virtualHeight; + pRADEONDRI->depth = disp->bpp; /* XXX: depth */ + pRADEONDRI->bpp = disp->bpp; + pRADEONDRI->IsPCI = (disp->card_type != RADEON_CARD_AGP);; + pRADEONDRI->frontOffset = info->frontOffset; + pRADEONDRI->frontPitch = info->frontPitch; + pRADEONDRI->backOffset = info->backOffset; + pRADEONDRI->backPitch = info->backPitch; + pRADEONDRI->depthOffset = info->depthOffset; + pRADEONDRI->depthPitch = info->depthPitch; + pRADEONDRI->textureOffset = info->textureOffset; + pRADEONDRI->textureSize = info->textureSize; + pRADEONDRI->log2TexGran = info->log2TexGran; + pRADEONDRI->statusHandle = info->ringReadPtrHandle; + pRADEONDRI->statusSize = info->ringReadMapSize; + pRADEONDRI->gartTexHandle = info->gartTexHandle; + pRADEONDRI->gartTexMapSize = info->gartTexMapSize; + pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran; + pRADEONDRI->gartTexOffset = info->gartTexStart; + pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t); + + /* Don't release the lock now - let the VT switch handler do it. */ + + return 1; +} + + +/** + * \brief Get Radeon chip family from chipset number. + * + * \param info driver private data. + * + * \return non-zero on success, or zero on failure. + * + * Called by radeonInitFBDev() to set RADEONInfoRec::ChipFamily + * according to the value of RADEONInfoRec::Chipset. Fails if the + * chipset is unrecognized or not appropriate for this driver (i.e., not + * an r100 style radeon) + */ +static int get_chipfamily_from_chipset( RADEONInfoPtr info ) +{ + switch (info->Chipset) { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + info->ChipFamily = CHIP_FAMILY_M6; + break; + + case PCI_CHIP_RADEON_QY: + case PCI_CHIP_RADEON_QZ: + info->ChipFamily = CHIP_FAMILY_VE; + break; + + case PCI_CHIP_R200_QL: + case PCI_CHIP_R200_QN: + case PCI_CHIP_R200_QO: + case PCI_CHIP_R200_Ql: + case PCI_CHIP_R200_BB: + info->ChipFamily = CHIP_FAMILY_R200; + break; + + case PCI_CHIP_RV200_QW: /* RV200 desktop */ + case PCI_CHIP_RV200_QX: + info->ChipFamily = CHIP_FAMILY_RV200; + break; + + case PCI_CHIP_RADEON_LW: + case PCI_CHIP_RADEON_LX: + info->ChipFamily = CHIP_FAMILY_M7; + break; + + case PCI_CHIP_RV250_Id: + case PCI_CHIP_RV250_Ie: + case PCI_CHIP_RV250_If: + case PCI_CHIP_RV250_Ig: + info->ChipFamily = CHIP_FAMILY_RV250; + break; + + case PCI_CHIP_RV250_Ld: + case PCI_CHIP_RV250_Le: + case PCI_CHIP_RV250_Lf: + case PCI_CHIP_RV250_Lg: + info->ChipFamily = CHIP_FAMILY_M9; + break; + + case PCI_CHIP_RV280_Y_: + case PCI_CHIP_RV280_Ya: + case PCI_CHIP_RV280_Yb: + case PCI_CHIP_RV280_Yc: + info->ChipFamily = CHIP_FAMILY_RV280; + break; + + case PCI_CHIP_R300_ND: + case PCI_CHIP_R300_NE: + case PCI_CHIP_R300_NF: + case PCI_CHIP_R300_NG: + info->ChipFamily = CHIP_FAMILY_R300; + break; + + case PCI_CHIP_RV370_5460: + info->ChipFamily = CHIP_FAMILY_RV380; + break; + + default: + /* Original Radeon/7200 */ + info->ChipFamily = CHIP_FAMILY_RADEON; + } + + return 1; +} + + +/** + * \brief Initialize the framebuffer device mode + * + * \param disp display handle. + * + * \return one on success, or zero on failure. + * + * Fills in \p info with some default values and some information from \p disp + * and then calls RADEONScreenInit() for the screen initialization. + * + * Before exiting clears the framebuffer memory accessing it directly. + */ +static int radeonInitFBDev( driDisplay *disp, RADEONDRIPtr pRADEONDRI ) +{ + int err; + RADEONInfoPtr info = calloc(1, sizeof(*info)); + + disp->driverPrivate = (void *)info; + + info->gartFastWrite = RADEON_DEFAULT_AGP_FAST_WRITE; + info->gartSize = RADEON_DEFAULT_AGP_SIZE; + info->gartTexSize = RADEON_DEFAULT_AGP_TEX_SIZE; + info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; + info->ringSize = RADEON_DEFAULT_RING_SIZE; + info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP; + + fprintf(stderr, + "Using %d MB AGP aperture\n", info->gartSize); + fprintf(stderr, + "Using %d MB for the ring buffer\n", info->ringSize); + fprintf(stderr, + "Using %d MB for vertex/indirect buffers\n", info->bufSize); + fprintf(stderr, + "Using %d MB for AGP textures\n", info->gartTexSize); + fprintf(stderr, + "page flipping %sabled\n", info->page_flip_enable?"en":"dis"); + + info->Chipset = disp->chipset; + + if (!get_chipfamily_from_chipset( info )) { + fprintf(stderr, "Unknown or non-radeon chipset -- cannot continue\n"); + fprintf(stderr, "==> Verify PCI BusID is correct in miniglx.conf\n"); + return 0; + } +#if 0 + if (info->ChipFamily >= CHIP_FAMILY_R300) { + fprintf(stderr, + "Direct rendering not yet supported on " + "Radeon 9700 and newer cards\n"); + return 0; + } +#endif + +#if 00 + /* don't seem to need this here */ + info->frontPitch = disp->virtualWidth; +#endif + + /* Check the radeon DRM version */ + if (!RADEONCheckDRMVersion(disp, info)) { + return 0; + } + + if (RADEONGetCardType(disp, info)<0) + return 0; + + if (disp->card_type!=RADEON_CARD_AGP) { + /* Initialize PCI */ + if (!RADEONDRIPciInit(disp, info)) + return 0; + } + else { + /* Initialize AGP */ + if (!RADEONDRIAgpInit(disp, info)) + return 0; + } + + if (!RADEONScreenInit( disp, info, pRADEONDRI)) + return 0; + + /* Initialize and start the CP if required */ + if ((err = drmCommandNone(disp->drmFD, DRM_RADEON_CP_START)) != 0) { + fprintf(stderr, "%s: CP start %d\n", __FUNCTION__, err); + return 0; + } + + return 1; +} + + +/** + * Create list of all supported surface configs, attach list to the display. + */ +static EGLBoolean +radeonFillInConfigs(_EGLDisplay *disp, unsigned pixel_bits, + unsigned depth_bits, + unsigned stencil_bits, GLboolean have_back_buffer) +{ + _EGLConfig *configs; + _EGLConfig *c; + unsigned int i, num_configs; + unsigned int depth_buffer_factor; + unsigned int back_buffer_factor; + GLenum fb_format; + GLenum fb_type; + + /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy + * enough to add support. Basically, if a context is created with an + * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping + * will never be used. + */ + static const GLenum back_buffer_modes[] = { + GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ + }; + + u_int8_t depth_bits_array[2]; + u_int8_t stencil_bits_array[2]; + + depth_bits_array[0] = depth_bits; + depth_bits_array[1] = depth_bits; + + /* Just like with the accumulation buffer, always provide some modes + * with a stencil buffer. It will be a sw fallback, but some apps won't + * care about that. + */ + stencil_bits_array[0] = 0; + stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; + + depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; + back_buffer_factor = (have_back_buffer) ? 2 : 1; + + num_configs = depth_buffer_factor * back_buffer_factor * 2; + + if (pixel_bits == 16) { + fb_format = GL_RGB; + fb_type = GL_UNSIGNED_SHORT_5_6_5; + } else { + fb_format = GL_RGBA; + fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; + } + + configs = calloc(sizeof(*configs), num_configs); + c = configs; + if (!_eglFillInConfigs(c, fb_format, fb_type, + depth_bits_array, stencil_bits_array, + depth_buffer_factor, + back_buffer_modes, back_buffer_factor, + GLX_TRUE_COLOR)) { + fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", + __func__, __LINE__); + return EGL_FALSE; + } + + /* Mark the visual as slow if there are "fake" stencil bits. + */ + for (i = 0, c = configs; i < num_configs; i++, c++) { + int stencil = GET_CONFIG_ATTRIB(c, EGL_STENCIL_SIZE); + if ((stencil != 0) && (stencil != stencil_bits)) { + SET_CONFIG_ATTRIB(c, EGL_CONFIG_CAVEAT, EGL_SLOW_CONFIG); + } + } + + for (i = 0, c = configs; i < num_configs; i++, c++) + _eglAddConfig(disp, c); + + free(configs); + + return EGL_TRUE; +} + + +/** + * Show the given surface on the named screen. + * If surface is EGL_NO_SURFACE, disable the screen's output. + */ +static EGLBoolean +radeonShowScreenSurfaceMESA(_EGLDriver *drv, EGLDisplay dpy, EGLScreenMESA screen, + EGLSurface surface, EGLModeMESA m) +{ + EGLBoolean b = _eglDRIShowScreenSurfaceMESA(drv, dpy, screen, surface, m); + return b; +} + + +/** + * Called via eglInitialize() by user. + */ +static EGLBoolean +radeonInitialize(_EGLDriver *drv, EGLDisplay dpy, EGLint *major, EGLint *minor) +{ + __DRIframebuffer framebuffer; + driDisplay *display; + + /* one-time init */ + radeon_drm_page_size = getpagesize(); + + if (!_eglDRIInitialize(drv, dpy, major, minor)) + return EGL_FALSE; + + display = Lookup_driDisplay(dpy); + + framebuffer.dev_priv_size = sizeof(RADEONDRIRec); + framebuffer.dev_priv = malloc(sizeof(RADEONDRIRec)); + + /* XXX we shouldn't hard-code values here! */ + /* we won't know the screen surface size until the user calls + * eglCreateScreenSurfaceMESA(). + */ +#if 0 + display->virtualWidth = 1024; + display->virtualHeight = 768; +#else + display->virtualWidth = 1280; + display->virtualHeight = 1024; +#endif + display->bpp = 32; + display->cpp = 4; + + if (!_eglDRIGetDisplayInfo(display)) + return EGL_FALSE; + + framebuffer.base = display->pFB; + framebuffer.width = display->virtualWidth; + framebuffer.height = display->virtualHeight; + framebuffer.stride = display->virtualWidth; + framebuffer.size = display->fbSize; + radeonInitFBDev( display, framebuffer.dev_priv ); + + if (!_eglDRICreateDisplay(display, &framebuffer)) + return EGL_FALSE; + + if (!_eglDRICreateScreens(display)) + return EGL_FALSE; + + /* create a variety of both 32 and 16-bit configurations */ + radeonFillInConfigs(&display->Base, 32, 24, 8, GL_TRUE); + radeonFillInConfigs(&display->Base, 16, 16, 0, GL_TRUE); + + drv->Initialized = EGL_TRUE; + return EGL_TRUE; +} + + +/** + * The bootstrap function. Return a new radeonDriver object and + * plug in API functions. + */ +_EGLDriver * +_eglMain(_EGLDisplay *dpy) +{ + radeonDriver *radeon; + + radeon = (radeonDriver *) calloc(1, sizeof(*radeon)); + if (!radeon) { + return NULL; + } + + /* First fill in the dispatch table with defaults */ + _eglDRIInitDriverFallbacks(&radeon->Base); + + /* then plug in our radeon-specific functions */ + radeon->Base.API.Initialize = radeonInitialize; + radeon->Base.API.ShowScreenSurfaceMESA = radeonShowScreenSurfaceMESA; + + return &radeon->Base; +} diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_macros.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_macros.h new file mode 100644 index 00000000000..60f0fa2d351 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_macros.h @@ -0,0 +1,129 @@ +/** + * \file server/radeon_macros.h + * \brief Macros for Radeon MMIO operation. + * + * \authors Kevin E. Martin + * \authors Rickard E. Faith + * \authors Alan Hourihane + */ + +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.20 2002/10/12 01:38:07 martin Exp $ */ + +#ifndef _RADEON_MACROS_H_ +#define _RADEON_MACROS_H_ + +#include + +# define MMIO_IN8(base, offset) \ + *(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) +# define MMIO_IN32(base, offset) \ + read_MMIO_LE32(base, offset) +# define MMIO_OUT8(base, offset, val) \ + *(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val) +# define MMIO_OUT32(base, offset, val) \ + *(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = CPU_TO_LE32(val) + + + /* Memory mapped register access macros */ +#define INREG8(addr) MMIO_IN8(RADEONMMIO, addr) +#define INREG(addr) MMIO_IN32(RADEONMMIO, addr) +#define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val) +#define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val) + +#define ADDRREG(addr) ((volatile GLuint *)(pointer)(RADEONMMIO + (addr))) + + +#define OUTREGP(addr, val, mask) \ +do { \ + GLuint tmp = INREG(addr); \ + tmp &= (mask); \ + tmp |= (val); \ + OUTREG(addr, tmp); \ +} while (0) + +#define INPLL(dpy, addr) RADEONINPLL(dpy, addr) + +#define OUTPLL(addr, val) \ +do { \ + OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | \ + RADEON_PLL_WR_EN)); \ + OUTREG(RADEON_CLOCK_CNTL_DATA, val); \ +} while (0) + +#define OUTPLLP(dpy, addr, val, mask) \ +do { \ + GLuint tmp = INPLL(dpy, addr); \ + tmp &= (mask); \ + tmp |= (val); \ + OUTPLL(addr, tmp); \ +} while (0) + +#define OUTPAL_START(idx) \ +do { \ + OUTREG8(RADEON_PALETTE_INDEX, (idx)); \ +} while (0) + +#define OUTPAL_NEXT(r, g, b) \ +do { \ + OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \ +} while (0) + +#define OUTPAL_NEXT_CARD32(v) \ +do { \ + OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \ +} while (0) + +#define OUTPAL(idx, r, g, b) \ +do { \ + OUTPAL_START((idx)); \ + OUTPAL_NEXT((r), (g), (b)); \ +} while (0) + +#define INPAL_START(idx) \ +do { \ + OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \ +} while (0) + +#define INPAL_NEXT() INREG(RADEON_PALETTE_DATA) + +#define PAL_SELECT(idx) \ +do { \ + if (!idx) { \ + OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ + (GLuint)~RADEON_DAC2_PALETTE_ACC_CTL); \ + } else { \ + OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \ + RADEON_DAC2_PALETTE_ACC_CTL); \ + } \ +} while (0) + + +#endif diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_reg.h b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_reg.h new file mode 100644 index 00000000000..4dcce638460 --- /dev/null +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/r300/server/radeon_reg.h @@ -0,0 +1,2144 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.30 2003/10/07 22:47:12 martin Exp $ */ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * Rickard E. Faith + * Alan Hourihane + * + * References: + * + * !!!! FIXME !!!! + * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical + * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April + * 1999. + * + * !!!! FIXME !!!! + * RAGE 128 Software Development Manual (Technical Reference Manual P/N + * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. + * + */ + +/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h + * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT + * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ + +#ifndef _RADEON_REG_H_ +#define _RADEON_REG_H_ + + /* Registers for 2D/Video/Overlay */ +#define RADEON_ADAPTER_ID 0x0f2c /* PCI */ +#define RADEON_AGP_BASE 0x0170 +#define RADEON_AGP_CNTL 0x0174 +# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) +# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) +# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) +# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) +# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) +# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) +# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) +# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) +#define RADEON_AGP_COMMAND 0x0f60 /* PCI */ +#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ +# define RADEON_AGP_ENABLE (1<<8) +#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ +#define RADEON_AGP_STATUS 0x0f5c /* PCI */ +# define RADEON_AGP_1X_MODE 0x01 +# define RADEON_AGP_2X_MODE 0x02 +# define RADEON_AGP_4X_MODE 0x04 +# define RADEON_AGP_FW_MODE 0x10 +# define RADEON_AGP_MODE_MASK 0x17 +#define RADEON_ATTRDR 0x03c1 /* VGA */ +#define RADEON_ATTRDW 0x03c0 /* VGA */ +#define RADEON_ATTRX 0x03c0 /* VGA */ +#define RADEON_AUX_SC_CNTL 0x1660 +# define RADEON_AUX1_SC_EN (1 << 0) +# define RADEON_AUX1_SC_MODE_OR (0 << 1) +# define RADEON_AUX1_SC_MODE_NAND (1 << 1) +# define RADEON_AUX2_SC_EN (1 << 2) +# define RADEON_AUX2_SC_MODE_OR (0 << 3) +# define RADEON_AUX2_SC_MODE_NAND (1 << 3) +# define RADEON_AUX3_SC_EN (1 << 4) +# define RADEON_AUX3_SC_MODE_OR (0 << 5) +# define RADEON_AUX3_SC_MODE_NAND (1 << 5) +#define RADEON_AUX1_SC_BOTTOM 0x1670 +#define RADEON_AUX1_SC_LEFT 0x1664 +#define RADEON_AUX1_SC_RIGHT 0x1668 +#define RADEON_AUX1_SC_TOP 0x166c +#define RADEON_AUX2_SC_BOTTOM 0x1680 +#define RADEON_AUX2_SC_LEFT 0x1674 +#define RADEON_AUX2_SC_RIGHT 0x1678 +#define RADEON_AUX2_SC_TOP 0x167c +#define RADEON_AUX3_SC_BOTTOM 0x1690 +#define RADEON_AUX3_SC_LEFT 0x1684 +#define RADEON_AUX3_SC_RIGHT 0x1688 +#define RADEON_AUX3_SC_TOP 0x168c +#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 +#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc + +#define RADEON_BASE_CODE 0x0f0b +#define RADEON_BIOS_0_SCRATCH 0x0010 +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +#define RADEON_BIOS_5_SCRATCH 0x0024 +#define RADEON_BIOS_6_SCRATCH 0x0028 +#define RADEON_BIOS_7_SCRATCH 0x002c +#define RADEON_BIOS_ROM 0x0f30 /* PCI */ +#define RADEON_BIST 0x0f0f /* PCI */ +#define RADEON_BRUSH_DATA0 0x1480 +#define RADEON_BRUSH_DATA1 0x1484 +#define RADEON_BRUSH_DATA10 0x14a8 +#define RADEON_BRUSH_DATA11 0x14ac +#define RADEON_BRUSH_DATA12 0x14b0 +#define RADEON_BRUSH_DATA13 0x14b4 +#define RADEON_BRUSH_DATA14 0x14b8 +#define RADEON_BRUSH_DATA15 0x14bc +#define RADEON_BRUSH_DATA16 0x14c0 +#define RADEON_BRUSH_DATA17 0x14c4 +#define RADEON_BRUSH_DATA18 0x14c8 +#define RADEON_BRUSH_DATA19 0x14cc +#define RADEON_BRUSH_DATA2 0x1488 +#define RADEON_BRUSH_DATA20 0x14d0 +#define RADEON_BRUSH_DATA21 0x14d4 +#define RADEON_BRUSH_DATA22 0x14d8 +#define RADEON_BRUSH_DATA23 0x14dc +#define RADEON_BRUSH_DATA24 0x14e0 +#define RADEON_BRUSH_DATA25 0x14e4 +#define RADEON_BRUSH_DATA26 0x14e8 +#define RADEON_BRUSH_DATA27 0x14ec +#define RADEON_BRUSH_DATA28 0x14f0 +#define RADEON_BRUSH_DATA29 0x14f4 +#define RADEON_BRUSH_DATA3 0x148c +#define RADEON_BRUSH_DATA30 0x14f8 +#define RADEON_BRUSH_DATA31 0x14fc +#define RADEON_BRUSH_DATA32 0x1500 +#define RADEON_BRUSH_DATA33 0x1504 +#define RADEON_BRUSH_DATA34 0x1508 +#define RADEON_BRUSH_DATA35 0x150c +#define RADEON_BRUSH_DATA36 0x1510 +#define RADEON_BRUSH_DATA37 0x1514 +#define RADEON_BRUSH_DATA38 0x1518 +#define RADEON_BRUSH_DATA39 0x151c +#define RADEON_BRUSH_DATA4 0x1490 +#define RADEON_BRUSH_DATA40 0x1520 +#define RADEON_BRUSH_DATA41 0x1524 +#define RADEON_BRUSH_DATA42 0x1528 +#define RADEON_BRUSH_DATA43 0x152c +#define RADEON_BRUSH_DATA44 0x1530 +#define RADEON_BRUSH_DATA45 0x1534 +#define RADEON_BRUSH_DATA46 0x1538 +#define RADEON_BRUSH_DATA47 0x153c +#define RADEON_BRUSH_DATA48 0x1540 +#define RADEON_BRUSH_DATA49 0x1544 +#define RADEON_BRUSH_DATA5 0x1494 +#define RADEON_BRUSH_DATA50 0x1548 +#define RADEON_BRUSH_DATA51 0x154c +#define RADEON_BRUSH_DATA52 0x1550 +#define RADEON_BRUSH_DATA53 0x1554 +#define RADEON_BRUSH_DATA54 0x1558 +#define RADEON_BRUSH_DATA55 0x155c +#define RADEON_BRUSH_DATA56 0x1560 +#define RADEON_BRUSH_DATA57 0x1564 +#define RADEON_BRUSH_DATA58 0x1568 +#define RADEON_BRUSH_DATA59 0x156c +#define RADEON_BRUSH_DATA6 0x1498 +#define RADEON_BRUSH_DATA60 0x1570 +#define RADEON_BRUSH_DATA61 0x1574 +#define RADEON_BRUSH_DATA62 0x1578 +#define RADEON_BRUSH_DATA63 0x157c +#define RADEON_BRUSH_DATA7 0x149c +#define RADEON_BRUSH_DATA8 0x14a0 +#define RADEON_BRUSH_DATA9 0x14a4 +#define RADEON_BRUSH_SCALE 0x1470 +#define RADEON_BRUSH_Y_X 0x1474 +#define RADEON_BUS_CNTL 0x0030 +# define RADEON_BUS_MASTER_DIS (1 << 6) +# define RADEON_BUS_RD_DISCARD_EN (1 << 24) +# define RADEON_BUS_RD_ABORT_EN (1 << 25) +# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) +# define RADEON_BUS_WRT_BURST (1 << 29) +# define RADEON_BUS_READ_BURST (1 << 30) +#define RADEON_BUS_CNTL1 0x0034 +# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) + +#define RADEON_CACHE_CNTL 0x1724 +#define RADEON_CACHE_LINE 0x0f0c /* PCI */ +#define RADEON_CAP0_TRIG_CNTL 0x0950 /* ? */ +#define RADEON_CAP1_TRIG_CNTL 0x09c0 /* ? */ +#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ +#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ +#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ +#define RADEON_CLOCK_CNTL_DATA 0x000c +#define RADEON_CLOCK_CNTL_INDEX 0x0008 +# define RADEON_PLL_WR_EN (1 << 7) +# define RADEON_PLL_DIV_SEL (3 << 8) +# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) +#define RADEON_CLR_CMP_CLR_3D 0x1a24 +#define RADEON_CLR_CMP_CLR_DST 0x15c8 +#define RADEON_CLR_CMP_CLR_SRC 0x15c4 +#define RADEON_CLR_CMP_CNTL 0x15c0 +# define RADEON_SRC_CMP_EQ_COLOR (4 << 0) +# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) +# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) +#define RADEON_CLR_CMP_MASK 0x15cc +# define RADEON_CLR_CMP_MSK 0xffffffff +#define RADEON_CLR_CMP_MASK_3D 0x1A28 +#define RADEON_COMMAND 0x0f04 /* PCI */ +#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c +#define RADEON_CONFIG_APER_0_BASE 0x0100 +#define RADEON_CONFIG_APER_1_BASE 0x0104 +#define RADEON_CONFIG_APER_SIZE 0x0108 +#define RADEON_CONFIG_BONDS 0x00e8 +#define RADEON_CONFIG_CNTL 0x00e0 +# define RADEON_CFG_ATI_REV_A11 (0 << 16) +# define RADEON_CFG_ATI_REV_A12 (1 << 16) +# define RADEON_CFG_ATI_REV_A13 (2 << 16) +# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) +#define RADEON_CONFIG_MEMSIZE 0x00f8 +#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 +#define RADEON_CONFIG_REG_1_BASE 0x010c +#define RADEON_CONFIG_REG_APER_SIZE 0x0110 +#define RADEON_CONFIG_XSTRAP 0x00e4 +#define RADEON_CONSTANT_COLOR_C 0x1d34 +# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff +# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff +# define RADEON_CONSTANT_COLOR_ZERO 0x00000000 +#define RADEON_CRC_CMDFIFO_ADDR 0x0740 +#define RADEON_CRC_CMDFIFO_DOUT 0x0744 +#define RADEON_GRPH_BUFFER_CNTL 0x02f0 +# define RADEON_GRPH_START_REQ_MASK (0x7f) +# define RADEON_GRPH_START_REQ_SHIFT 0 +# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) +# define RADEON_GRPH_STOP_REQ_SHIFT 8 +# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) +# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 +# define RADEON_GRPH_CRITICAL_CNTL (1<<28) +# define RADEON_GRPH_BUFFER_SIZE (1<<29) +# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) +# define RADEON_GRPH_STOP_CNTL (1<<31) +#define RADEON_GRPH2_BUFFER_CNTL 0x03f0 +# define RADEON_GRPH2_START_REQ_MASK (0x7f) +# define RADEON_GRPH2_START_REQ_SHIFT 0 +# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) +# define RADEON_GRPH2_STOP_REQ_SHIFT 8 +# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) +# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 +# define RADEON_GRPH2_CRITICAL_CNTL (1<<28) +# define RADEON_GRPH2_BUFFER_SIZE (1<<29) +# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) +# define RADEON_GRPH2_STOP_CNTL (1<<31) +#define RADEON_CRTC_CRNT_FRAME 0x0214 +#define RADEON_CRTC_EXT_CNTL 0x0054 +# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) +# define RADEON_VGA_ATI_LINEAR (1 << 3) +# define RADEON_XCRT_CNT_EN (1 << 6) +# define RADEON_CRTC_HSYNC_DIS (1 << 8) +# define RADEON_CRTC_VSYNC_DIS (1 << 9) +# define RADEON_CRTC_DISPLAY_DIS (1 << 10) +# define RADEON_CRTC_SYNC_TRISTAT (1 << 11) +# define RADEON_CRTC_CRT_ON (1 << 15) +#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) +# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) +# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define RADEON_CRTC_GEN_CNTL 0x0050 +# define RADEON_CRTC_DBL_SCAN_EN (1 << 0) +# define RADEON_CRTC_INTERLACE_EN (1 << 1) +# define RADEON_CRTC_CSYNC_EN (1 << 4) +# define RADEON_CRTC_CUR_EN (1 << 16) +# define RADEON_CRTC_CUR_MODE_MASK (7 << 17) +# define RADEON_CRTC_ICON_EN (1 << 20) +# define RADEON_CRTC_EXT_DISP_EN (1 << 24) +# define RADEON_CRTC_EN (1 << 25) +# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) +#define RADEON_CRTC2_GEN_CNTL 0x03f8 +# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) +# define RADEON_CRTC2_INTERLACE_EN (1 << 1) +# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) +# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) +# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) +# define RADEON_CRTC2_CRT2_ON (1 << 7) +# define RADEON_CRTC2_ICON_EN (1 << 15) +# define RADEON_CRTC2_CUR_EN (1 << 16) +# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) +# define RADEON_CRTC2_DISP_DIS (1 << 23) +# define RADEON_CRTC2_EN (1 << 25) +# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) +# define RADEON_CRTC2_CSYNC_EN (1 << 27) +# define RADEON_CRTC2_HSYNC_DIS (1 << 28) +# define RADEON_CRTC2_VSYNC_DIS (1 << 29) +#define RADEON_CRTC_MORE_CNTL 0x27c +# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 +#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 +# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) +# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +# define RADEON_CRTC_H_SYNC_WID (0x3f << 16) +# define RADEON_CRTC_H_SYNC_WID_SHIFT 16 +# define RADEON_CRTC_H_SYNC_POL (1 << 23) +#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 +# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) +# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 +# define RADEON_CRTC2_H_SYNC_POL (1 << 23) +#define RADEON_CRTC_H_TOTAL_DISP 0x0200 +# define RADEON_CRTC_H_TOTAL (0x03ff << 0) +# define RADEON_CRTC_H_TOTAL_SHIFT 0 +# define RADEON_CRTC_H_DISP (0x01ff << 16) +# define RADEON_CRTC_H_DISP_SHIFT 16 +#define RADEON_CRTC2_H_TOTAL_DISP 0x0300 +# define RADEON_CRTC2_H_TOTAL (0x03ff << 0) +# define RADEON_CRTC2_H_TOTAL_SHIFT 0 +# define RADEON_CRTC2_H_DISP (0x01ff << 16) +# define RADEON_CRTC2_H_DISP_SHIFT 16 +#define RADEON_CRTC_OFFSET 0x0224 +#define RADEON_CRTC2_OFFSET 0x0324 +#define RADEON_CRTC_OFFSET_CNTL 0x0228 +# define RADEON_CRTC_TILE_EN (1 << 15) +#define RADEON_CRTC2_OFFSET_CNTL 0x0328 +# define RADEON_CRTC2_TILE_EN (1 << 15) +#define RADEON_CRTC_PITCH 0x022c +#define RADEON_CRTC2_PITCH 0x032c +#define RADEON_CRTC_STATUS 0x005c +# define RADEON_CRTC_VBLANK_SAVE (1 << 1) +# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) +#define RADEON_CRTC2_STATUS 0x03fc +# define RADEON_CRTC2_VBLANK_SAVE (1 << 1) +# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) +#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c +# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) +# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 +# define RADEON_CRTC_V_SYNC_WID (0x1f << 16) +# define RADEON_CRTC_V_SYNC_WID_SHIFT 16 +# define RADEON_CRTC_V_SYNC_POL (1 << 23) +#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c +# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) +# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 +# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) +# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 +# define RADEON_CRTC2_V_SYNC_POL (1 << 23) +#define RADEON_CRTC_V_TOTAL_DISP 0x0208 +# define RADEON_CRTC_V_TOTAL (0x07ff << 0) +# define RADEON_CRTC_V_TOTAL_SHIFT 0 +# define RADEON_CRTC_V_DISP (0x07ff << 16) +# define RADEON_CRTC_V_DISP_SHIFT 16 +#define RADEON_CRTC2_V_TOTAL_DISP 0x0308 +# define RADEON_CRTC2_V_TOTAL (0x07ff << 0) +# define RADEON_CRTC2_V_TOTAL_SHIFT 0 +# define RADEON_CRTC2_V_DISP (0x07ff << 16) +# define RADEON_CRTC2_V_DISP_SHIFT 16 +#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 +# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define RADEON_CRTC2_CRNT_FRAME 0x0314 +#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 +#define RADEON_CRTC2_STATUS 0x03fc +#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 +#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ +#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ +#define RADEON_CUR_CLR0 0x026c +#define RADEON_CUR_CLR1 0x0270 +#define RADEON_CUR_HORZ_VERT_OFF 0x0268 +#define RADEON_CUR_HORZ_VERT_POSN 0x0264 +#define RADEON_CUR_OFFSET 0x0260 +# define RADEON_CUR_LOCK (1 << 31) +#define RADEON_CUR2_CLR0 0x036c +#define RADEON_CUR2_CLR1 0x0370 +#define RADEON_CUR2_HORZ_VERT_OFF 0x0368 +#define RADEON_CUR2_HORZ_VERT_POSN 0x0364 +#define RADEON_CUR2_OFFSET 0x0360 +# define RADEON_CUR2_LOCK (1 << 31) + +#define RADEON_DAC_CNTL 0x0058 +# define RADEON_DAC_RANGE_CNTL (3 << 0) +# define RADEON_DAC_RANGE_CNTL_MASK 0x03 +# define RADEON_DAC_BLANKING (1 << 2) +# define RADEON_DAC_CMP_EN (1 << 3) +# define RADEON_DAC_CMP_OUTPUT (1 << 7) +# define RADEON_DAC_8BIT_EN (1 << 8) +# define RADEON_DAC_VGA_ADR_EN (1 << 13) +# define RADEON_DAC_PDWN (1 << 15) +# define RADEON_DAC_MASK_ALL (0xff << 24) +#define RADEON_DAC_CNTL2 0x007c +# define RADEON_DAC2_DAC_CLK_SEL (1 << 0) +# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) +# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) +#define RADEON_DAC_EXT_CNTL 0x0280 +# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) +# define RADEON_DAC_FORCE_DATA_EN (1 << 5) +# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) +# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 +# define RADEON_DAC_FORCE_DATA_SHIFT 8 +#define RADEON_TV_DAC_CNTL 0x088c +# define RADEON_TV_DAC_STD_MASK 0x0300 +# define RADEON_TV_DAC_RDACPD (1 << 24) +# define RADEON_TV_DAC_GDACPD (1 << 25) +# define RADEON_TV_DAC_BDACPD (1 << 26) +#define RADEON_DISP_HW_DEBUG 0x0d14 +# define RADEON_CRT2_DISP1_SEL (1 << 5) +#define RADEON_DISP_OUTPUT_CNTL 0x0d64 +# define RADEON_DISP_DAC_SOURCE_MASK 0x03 +# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c +# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 +# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 +#define RADEON_DAC_CRC_SIG 0x02cc +#define RADEON_DAC_DATA 0x03c9 /* VGA */ +#define RADEON_DAC_MASK 0x03c6 /* VGA */ +#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ +#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ +#define RADEON_DDA_CONFIG 0x02e0 +#define RADEON_DDA_ON_OFF 0x02e4 +#define RADEON_DEFAULT_OFFSET 0x16e0 +#define RADEON_DEFAULT_PITCH 0x16e4 +#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 +# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 +#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 +#define RADEON_DEVICE_ID 0x0f02 /* PCI */ +#define RADEON_DISP_MISC_CNTL 0x0d00 +# define RADEON_SOFT_RESET_GRPH_PP (1 << 0) +#define RADEON_DISP_MERGE_CNTL 0x0d60 +# define RADEON_DISP_ALPHA_MODE_MASK 0x03 +# define RADEON_DISP_ALPHA_MODE_KEY 0 +# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 +# define RADEON_DISP_ALPHA_MODE_GLOBAL 2 +# define RADEON_DISP_RGB_OFFSET_EN (1<<8) +# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) +# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) +# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) +#define RADEON_DISP2_MERGE_CNTL 0x0d68 +# define RADEON_DISP2_RGB_OFFSET_EN (1<<8) +#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 +#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 +#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 +#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c +#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 +#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 +#define RADEON_DP_BRUSH_BKGD_CLR 0x1478 +#define RADEON_DP_BRUSH_FRGD_CLR 0x147c +#define RADEON_DP_CNTL 0x16c0 +# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) +# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) +#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 +# define RADEON_DST_Y_MAJOR (1 << 2) +# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) +# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) +#define RADEON_DP_DATATYPE 0x16c4 +# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) +#define RADEON_DP_GUI_MASTER_CNTL 0x146c +# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define RADEON_GMC_SRC_CLIPPING (1 << 2) +# define RADEON_GMC_DST_CLIPPING (1 << 3) +# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) +# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) +# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) +# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) +# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) +# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) +# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) +# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) +# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) +# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) +# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) +# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define RADEON_GMC_BRUSH_NONE (15 << 4) +# define RADEON_GMC_DST_8BPP_CI (2 << 8) +# define RADEON_GMC_DST_15BPP (3 << 8) +# define RADEON_GMC_DST_16BPP (4 << 8) +# define RADEON_GMC_DST_24BPP (5 << 8) +# define RADEON_GMC_DST_32BPP (6 << 8) +# define RADEON_GMC_DST_8BPP_RGB (7 << 8) +# define RADEON_GMC_DST_Y8 (8 << 8) +# define RADEON_GMC_DST_RGB8 (9 << 8) +# define RADEON_GMC_DST_VYUY (11 << 8) +# define RADEON_GMC_DST_YVYU (12 << 8) +# define RADEON_GMC_DST_AYUV444 (14 << 8) +# define RADEON_GMC_DST_ARGB4444 (15 << 8) +# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) +# define RADEON_GMC_DST_DATATYPE_SHIFT 8 +# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) +# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) +# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) +# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) +# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) +# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) +# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) +# define RADEON_GMC_CONVERSION_TEMP (1 << 15) +# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) +# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) +# define RADEON_GMC_ROP3_MASK (0xff << 16) +# define RADEON_DP_SRC_SOURCE_MASK (7 << 24) +# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) +# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define RADEON_GMC_3D_FCN_EN (1 << 27) +# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define RADEON_GMC_AUX_CLIP_DIS (1 << 29) +# define RADEON_GMC_WR_MSK_DIS (1 << 30) +# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) +# define RADEON_ROP3_ZERO 0x00000000 +# define RADEON_ROP3_DSa 0x00880000 +# define RADEON_ROP3_SDna 0x00440000 +# define RADEON_ROP3_S 0x00cc0000 +# define RADEON_ROP3_DSna 0x00220000 +# define RADEON_ROP3_D 0x00aa0000 +# define RADEON_ROP3_DSx 0x00660000 +# define RADEON_ROP3_DSo 0x00ee0000 +# define RADEON_ROP3_DSon 0x00110000 +# define RADEON_ROP3_DSxn 0x00990000 +# define RADEON_ROP3_Dn 0x00550000 +# define RADEON_ROP3_SDno 0x00dd0000 +# define RADEON_ROP3_Sn 0x00330000 +# define RADEON_ROP3_DSno 0x00bb0000 +# define RADEON_ROP3_DSan 0x00770000 +# define RADEON_ROP3_ONE 0x00ff0000 +# define RADEON_ROP3_DPa 0x00a00000 +# define RADEON_ROP3_PDna 0x00500000 +# define RADEON_ROP3_P 0x00f00000 +# define RADEON_ROP3_DPna 0x000a0000 +# define RADEON_ROP3_D 0x00aa0000 +# define RADEON_ROP3_DPx 0x005a0000 +# define RADEON_ROP3_DPo 0x00fa0000 +# define RADEON_ROP3_DPon 0x00050000 +# define RADEON_ROP3_PDxn 0x00a50000 +# define RADEON_ROP3_PDno 0x00f50000 +# define RADEON_ROP3_Pn 0x000f0000 +# define RADEON_ROP3_DPno 0x00af0000 +# define RADEON_ROP3_DPan 0x005f0000 +#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 +#define RADEON_DP_MIX 0x16c8 +#define RADEON_DP_SRC_BKGD_CLR 0x15dc +#define RADEON_DP_SRC_FRGD_CLR 0x15d8 +#define RADEON_DP_WRITE_MASK 0x16cc +#define RADEON_DST_BRES_DEC 0x1630 +#define RADEON_DST_BRES_ERR 0x1628 +#define RADEON_DST_BRES_INC 0x162c +#define RADEON_DST_BRES_LNTH 0x1634 +#define RADEON_DST_BRES_LNTH_SUB 0x1638 +#define RADEON_DST_HEIGHT 0x1410 +#define RADEON_DST_HEIGHT_WIDTH 0x143c +#define RADEON_DST_HEIGHT_WIDTH_8 0x158c +#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 +#define RADEON_DST_HEIGHT_Y 0x15a0 +#define RADEON_DST_LINE_START 0x1600 +#define RADEON_DST_LINE_END 0x1604 +#define RADEON_DST_LINE_PATCOUNT 0x1608 +# define RADEON_BRES_CNTL_SHIFT 8 +#define RADEON_DST_OFFSET 0x1404 +#define RADEON_DST_PITCH 0x1408 +#define RADEON_DST_PITCH_OFFSET 0x142c +#define RADEON_DST_PITCH_OFFSET_C 0x1c80 +# define RADEON_PITCH_SHIFT 21 +# define RADEON_DST_TILE_LINEAR (0 << 30) +# define RADEON_DST_TILE_MACRO (1 << 30) +# define RADEON_DST_TILE_MICRO (2 << 30) +# define RADEON_DST_TILE_BOTH (3 << 30) +#define RADEON_DST_WIDTH 0x140c +#define RADEON_DST_WIDTH_HEIGHT 0x1598 +#define RADEON_DST_WIDTH_X 0x1588 +#define RADEON_DST_WIDTH_X_INCY 0x159c +#define RADEON_DST_X 0x141c +#define RADEON_DST_X_SUB 0x15a4 +#define RADEON_DST_X_Y 0x1594 +#define RADEON_DST_Y 0x1420 +#define RADEON_DST_Y_SUB 0x15a8 +#define RADEON_DST_Y_X 0x1438 + +#define RADEON_FCP_CNTL 0x0910 +# define RADEON_FCP0_SRC_PCICLK 0 +# define RADEON_FCP0_SRC_PCLK 1 +# define RADEON_FCP0_SRC_PCLKb 2 +# define RADEON_FCP0_SRC_HREF 3 +# define RADEON_FCP0_SRC_GND 4 +# define RADEON_FCP0_SRC_HREFb 5 +#define RADEON_FLUSH_1 0x1704 +#define RADEON_FLUSH_2 0x1708 +#define RADEON_FLUSH_3 0x170c +#define RADEON_FLUSH_4 0x1710 +#define RADEON_FLUSH_5 0x1714 +#define RADEON_FLUSH_6 0x1718 +#define RADEON_FLUSH_7 0x171c +#define RADEON_FOG_3D_TABLE_START 0x1810 +#define RADEON_FOG_3D_TABLE_END 0x1814 +#define RADEON_FOG_3D_TABLE_DENSITY 0x181c +#define RADEON_FOG_TABLE_INDEX 0x1a14 +#define RADEON_FOG_TABLE_DATA 0x1a18 +#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 +#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 +#define RADEON_FP_CRTC2_H_TOTAL_DISP 0x0350 +#define RADEON_FP_CRTC2_V_TOTAL_DISP 0x0354 +# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff +# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 +# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff +# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 +# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 +# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff +# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 +# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 +# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 +# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 +# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 +# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 +# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 +# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 +#define RADEON_FP_GEN_CNTL 0x0284 +# define RADEON_FP_FPON (1 << 0) +# define RADEON_FP_TMDS_EN (1 << 2) +# define RADEON_FP_PANEL_FORMAT (1 << 3) +# define RADEON_FP_EN_TMDS (1 << 7) +# define RADEON_FP_DETECT_SENSE (1 << 8) +# define RADEON_FP_SEL_CRTC2 (1 << 13) +# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) +# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) +# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +# define RADEON_FP_DFP_SYNC_SEL (1 << 21) +# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) +# define RADEON_FP_CRT_SYNC_SEL (1 << 23) +# define RADEON_FP_USE_SHADOW_EN (1 << 24) +# define RADEON_FP_CRT_SYNC_ALT (1 << 26) +#define RADEON_FP2_GEN_CNTL 0x0288 +# define RADEON_FP2_BLANK_EN (1 << 1) +# define RADEON_FP2_ON (1 << 2) +# define RADEON_FP2_PANEL_FORMAT (1 << 3) +# define RADEON_FP2_SOURCE_SEL_MASK (3 << 10) +# define RADEON_FP2_SOURCE_SEL_CRTC2 (1 << 10) +# define RADEON_FP2_SRC_SEL_MASK (3 << 13) +# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) +# define RADEON_FP2_FP_POL (1 << 16) +# define RADEON_FP2_LP_POL (1 << 17) +# define RADEON_FP2_SCK_POL (1 << 18) +# define RADEON_FP2_LCD_CNTL_MASK (7 << 19) +# define RADEON_FP2_PAD_FLOP_EN (1 << 22) +# define RADEON_FP2_CRC_EN (1 << 23) +# define RADEON_FP2_CRC_READ_EN (1 << 24) +# define RADEON_FP2_DV0_EN (1 << 25) +# define RADEON_FP2_DV0_RATE_SEL_SDR (1 << 26) +#define RADEON_FP_H_SYNC_STRT_WID 0x02c4 +#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 +#define RADEON_FP_HORZ_STRETCH 0x028c +#define RADEON_FP_HORZ2_STRETCH 0x038c +# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff +# define RADEON_HORZ_STRETCH_RATIO_MAX 4096 +# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) +# define RADEON_HORZ_PANEL_SHIFT 16 +# define RADEON_HORZ_STRETCH_PIXREP (0 << 25) +# define RADEON_HORZ_STRETCH_BLEND (1 << 26) +# define RADEON_HORZ_STRETCH_ENABLE (1 << 25) +# define RADEON_HORZ_AUTO_RATIO (1 << 27) +# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) +# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) +#define RADEON_FP_V_SYNC_STRT_WID 0x02c8 +#define RADEON_FP_VERT_STRETCH 0x0290 +#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 +#define RADEON_FP_VERT2_STRETCH 0x0390 +# define RADEON_VERT_PANEL_SIZE (0xfff << 12) +# define RADEON_VERT_PANEL_SHIFT 12 +# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff +# define RADEON_VERT_STRETCH_RATIO_SHIFT 0 +# define RADEON_VERT_STRETCH_RATIO_MAX 4096 +# define RADEON_VERT_STRETCH_ENABLE (1 << 25) +# define RADEON_VERT_STRETCH_LINEREP (0 << 26) +# define RADEON_VERT_STRETCH_BLEND (1 << 26) +# define RADEON_VERT_AUTO_RATIO_EN (1 << 27) +# define RADEON_VERT_STRETCH_RESERVED 0xf1000000 + +#define RADEON_GEN_INT_CNTL 0x0040 +#define RADEON_GEN_INT_STATUS 0x0044 +# define RADEON_VSYNC_INT_AK (1 << 2) +# define RADEON_VSYNC_INT (1 << 2) +# define RADEON_VSYNC2_INT_AK (1 << 6) +# define RADEON_VSYNC2_INT (1 << 6) +#define RADEON_GENENB 0x03c3 /* VGA */ +#define RADEON_GENFC_RD 0x03ca /* VGA */ +#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ +#define RADEON_GENMO_RD 0x03cc /* VGA */ +#define RADEON_GENMO_WT 0x03c2 /* VGA */ +#define RADEON_GENS0 0x03c2 /* VGA */ +#define RADEON_GENS1 0x03da /* VGA, 0x03ba */ +#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ +#define RADEON_GPIO_MONIDB 0x006c +#define RADEON_GPIO_CRT2_DDC 0x006c +#define RADEON_GPIO_DVI_DDC 0x0064 +#define RADEON_GPIO_VGA_DDC 0x0060 +# define RADEON_GPIO_A_0 (1 << 0) +# define RADEON_GPIO_A_1 (1 << 1) +# define RADEON_GPIO_Y_0 (1 << 8) +# define RADEON_GPIO_Y_1 (1 << 9) +# define RADEON_GPIO_Y_SHIFT_0 8 +# define RADEON_GPIO_Y_SHIFT_1 9 +# define RADEON_GPIO_EN_0 (1 << 16) +# define RADEON_GPIO_EN_1 (1 << 17) +# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ +# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ +#define RADEON_GRPH8_DATA 0x03cf /* VGA */ +#define RADEON_GRPH8_IDX 0x03ce /* VGA */ +#define RADEON_GUI_SCRATCH_REG0 0x15e0 +#define RADEON_GUI_SCRATCH_REG1 0x15e4 +#define RADEON_GUI_SCRATCH_REG2 0x15e8 +#define RADEON_GUI_SCRATCH_REG3 0x15ec +#define RADEON_GUI_SCRATCH_REG4 0x15f0 +#define RADEON_GUI_SCRATCH_REG5 0x15f4 + +#define RADEON_HEADER 0x0f0e /* PCI */ +#define RADEON_HOST_DATA0 0x17c0 +#define RADEON_HOST_DATA1 0x17c4 +#define RADEON_HOST_DATA2 0x17c8 +#define RADEON_HOST_DATA3 0x17cc +#define RADEON_HOST_DATA4 0x17d0 +#define RADEON_HOST_DATA5 0x17d4 +#define RADEON_HOST_DATA6 0x17d8 +#define RADEON_HOST_DATA7 0x17dc +#define RADEON_HOST_DATA_LAST 0x17e0 +#define RADEON_HOST_PATH_CNTL 0x0130 +# define RADEON_HDP_SOFT_RESET (1 << 26) +#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ +#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ + +#define RADEON_I2C_CNTL_1 0x0094 /* ? */ +#define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */ +#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ +#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ +#define RADEON_IO_BASE 0x0f14 /* PCI */ + +#define RADEON_LATENCY 0x0f0d /* PCI */ +#define RADEON_LEAD_BRES_DEC 0x1608 +#define RADEON_LEAD_BRES_LNTH 0x161c +#define RADEON_LEAD_BRES_LNTH_SUB 0x1624 +#define RADEON_LVDS_GEN_CNTL 0x02d0 +# define RADEON_LVDS_ON (1 << 0) +# define RADEON_LVDS_DISPLAY_DIS (1 << 1) +# define RADEON_LVDS_PANEL_TYPE (1 << 2) +# define RADEON_LVDS_PANEL_FORMAT (1 << 3) +# define RADEON_LVDS_EN (1 << 7) +# define RADEON_LVDS_DIGON (1 << 18) +# define RADEON_LVDS_BLON (1 << 19) +# define RADEON_LVDS_SEL_CRTC2 (1 << 23) +#define RADEON_LVDS_PLL_CNTL 0x02d4 +# define RADEON_HSYNC_DELAY_SHIFT 28 +# define RADEON_HSYNC_DELAY_MASK (0xf << 28) + +#define RADEON_MAX_LATENCY 0x0f3f /* PCI */ +#define RADEON_MC_AGP_LOCATION 0x014c +#define RADEON_MC_FB_LOCATION 0x0148 +#define RADEON_DISPLAY_BASE_ADDR 0x23c +#define RADEON_DISPLAY2_BASE_ADDR 0x33c +#define RADEON_OV0_BASE_ADDR 0x43c +#define RADEON_NB_TOM 0x15c +#define RADEON_MCLK_CNTL 0x0012 /* PLL */ +# define RADEON_FORCEON_MCLKA (1 << 16) +# define RADEON_FORCEON_MCLKB (1 << 17) +# define RADEON_FORCEON_YCLKA (1 << 18) +# define RADEON_FORCEON_YCLKB (1 << 19) +# define RADEON_FORCEON_MC (1 << 20) +# define RADEON_FORCEON_AIC (1 << 21) +#define RADEON_MDGPIO_A_REG 0x01ac +#define RADEON_MDGPIO_EN_REG 0x01b0 +#define RADEON_MDGPIO_MASK 0x0198 +#define RADEON_MDGPIO_Y_REG 0x01b4 +#define RADEON_MEM_ADDR_CONFIG 0x0148 +#define RADEON_MEM_BASE 0x0f10 /* PCI */ +#define RADEON_MEM_CNTL 0x0140 +# define RADEON_MEM_NUM_CHANNELS_MASK 0x01 +# define RADEON_MEM_USE_B_CH_ONLY (1<<1) +# define RV100_HALF_MODE (1<<3) +# define R300_MEM_NUM_CHANNELS_MASK 0x03 +# define R300_MEM_USE_CD_CH_ONLY (1<<2) +#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ +#define RADEON_MEM_INIT_LAT_TIMER 0x0154 +#define RADEON_MEM_INTF_CNTL 0x014c +#define RADEON_MEM_SDRAM_MODE_REG 0x0158 +#define RADEON_MEM_STR_CNTL 0x0150 +#define RADEON_MEM_VGA_RP_SEL 0x003c +#define RADEON_MEM_VGA_WP_SEL 0x0038 +#define RADEON_MIN_GRANT 0x0f3e /* PCI */ +#define RADEON_MM_DATA 0x0004 +#define RADEON_MM_INDEX 0x0000 +#define RADEON_MPLL_CNTL 0x000e /* PLL */ +#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ +#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ +#define R300_MC_IND_INDEX 0x01f8 +# define R300_MC_IND_ADDR_MASK 0x3f +#define R300_MC_IND_DATA 0x01fc +#define R300_MC_READ_CNTL_AB 0x017c +# define R300_MEM_RBS_POSITION_A_MASK 0x03 +#define R300_MC_READ_CNTL_CD_mcind 0x24 +# define R300_MEM_RBS_POSITION_C_MASK 0x03 + +#define RADEON_N_VIF_COUNT 0x0248 + +#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 +#define RADEON_OV0_COLOUR_CNTL 0x04E0 +#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 +#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 +# define RADEON_EXCL_HORZ_START_MASK 0x000000ff +# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 +# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define RADEON_OV0_EXCLUSIVE_VERT 0x040C +# define RADEON_EXCL_VERT_START_MASK 0x000003ff +# define RADEON_EXCL_VERT_END_MASK 0x03ff0000 +#define RADEON_OV0_FILTER_CNTL 0x04A0 +#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 +#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 +#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 +#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC +#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 +#define RADEON_OV0_GAMMA_000_00F 0x0d40 +#define RADEON_OV0_GAMMA_010_01F 0x0d44 +#define RADEON_OV0_GAMMA_020_03F 0x0d48 +#define RADEON_OV0_GAMMA_040_07F 0x0d4c +#define RADEON_OV0_GAMMA_080_0BF 0x0e00 +#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 +#define RADEON_OV0_GAMMA_100_13F 0x0e08 +#define RADEON_OV0_GAMMA_140_17F 0x0e0c +#define RADEON_OV0_GAMMA_180_1BF 0x0e10 +#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 +#define RADEON_OV0_GAMMA_200_23F 0x0e18 +#define RADEON_OV0_GAMMA_240_27F 0x0e1c +#define RADEON_OV0_GAMMA_280_2BF 0x0e20 +#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 +#define RADEON_OV0_GAMMA_300_33F 0x0e28 +#define RADEON_OV0_GAMMA_340_37F 0x0e2c +#define RADEON_OV0_GAMMA_380_3BF 0x0d50 +#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 +#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC +#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 +#define RADEON_OV0_H_INC 0x0480 +#define RADEON_OV0_KEY_CNTL 0x04F4 +# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L +# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L +# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L +# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L +# define RADEON_VIDEO_KEY_FN_NE 0x00000003L +# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L +# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L +# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L +# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L +# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L +# define RADEON_CMP_MIX_MASK 0x00000100L +# define RADEON_CMP_MIX_OR 0x00000000L +# define RADEON_CMP_MIX_AND 0x00000100L +#define RADEON_OV0_LIN_TRANS_A 0x0d20 +#define RADEON_OV0_LIN_TRANS_B 0x0d24 +#define RADEON_OV0_LIN_TRANS_C 0x0d28 +#define RADEON_OV0_LIN_TRANS_D 0x0d2c +#define RADEON_OV0_LIN_TRANS_E 0x0d30 +#define RADEON_OV0_LIN_TRANS_F 0x0d34 +#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L +#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 +#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 +# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define RADEON_OV0_P1_X_START_END 0x0494 +#define RADEON_OV0_P2_X_START_END 0x0498 +#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L +#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C +#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C +#define RADEON_OV0_P3_X_START_END 0x049C +#define RADEON_OV0_REG_LOAD_CNTL 0x0410 +# define RADEON_REG_LD_CTL_LOCK 0x00000001L +# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L +#define RADEON_OV0_SCALE_CNTL 0x0420 +# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L +# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L +# define RADEON_SCALER_SIGNED_UV 0x00000010L +# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L +# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L +# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L +# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L +# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L +# define RADEON_SCALER_SOURCE_15BPP 0x00000300L +# define RADEON_SCALER_SOURCE_16BPP 0x00000400L +# define RADEON_SCALER_SOURCE_32BPP 0x00000600L +# define RADEON_SCALER_SOURCE_YUV9 0x00000900L +# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L +# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L +# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L +# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L +# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L +# define RADEON_SCALER_SMART_SWITCH 0x00008000L +# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L +# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L +# define RADEON_SCALER_DIS_LIMIT 0x08000000L +# define RADEON_SCALER_INT_EMU 0x20000000L +# define RADEON_SCALER_ENABLE 0x40000000L +# define RADEON_SCALER_SOFT_RESET 0x80000000L +# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L +#define RADEON_OV0_STEP_BY 0x0484 +#define RADEON_OV0_TEST 0x04F8 +#define RADEON_OV0_V_INC 0x0424 +#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 +# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 +# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 +# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C +#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 +#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 +#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 +#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 +#define RADEON_OV0_Y_X_START 0x0400 +#define RADEON_OV0_Y_X_END 0x0404 +#define RADEON_OV1_Y_X_START 0x0600 +#define RADEON_OV1_Y_X_END 0x0604 +#define RADEON_OVR_CLR 0x0230 +#define RADEON_OVR_WID_LEFT_RIGHT 0x0234 +#define RADEON_OVR_WID_TOP_BOTTOM 0x0238 + +#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ +# define RADEON_P2PLL_RESET (1 << 0) +# define RADEON_P2PLL_SLEEP (1 << 1) +# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define RADEON_P2PLL_DIV_0 0x002c +# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff +# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 +#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ +# define RADEON_P2PLL_REF_DIV_MASK 0x03ff +# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +# define R300_PPLL_REF_DIV_ACC_SHIFT 18 +#define RADEON_PALETTE_DATA 0x00b4 +#define RADEON_PALETTE_30_DATA 0x00b8 +#define RADEON_PALETTE_INDEX 0x00b0 +#define RADEON_PCI_GART_PAGE 0x017c +#define RADEON_PIXCLKS_CNTL 0x002d +# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 +# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 +# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 +# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 +# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) +# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) +# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) +# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +#define RADEON_PLANE_3D_MASK_C 0x1d44 +#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ +#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ +#define RADEON_PMI_DATA 0x0f63 /* PCI */ +#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ +#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ +#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ +#define RADEON_PMI_REGISTER 0x0f5c /* PCI */ +#define RADEON_PPLL_CNTL 0x0002 /* PLL */ +# define RADEON_PPLL_RESET (1 << 0) +# define RADEON_PPLL_SLEEP (1 << 1) +# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) +# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define RADEON_PPLL_DIV_0 0x0004 /* PLL */ +#define RADEON_PPLL_DIV_1 0x0005 /* PLL */ +#define RADEON_PPLL_DIV_2 0x0006 /* PLL */ +#define RADEON_PPLL_DIV_3 0x0007 /* PLL */ +# define RADEON_PPLL_FB3_DIV_MASK 0x07ff +# define RADEON_PPLL_POST3_DIV_MASK 0x00070000 +#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ +# define RADEON_PPLL_REF_DIV_MASK 0x03ff +# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ + +#define RADEON_RBBM_GUICNTL 0x172c +# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) +# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) +# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) +# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) +#define RADEON_RBBM_SOFT_RESET 0x00f0 +# define RADEON_SOFT_RESET_CP (1 << 0) +# define RADEON_SOFT_RESET_HI (1 << 1) +# define RADEON_SOFT_RESET_SE (1 << 2) +# define RADEON_SOFT_RESET_RE (1 << 3) +# define RADEON_SOFT_RESET_PP (1 << 4) +# define RADEON_SOFT_RESET_E2 (1 << 5) +# define RADEON_SOFT_RESET_RB (1 << 6) +# define RADEON_SOFT_RESET_HDP (1 << 7) +#define RADEON_RBBM_STATUS 0x0e40 +# define RADEON_RBBM_FIFOCNT_MASK 0x007f +# define RADEON_RBBM_ACTIVE (1 << 31) +#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c +# define RADEON_RB2D_DC_FLUSH (3 << 0) +# define RADEON_RB2D_DC_FREE (3 << 2) +# define RADEON_RB2D_DC_FLUSH_ALL 0xf +# define RADEON_RB2D_DC_BUSY (1 << 31) +#define RADEON_RB2D_DSTCACHE_MODE 0x3428 +#define RADEON_REG_BASE 0x0f18 /* PCI */ +#define RADEON_REGPROG_INF 0x0f09 /* PCI */ +#define RADEON_REVISION_ID 0x0f08 /* PCI */ + +#define RADEON_SC_BOTTOM 0x164c +#define RADEON_SC_BOTTOM_RIGHT 0x16f0 +#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c +#define RADEON_SC_LEFT 0x1640 +#define RADEON_SC_RIGHT 0x1644 +#define RADEON_SC_TOP 0x1648 +#define RADEON_SC_TOP_LEFT 0x16ec +#define RADEON_SC_TOP_LEFT_C 0x1c88 +# define RADEON_SC_SIGN_MASK_LO 0x8000 +# define RADEON_SC_SIGN_MASK_HI 0x80000000 +#define RADEON_SCLK_CNTL 0x000d /* PLL */ +# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 +# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 +# define RADEON_SCLK_FORCEON_MASK 0xffff8000 +#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ +# define RADEON_SCLK_MORE_FORCEON 0x0700 +#define RADEON_SDRAM_MODE_REG 0x0158 +#define RADEON_SEQ8_DATA 0x03c5 /* VGA */ +#define RADEON_SEQ8_IDX 0x03c4 /* VGA */ +#define RADEON_SNAPSHOT_F_COUNT 0x0244 +#define RADEON_SNAPSHOT_VH_COUNTS 0x0240 +#define RADEON_SNAPSHOT_VIF_COUNT 0x024c +#define RADEON_SRC_OFFSET 0x15ac +#define RADEON_SRC_PITCH 0x15b0 +#define RADEON_SRC_PITCH_OFFSET 0x1428 +#define RADEON_SRC_SC_BOTTOM 0x165c +#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 +#define RADEON_SRC_SC_RIGHT 0x1654 +#define RADEON_SRC_X 0x1414 +#define RADEON_SRC_X_Y 0x1590 +#define RADEON_SRC_Y 0x1418 +#define RADEON_SRC_Y_X 0x1434 +#define RADEON_STATUS 0x0f06 /* PCI */ +#define RADEON_SUBPIC_CNTL 0x0540 /* ? */ +#define RADEON_SUB_CLASS 0x0f0a /* PCI */ +#define RADEON_SURFACE_CNTL 0x0b00 +# define RADEON_SURF_TRANSLATION_DIS (1 << 8) +# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) +# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) +#define RADEON_SURFACE0_INFO 0x0b0c +# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) +# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) +# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) +# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) +# define R200_SURF_TILE_NONE (0 << 16) +# define R200_SURF_TILE_COLOR_MACRO (1 << 16) +# define R200_SURF_TILE_COLOR_MICRO (2 << 16) +# define R200_SURF_TILE_COLOR_BOTH (3 << 16) +# define R200_SURF_TILE_DEPTH_32BPP (4 << 16) +# define R200_SURF_TILE_DEPTH_16BPP (5 << 16) +# define RADEON_SURF_AP0_SWP_16BPP (1 << 20) +# define RADEON_SURF_AP0_SWP_32BPP (1 << 21) +# define RADEON_SURF_AP1_SWP_16BPP (1 << 22) +# define RADEON_SURF_AP1_SWP_32BPP (1 << 23) +#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 +#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 +#define RADEON_SURFACE1_INFO 0x0b1c +#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 +#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 +#define RADEON_SURFACE2_INFO 0x0b2c +#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 +#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 +#define RADEON_SURFACE3_INFO 0x0b3c +#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 +#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 +#define RADEON_SURFACE4_INFO 0x0b4c +#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 +#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 +#define RADEON_SURFACE5_INFO 0x0b5c +#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 +#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 +#define RADEON_SURFACE6_INFO 0x0b6c +#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 +#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 +#define RADEON_SURFACE7_INFO 0x0b7c +#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 +#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 +#define RADEON_SW_SEMAPHORE 0x013c + +#define RADEON_TEST_DEBUG_CNTL 0x0120 +#define RADEON_TEST_DEBUG_MUX 0x0124 +#define RADEON_TEST_DEBUG_OUT 0x012c +#define RADEON_TMDS_PLL_CNTL 0x02a8 +#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 +# define RADEON_TMDS_TRANSMITTER_PLLEN 1 +# define RADEON_TMDS_TRANSMITTER_PLLRST 2 +#define RADEON_TRAIL_BRES_DEC 0x1614 +#define RADEON_TRAIL_BRES_ERR 0x160c +#define RADEON_TRAIL_BRES_INC 0x1610 +#define RADEON_TRAIL_X 0x1618 +#define RADEON_TRAIL_X_SUB 0x1620 + +#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ +# define RADEON_VCLK_SRC_SEL_MASK 0x03 +# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 +# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 +# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 +# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 +# define RADEON_PIXCLK_ALWAYS_ONb (1<<6) +# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) + +#define RADEON_VENDOR_ID 0x0f00 /* PCI */ +#define RADEON_VGA_DDA_CONFIG 0x02e8 +#define RADEON_VGA_DDA_ON_OFF 0x02ec +#define RADEON_VID_BUFFER_CONTROL 0x0900 +#define RADEON_VIDEOMUX_CNTL 0x0190 +#define RADEON_VIPH_CONTROL 0x0c40 /* ? */ + +#define RADEON_WAIT_UNTIL 0x1720 +# define RADEON_WAIT_CRTC_PFLIP (1 << 0) +# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) +# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) +# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) + +#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ +#define RADEON_XCLK_CNTL 0x000d /* PLL */ +#define RADEON_XDLL_CNTL 0x000c /* PLL */ +#define RADEON_XPLL_CNTL 0x000b /* PLL */ + + + + /* Registers for 3D/TCL */ +#define RADEON_PP_BORDER_COLOR_0 0x1d40 +#define RADEON_PP_BORDER_COLOR_1 0x1d44 +#define RADEON_PP_BORDER_COLOR_2 0x1d48 +#define RADEON_PP_CNTL 0x1c38 +# define RADEON_STIPPLE_ENABLE (1 << 0) +# define RADEON_SCISSOR_ENABLE (1 << 1) +# define RADEON_PATTERN_ENABLE (1 << 2) +# define RADEON_SHADOW_ENABLE (1 << 3) +# define RADEON_TEX_ENABLE_MASK (0xf << 4) +# define RADEON_TEX_0_ENABLE (1 << 4) +# define RADEON_TEX_1_ENABLE (1 << 5) +# define RADEON_TEX_2_ENABLE (1 << 6) +# define RADEON_TEX_3_ENABLE (1 << 7) +# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) +# define RADEON_TEX_BLEND_0_ENABLE (1 << 12) +# define RADEON_TEX_BLEND_1_ENABLE (1 << 13) +# define RADEON_TEX_BLEND_2_ENABLE (1 << 14) +# define RADEON_TEX_BLEND_3_ENABLE (1 << 15) +# define RADEON_PLANAR_YUV_ENABLE (1 << 20) +# define RADEON_SPECULAR_ENABLE (1 << 21) +# define RADEON_FOG_ENABLE (1 << 22) +# define RADEON_ALPHA_TEST_ENABLE (1 << 23) +# define RADEON_ANTI_ALIAS_NONE (0 << 24) +# define RADEON_ANTI_ALIAS_LINE (1 << 24) +# define RADEON_ANTI_ALIAS_POLY (2 << 24) +# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) +# define RADEON_BUMP_MAP_ENABLE (1 << 26) +# define RADEON_BUMPED_MAP_T0 (0 << 27) +# define RADEON_BUMPED_MAP_T1 (1 << 27) +# define RADEON_BUMPED_MAP_T2 (2 << 27) +# define RADEON_TEX_3D_ENABLE_0 (1 << 29) +# define RADEON_TEX_3D_ENABLE_1 (1 << 30) +# define RADEON_MC_ENABLE (1 << 31) +#define RADEON_PP_FOG_COLOR 0x1c18 +# define RADEON_FOG_COLOR_MASK 0x00ffffff +# define RADEON_FOG_VERTEX (0 << 24) +# define RADEON_FOG_TABLE (1 << 24) +# define RADEON_FOG_USE_DEPTH (0 << 25) +# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) +# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) +#define RADEON_PP_LUM_MATRIX 0x1d00 +#define RADEON_PP_MISC 0x1c14 +# define RADEON_REF_ALPHA_MASK 0x000000ff +# define RADEON_ALPHA_TEST_FAIL (0 << 8) +# define RADEON_ALPHA_TEST_LESS (1 << 8) +# define RADEON_ALPHA_TEST_LEQUAL (2 << 8) +# define RADEON_ALPHA_TEST_EQUAL (3 << 8) +# define RADEON_ALPHA_TEST_GEQUAL (4 << 8) +# define RADEON_ALPHA_TEST_GREATER (5 << 8) +# define RADEON_ALPHA_TEST_NEQUAL (6 << 8) +# define RADEON_ALPHA_TEST_PASS (7 << 8) +# define RADEON_ALPHA_TEST_OP_MASK (7 << 8) +# define RADEON_CHROMA_FUNC_FAIL (0 << 16) +# define RADEON_CHROMA_FUNC_PASS (1 << 16) +# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) +# define RADEON_CHROMA_FUNC_EQUAL (3 << 16) +# define RADEON_CHROMA_KEY_NEAREST (0 << 18) +# define RADEON_CHROMA_KEY_ZERO (1 << 18) +# define RADEON_SHADOW_ID_AUTO_INC (1 << 20) +# define RADEON_SHADOW_FUNC_EQUAL (0 << 21) +# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) +# define RADEON_SHADOW_PASS_1 (0 << 22) +# define RADEON_SHADOW_PASS_2 (1 << 22) +# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) +# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) +#define RADEON_PP_ROT_MATRIX_0 0x1d58 +#define RADEON_PP_ROT_MATRIX_1 0x1d5c +#define RADEON_PP_TXFILTER_0 0x1c54 +#define RADEON_PP_TXFILTER_1 0x1c6c +#define RADEON_PP_TXFILTER_2 0x1c84 +# define RADEON_MAG_FILTER_NEAREST (0 << 0) +# define RADEON_MAG_FILTER_LINEAR (1 << 0) +# define RADEON_MAG_FILTER_MASK (1 << 0) +# define RADEON_MIN_FILTER_NEAREST (0 << 1) +# define RADEON_MIN_FILTER_LINEAR (1 << 1) +# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) +# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +# define RADEON_MIN_FILTER_MASK (15 << 1) +# define RADEON_MAX_ANISO_1_TO_1 (0 << 5) +# define RADEON_MAX_ANISO_2_TO_1 (1 << 5) +# define RADEON_MAX_ANISO_4_TO_1 (2 << 5) +# define RADEON_MAX_ANISO_8_TO_1 (3 << 5) +# define RADEON_MAX_ANISO_16_TO_1 (4 << 5) +# define RADEON_MAX_ANISO_MASK (7 << 5) +# define RADEON_LOD_BIAS_MASK (0xff << 8) +# define RADEON_LOD_BIAS_SHIFT 8 +# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) +# define RADEON_MAX_MIP_LEVEL_SHIFT 16 +# define RADEON_YUV_TO_RGB (1 << 20) +# define RADEON_YUV_TEMPERATURE_COOL (0 << 21) +# define RADEON_YUV_TEMPERATURE_HOT (1 << 21) +# define RADEON_YUV_TEMPERATURE_MASK (1 << 21) +# define RADEON_WRAPEN_S (1 << 22) +# define RADEON_CLAMP_S_WRAP (0 << 23) +# define RADEON_CLAMP_S_MIRROR (1 << 23) +# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +# define RADEON_CLAMP_S_CLAMP_GL (6 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +# define RADEON_CLAMP_S_MASK (7 << 23) +# define RADEON_WRAPEN_T (1 << 26) +# define RADEON_CLAMP_T_WRAP (0 << 27) +# define RADEON_CLAMP_T_MIRROR (1 << 27) +# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +# define RADEON_CLAMP_T_CLAMP_GL (6 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +# define RADEON_CLAMP_T_MASK (7 << 27) +# define RADEON_BORDER_MODE_OGL (0 << 31) +# define RADEON_BORDER_MODE_D3D (1 << 31) +#define RADEON_PP_TXFORMAT_0 0x1c58 +#define RADEON_PP_TXFORMAT_1 0x1c70 +#define RADEON_PP_TXFORMAT_2 0x1c88 +# define RADEON_TXFORMAT_I8 (0 << 0) +# define RADEON_TXFORMAT_AI88 (1 << 0) +# define RADEON_TXFORMAT_RGB332 (2 << 0) +# define RADEON_TXFORMAT_ARGB1555 (3 << 0) +# define RADEON_TXFORMAT_RGB565 (4 << 0) +# define RADEON_TXFORMAT_ARGB4444 (5 << 0) +# define RADEON_TXFORMAT_ARGB8888 (6 << 0) +# define RADEON_TXFORMAT_RGBA8888 (7 << 0) +# define RADEON_TXFORMAT_Y8 (8 << 0) +# define RADEON_TXFORMAT_VYUY422 (10 << 0) +# define RADEON_TXFORMAT_YVYU422 (11 << 0) +# define RADEON_TXFORMAT_DXT1 (12 << 0) +# define RADEON_TXFORMAT_DXT23 (14 << 0) +# define RADEON_TXFORMAT_DXT45 (15 << 0) +# define RADEON_TXFORMAT_SHADOW16 (16 << 0) +# define RADEON_TXFORMAT_SHADOW32 (17 << 0) +# define RADEON_TXFORMAT_DUDV88 (18 << 0) +# define RADEON_TXFORMAT_LDUDV655 (19 << 0) +# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0) +# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) +# define RADEON_TXFORMAT_FORMAT_SHIFT 0 +# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) +# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) +# define RADEON_TXFORMAT_NON_POWER2 (1 << 7) +# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) +# define RADEON_TXFORMAT_WIDTH_SHIFT 8 +# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) +# define RADEON_TXFORMAT_HEIGHT_SHIFT 12 +# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) +# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 +# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 +# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) +# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) +# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) +# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) +# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) +#define RADEON_PP_CUBIC_FACES_0 0x1d24 +#define RADEON_PP_CUBIC_FACES_1 0x1d28 +#define RADEON_PP_CUBIC_FACES_2 0x1d2c +# define RADEON_FACE_WIDTH_1_SHIFT 0 +# define RADEON_FACE_HEIGHT_1_SHIFT 4 +# define RADEON_FACE_WIDTH_1_MASK (0xf << 0) +# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) +# define RADEON_FACE_WIDTH_2_SHIFT 8 +# define RADEON_FACE_HEIGHT_2_SHIFT 12 +# define RADEON_FACE_WIDTH_2_MASK (0xf << 8) +# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) +# define RADEON_FACE_WIDTH_3_SHIFT 16 +# define RADEON_FACE_HEIGHT_3_SHIFT 20 +# define RADEON_FACE_WIDTH_3_MASK (0xf << 16) +# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) +# define RADEON_FACE_WIDTH_4_SHIFT 24 +# define RADEON_FACE_HEIGHT_4_SHIFT 28 +# define RADEON_FACE_WIDTH_4_MASK (0xf << 24) +# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) + +#define RADEON_PP_TXOFFSET_0 0x1c5c +#define RADEON_PP_TXOFFSET_1 0x1c74 +#define RADEON_PP_TXOFFSET_2 0x1c8c +# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) +# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) +# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) +# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define RADEON_TXO_MACRO_LINEAR (0 << 2) +# define RADEON_TXO_MACRO_TILE (1 << 2) +# define RADEON_TXO_MICRO_LINEAR (0 << 3) +# define RADEON_TXO_MICRO_TILE_X2 (1 << 3) +# define RADEON_TXO_MICRO_TILE_OPT (2 << 3) +# define RADEON_TXO_OFFSET_MASK 0xffffffe0 +# define RADEON_TXO_OFFSET_SHIFT 5 + +#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ +#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 +#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 +#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc +#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 +#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 +#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 +#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 +#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c +#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 +#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 +#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 +#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c +#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 +#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 + +#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define RADEON_PP_TEX_SIZE_1 0x1d0c +#define RADEON_PP_TEX_SIZE_2 0x1d14 +# define RADEON_TEX_USIZE_MASK (0x7ff << 0) +# define RADEON_TEX_USIZE_SHIFT 0 +# define RADEON_TEX_VSIZE_MASK (0x7ff << 16) +# define RADEON_TEX_VSIZE_SHIFT 16 +# define RADEON_SIGNED_RGB_MASK (1 << 30) +# define RADEON_SIGNED_RGB_SHIFT 30 +# define RADEON_SIGNED_ALPHA_MASK (1 << 31) +# define RADEON_SIGNED_ALPHA_SHIFT 31 +#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ +#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ +#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ +/* note: bits 13-5: 32 byte aligned stride of texture map */ + +#define RADEON_PP_TXCBLEND_0 0x1c60 +#define RADEON_PP_TXCBLEND_1 0x1c78 +#define RADEON_PP_TXCBLEND_2 0x1c90 +# define RADEON_COLOR_ARG_A_SHIFT 0 +# define RADEON_COLOR_ARG_A_MASK (0x1f << 0) +# define RADEON_COLOR_ARG_A_ZERO (0 << 0) +# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) +# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) +# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) +# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) +# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) +# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) +# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) +# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) +# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) +# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) +# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) +# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) +# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) +# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) +# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) +# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) +# define RADEON_COLOR_ARG_B_SHIFT 5 +# define RADEON_COLOR_ARG_B_MASK (0x1f << 5) +# define RADEON_COLOR_ARG_B_ZERO (0 << 5) +# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) +# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) +# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) +# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) +# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) +# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) +# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) +# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) +# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) +# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) +# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) +# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) +# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) +# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) +# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) +# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) +# define RADEON_COLOR_ARG_C_SHIFT 10 +# define RADEON_COLOR_ARG_C_MASK (0x1f << 10) +# define RADEON_COLOR_ARG_C_ZERO (0 << 10) +# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) +# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) +# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) +# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) +# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) +# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) +# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) +# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) +# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) +# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) +# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) +# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) +# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) +# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) +# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) +# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) +# define RADEON_COMP_ARG_A (1 << 15) +# define RADEON_COMP_ARG_A_SHIFT 15 +# define RADEON_COMP_ARG_B (1 << 16) +# define RADEON_COMP_ARG_B_SHIFT 16 +# define RADEON_COMP_ARG_C (1 << 17) +# define RADEON_COMP_ARG_C_SHIFT 17 +# define RADEON_BLEND_CTL_MASK (7 << 18) +# define RADEON_BLEND_CTL_ADD (0 << 18) +# define RADEON_BLEND_CTL_SUBTRACT (1 << 18) +# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) +# define RADEON_BLEND_CTL_BLEND (3 << 18) +# define RADEON_BLEND_CTL_DOT3 (4 << 18) +# define RADEON_SCALE_SHIFT 21 +# define RADEON_SCALE_MASK (3 << 21) +# define RADEON_SCALE_1X (0 << 21) +# define RADEON_SCALE_2X (1 << 21) +# define RADEON_SCALE_4X (2 << 21) +# define RADEON_CLAMP_TX (1 << 23) +# define RADEON_T0_EQ_TCUR (1 << 24) +# define RADEON_T1_EQ_TCUR (1 << 25) +# define RADEON_T2_EQ_TCUR (1 << 26) +# define RADEON_T3_EQ_TCUR (1 << 27) +# define RADEON_COLOR_ARG_MASK 0x1f +# define RADEON_COMP_ARG_SHIFT 15 +#define RADEON_PP_TXABLEND_0 0x1c64 +#define RADEON_PP_TXABLEND_1 0x1c7c +#define RADEON_PP_TXABLEND_2 0x1c94 +# define RADEON_ALPHA_ARG_A_SHIFT 0 +# define RADEON_ALPHA_ARG_A_MASK (0xf << 0) +# define RADEON_ALPHA_ARG_A_ZERO (0 << 0) +# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) +# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) +# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) +# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) +# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) +# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) +# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) +# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) +# define RADEON_ALPHA_ARG_B_SHIFT 4 +# define RADEON_ALPHA_ARG_B_MASK (0xf << 4) +# define RADEON_ALPHA_ARG_B_ZERO (0 << 4) +# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) +# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) +# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) +# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) +# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) +# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) +# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) +# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) +# define RADEON_ALPHA_ARG_C_SHIFT 8 +# define RADEON_ALPHA_ARG_C_MASK (0xf << 8) +# define RADEON_ALPHA_ARG_C_ZERO (0 << 8) +# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) +# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) +# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) +# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) +# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) +# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) +# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) +# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) +# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) +# define RADEON_ALPHA_ARG_MASK 0xf + +#define RADEON_PP_TFACTOR_0 0x1c68 +#define RADEON_PP_TFACTOR_1 0x1c80 +#define RADEON_PP_TFACTOR_2 0x1c98 + +#define RADEON_RB3D_BLENDCNTL 0x1c20 +# define RADEON_COMB_FCN_MASK (3 << 12) +# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) +# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) +# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) +# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) +# define RADEON_SRC_BLEND_GL_ZERO (32 << 16) +# define RADEON_SRC_BLEND_GL_ONE (33 << 16) +# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) +# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) +# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) +# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) +# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) +# define RADEON_SRC_BLEND_MASK (63 << 16) +# define RADEON_DST_BLEND_GL_ZERO (32 << 24) +# define RADEON_DST_BLEND_GL_ONE (33 << 24) +# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) +# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) +# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) +# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) +# define RADEON_DST_BLEND_MASK (63 << 24) +#define RADEON_RB3D_CNTL 0x1c3c +# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) +# define RADEON_PLANE_MASK_ENABLE (1 << 1) +# define RADEON_DITHER_ENABLE (1 << 2) +# define RADEON_ROUND_ENABLE (1 << 3) +# define RADEON_SCALE_DITHER_ENABLE (1 << 4) +# define RADEON_DITHER_INIT (1 << 5) +# define RADEON_ROP_ENABLE (1 << 6) +# define RADEON_STENCIL_ENABLE (1 << 7) +# define RADEON_Z_ENABLE (1 << 8) +# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) +# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) +# define RADEON_COLOR_FORMAT_RGB565 (4 << 10) +# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) +# define RADEON_COLOR_FORMAT_RGB332 (7 << 10) +# define RADEON_COLOR_FORMAT_Y8 (8 << 10) +# define RADEON_COLOR_FORMAT_RGB8 (9 << 10) +# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) +# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) +# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) +# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) +# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) +# define RADEON_ZBLOCK16 (1 << 15) +#define RADEON_RB3D_COLOROFFSET 0x1c40 +# define RADEON_COLOROFFSET_MASK 0xfffffff0 +#define RADEON_RB3D_COLORPITCH 0x1c48 +# define RADEON_COLORPITCH_MASK 0x000001ff8 +# define RADEON_COLOR_TILE_ENABLE (1 << 16) +# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) +# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) +# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) +# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) +#define RADEON_RB3D_DEPTHOFFSET 0x1c24 +#define RADEON_RB3D_DEPTHPITCH 0x1c28 +# define RADEON_DEPTHPITCH_MASK 0x00001ff8 +# define RADEON_DEPTH_HYPERZ (3 << 16) +# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) +# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) +# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) +#define RADEON_RB3D_PLANEMASK 0x1d84 +#define RADEON_RB3D_ROPCNTL 0x1d80 +# define RADEON_ROP_MASK (15 << 8) +# define RADEON_ROP_CLEAR (0 << 8) +# define RADEON_ROP_NOR (1 << 8) +# define RADEON_ROP_AND_INVERTED (2 << 8) +# define RADEON_ROP_COPY_INVERTED (3 << 8) +# define RADEON_ROP_AND_REVERSE (4 << 8) +# define RADEON_ROP_INVERT (5 << 8) +# define RADEON_ROP_XOR (6 << 8) +# define RADEON_ROP_NAND (7 << 8) +# define RADEON_ROP_AND (8 << 8) +# define RADEON_ROP_EQUIV (9 << 8) +# define RADEON_ROP_NOOP (10 << 8) +# define RADEON_ROP_OR_INVERTED (11 << 8) +# define RADEON_ROP_COPY (12 << 8) +# define RADEON_ROP_OR_REVERSE (13 << 8) +# define RADEON_ROP_OR (14 << 8) +# define RADEON_ROP_SET (15 << 8) +#define RADEON_RB3D_STENCILREFMASK 0x1d7c +# define RADEON_STENCIL_REF_SHIFT 0 +# define RADEON_STENCIL_REF_MASK (0xff << 0) +# define RADEON_STENCIL_MASK_SHIFT 16 +# define RADEON_STENCIL_VALUE_MASK (0xff << 16) +# define RADEON_STENCIL_WRITEMASK_SHIFT 24 +# define RADEON_STENCIL_WRITE_MASK (0xff << 24) +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +# define RADEON_DEPTH_FORMAT_MASK (0xf << 0) +# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) +# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) +# define RADEON_Z_TEST_NEVER (0 << 4) +# define RADEON_Z_TEST_LESS (1 << 4) +# define RADEON_Z_TEST_LEQUAL (2 << 4) +# define RADEON_Z_TEST_EQUAL (3 << 4) +# define RADEON_Z_TEST_GEQUAL (4 << 4) +# define RADEON_Z_TEST_GREATER (5 << 4) +# define RADEON_Z_TEST_NEQUAL (6 << 4) +# define RADEON_Z_TEST_ALWAYS (7 << 4) +# define RADEON_Z_TEST_MASK (7 << 4) +# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) +# define RADEON_STENCIL_TEST_NEVER (0 << 12) +# define RADEON_STENCIL_TEST_LESS (1 << 12) +# define RADEON_STENCIL_TEST_LEQUAL (2 << 12) +# define RADEON_STENCIL_TEST_EQUAL (3 << 12) +# define RADEON_STENCIL_TEST_GEQUAL (4 << 12) +# define RADEON_STENCIL_TEST_GREATER (5 << 12) +# define RADEON_STENCIL_TEST_NEQUAL (6 << 12) +# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) +# define RADEON_STENCIL_TEST_MASK (0x7 << 12) +# define RADEON_STENCIL_FAIL_KEEP (0 << 16) +# define RADEON_STENCIL_FAIL_ZERO (1 << 16) +# define RADEON_STENCIL_FAIL_REPLACE (2 << 16) +# define RADEON_STENCIL_FAIL_INC (3 << 16) +# define RADEON_STENCIL_FAIL_DEC (4 << 16) +# define RADEON_STENCIL_FAIL_INVERT (5 << 16) +# define RADEON_STENCIL_FAIL_INC_WRAP (6 << 16) +# define RADEON_STENCIL_FAIL_DEC_WRAP (7 << 16) +# define RADEON_STENCIL_FAIL_MASK (0x7 << 16) +# define RADEON_STENCIL_ZPASS_KEEP (0 << 20) +# define RADEON_STENCIL_ZPASS_ZERO (1 << 20) +# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) +# define RADEON_STENCIL_ZPASS_INC (3 << 20) +# define RADEON_STENCIL_ZPASS_DEC (4 << 20) +# define RADEON_STENCIL_ZPASS_INVERT (5 << 20) +# define RADEON_STENCIL_ZPASS_INC_WRAP (6 << 20) +# define RADEON_STENCIL_ZPASS_DEC_WRAP (7 << 20) +# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) +# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) +# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) +# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) +# define RADEON_STENCIL_ZFAIL_INC (3 << 24) +# define RADEON_STENCIL_ZFAIL_DEC (4 << 24) +# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) +# define RADEON_STENCIL_ZFAIL_INC_WRAP (6 << 24) +# define RADEON_STENCIL_ZFAIL_DEC_WRAP (7 << 24) +# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) +# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) +# define RADEON_FORCE_Z_DIRTY (1 << 29) +# define RADEON_Z_WRITE_ENABLE (1 << 30) +# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) +#define RADEON_RE_LINE_PATTERN 0x1cd0 +# define RADEON_LINE_PATTERN_MASK 0x0000ffff +# define RADEON_LINE_REPEAT_COUNT_SHIFT 16 +# define RADEON_LINE_PATTERN_START_SHIFT 24 +# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) +# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) +# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) +#define RADEON_RE_LINE_STATE 0x1cd4 +# define RADEON_LINE_CURRENT_PTR_SHIFT 0 +# define RADEON_LINE_CURRENT_COUNT_SHIFT 8 +#define RADEON_RE_MISC 0x26c4 +# define RADEON_STIPPLE_COORD_MASK 0x1f +# define RADEON_STIPPLE_X_OFFSET_SHIFT 0 +# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) +# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 +# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) +# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) +# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) +#define RADEON_RE_SOLID_COLOR 0x1c1c +#define RADEON_RE_TOP_LEFT 0x26c0 +# define RADEON_RE_LEFT_SHIFT 0 +# define RADEON_RE_TOP_SHIFT 16 +#define RADEON_RE_WIDTH_HEIGHT 0x1c44 +# define RADEON_RE_WIDTH_SHIFT 0 +# define RADEON_RE_HEIGHT_SHIFT 16 + +#define RADEON_SE_CNTL 0x1c4c +# define RADEON_FFACE_CULL_CW (0 << 0) +# define RADEON_FFACE_CULL_CCW (1 << 0) +# define RADEON_FFACE_CULL_DIR_MASK (1 << 0) +# define RADEON_BFACE_CULL (0 << 1) +# define RADEON_BFACE_SOLID (3 << 1) +# define RADEON_FFACE_CULL (0 << 3) +# define RADEON_FFACE_SOLID (3 << 3) +# define RADEON_FFACE_CULL_MASK (3 << 3) +# define RADEON_BADVTX_CULL_DISABLE (1 << 5) +# define RADEON_FLAT_SHADE_VTX_0 (0 << 6) +# define RADEON_FLAT_SHADE_VTX_1 (1 << 6) +# define RADEON_FLAT_SHADE_VTX_2 (2 << 6) +# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) +# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) +# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) +# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) +# define RADEON_DIFFUSE_SHADE_MASK (3 << 8) +# define RADEON_ALPHA_SHADE_SOLID (0 << 10) +# define RADEON_ALPHA_SHADE_FLAT (1 << 10) +# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) +# define RADEON_ALPHA_SHADE_MASK (3 << 10) +# define RADEON_SPECULAR_SHADE_SOLID (0 << 12) +# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) +# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) +# define RADEON_SPECULAR_SHADE_MASK (3 << 12) +# define RADEON_FOG_SHADE_SOLID (0 << 14) +# define RADEON_FOG_SHADE_FLAT (1 << 14) +# define RADEON_FOG_SHADE_GOURAUD (2 << 14) +# define RADEON_FOG_SHADE_MASK (3 << 14) +# define RADEON_ZBIAS_ENABLE_POINT (1 << 16) +# define RADEON_ZBIAS_ENABLE_LINE (1 << 17) +# define RADEON_ZBIAS_ENABLE_TRI (1 << 18) +# define RADEON_WIDELINE_ENABLE (1 << 20) +# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) +# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) +# define RADEON_VTX_PIX_CENTER_D3D (0 << 27) +# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) +# define RADEON_ROUND_MODE_TRUNC (0 << 28) +# define RADEON_ROUND_MODE_ROUND (1 << 28) +# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) +# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) +# define RADEON_ROUND_PREC_16TH_PIX (0 << 30) +# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) +# define RADEON_ROUND_PREC_4TH_PIX (2 << 30) +# define RADEON_ROUND_PREC_HALF_PIX (3 << 30) +#define RADEON_SE_CNTL_STATUS 0x2140 +# define RADEON_VC_NO_SWAP (0 << 0) +# define RADEON_VC_16BIT_SWAP (1 << 0) +# define RADEON_VC_32BIT_SWAP (2 << 0) +# define RADEON_VC_HALF_DWORD_SWAP (3 << 0) +# define RADEON_TCL_BYPASS (1 << 8) +#define RADEON_SE_COORD_FMT 0x1c50 +# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) +# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) +# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) +# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) +# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) +# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) +# define RADEON_VTX_W0_NORMALIZE (1 << 12) +# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) +# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) +# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) +# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) +# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) +# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) +# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) +#define RADEON_SE_LINE_WIDTH 0x1db8 +#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c +# define RADEON_LIGHTING_ENABLE (1 << 0) +# define RADEON_LIGHT_IN_MODELSPACE (1 << 1) +# define RADEON_LOCAL_VIEWER (1 << 2) +# define RADEON_NORMALIZE_NORMALS (1 << 3) +# define RADEON_RESCALE_NORMALS (1 << 4) +# define RADEON_SPECULAR_LIGHTS (1 << 5) +# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) +# define RADEON_LIGHT_ALPHA (1 << 7) +# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) +# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) +# define RADEON_LM_SOURCE_STATE_PREMULT 0 +# define RADEON_LM_SOURCE_STATE_MULT 1 +# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 +# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 +# define RADEON_EMISSIVE_SOURCE_SHIFT 16 +# define RADEON_AMBIENT_SOURCE_SHIFT 18 +# define RADEON_DIFFUSE_SOURCE_SHIFT 20 +# define RADEON_SPECULAR_SOURCE_SHIFT 22 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c +#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c +#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c +# define RADEON_MODELVIEW_0_SHIFT 0 +# define RADEON_MODELVIEW_1_SHIFT 4 +# define RADEON_MODELVIEW_2_SHIFT 8 +# define RADEON_MODELVIEW_3_SHIFT 12 +# define RADEON_IT_MODELVIEW_0_SHIFT 16 +# define RADEON_IT_MODELVIEW_1_SHIFT 20 +# define RADEON_IT_MODELVIEW_2_SHIFT 24 +# define RADEON_IT_MODELVIEW_3_SHIFT 28 +#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 +# define RADEON_MODELPROJECT_0_SHIFT 0 +# define RADEON_MODELPROJECT_1_SHIFT 4 +# define RADEON_MODELPROJECT_2_SHIFT 8 +# define RADEON_MODELPROJECT_3_SHIFT 12 +# define RADEON_TEXMAT_0_SHIFT 16 +# define RADEON_TEXMAT_1_SHIFT 20 +# define RADEON_TEXMAT_2_SHIFT 24 +# define RADEON_TEXMAT_3_SHIFT 28 + + +#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 +# define RADEON_TCL_VTX_W0 (1 << 0) +# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) +# define RADEON_TCL_VTX_FP_ALPHA (1 << 2) +# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) +# define RADEON_TCL_VTX_FP_SPEC (1 << 4) +# define RADEON_TCL_VTX_FP_FOG (1 << 5) +# define RADEON_TCL_VTX_PK_SPEC (1 << 6) +# define RADEON_TCL_VTX_ST0 (1 << 7) +# define RADEON_TCL_VTX_ST1 (1 << 8) +# define RADEON_TCL_VTX_Q1 (1 << 9) +# define RADEON_TCL_VTX_ST2 (1 << 10) +# define RADEON_TCL_VTX_Q2 (1 << 11) +# define RADEON_TCL_VTX_ST3 (1 << 12) +# define RADEON_TCL_VTX_Q3 (1 << 13) +# define RADEON_TCL_VTX_Q0 (1 << 14) +# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 +# define RADEON_TCL_VTX_NORM0 (1 << 18) +# define RADEON_TCL_VTX_XY1 (1 << 27) +# define RADEON_TCL_VTX_Z1 (1 << 28) +# define RADEON_TCL_VTX_W1 (1 << 29) +# define RADEON_TCL_VTX_NORM1 (1 << 30) +# define RADEON_TCL_VTX_Z0 (1 << 31) + +#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 +# define RADEON_TCL_COMPUTE_XYZW (1 << 0) +# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) +# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) +# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) +# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) +# define RADEON_TCL_TEX_INPUT_TEX_0 0 +# define RADEON_TCL_TEX_INPUT_TEX_1 1 +# define RADEON_TCL_TEX_INPUT_TEX_2 2 +# define RADEON_TCL_TEX_INPUT_TEX_3 3 +# define RADEON_TCL_TEX_COMPUTED_TEX_0 8 +# define RADEON_TCL_TEX_COMPUTED_TEX_1 9 +# define RADEON_TCL_TEX_COMPUTED_TEX_2 10 +# define RADEON_TCL_TEX_COMPUTED_TEX_3 11 +# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 +# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 +# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 +# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 + +#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 +# define RADEON_LIGHT_0_ENABLE (1 << 0) +# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) +# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) +# define RADEON_LIGHT_0_IS_LOCAL (1 << 3) +# define RADEON_LIGHT_0_IS_SPOT (1 << 4) +# define RADEON_LIGHT_0_DUAL_CONE (1 << 5) +# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) +# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) +# define RADEON_LIGHT_0_SHIFT 0 +# define RADEON_LIGHT_1_ENABLE (1 << 16) +# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) +# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) +# define RADEON_LIGHT_1_IS_LOCAL (1 << 19) +# define RADEON_LIGHT_1_IS_SPOT (1 << 20) +# define RADEON_LIGHT_1_DUAL_CONE (1 << 21) +# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) +# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) +# define RADEON_LIGHT_1_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 +# define RADEON_LIGHT_2_SHIFT 0 +# define RADEON_LIGHT_3_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 +# define RADEON_LIGHT_4_SHIFT 0 +# define RADEON_LIGHT_5_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c +# define RADEON_LIGHT_6_SHIFT 0 +# define RADEON_LIGHT_7_SHIFT 16 + +#define RADEON_SE_TCL_STATE_FLUSH 0x2284 + +#define RADEON_SE_TCL_SHININESS 0x2250 + +#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 +# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) +# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) +# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) +# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) +# define RADEON_TEXMAT_0_ENABLE (1 << 4) +# define RADEON_TEXMAT_1_ENABLE (1 << 5) +# define RADEON_TEXMAT_2_ENABLE (1 << 6) +# define RADEON_TEXMAT_3_ENABLE (1 << 7) +# define RADEON_TEXGEN_INPUT_MASK 0xf +# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 +# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 +# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 +# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 +# define RADEON_TEXGEN_INPUT_OBJ 4 +# define RADEON_TEXGEN_INPUT_EYE 5 +# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 +# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 +# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 +# define RADEON_TEXGEN_0_INPUT_SHIFT 16 +# define RADEON_TEXGEN_1_INPUT_SHIFT 20 +# define RADEON_TEXGEN_2_INPUT_SHIFT 24 +# define RADEON_TEXGEN_3_INPUT_SHIFT 28 + +#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 +# define RADEON_UCP_IN_CLIP_SPACE (1 << 0) +# define RADEON_UCP_IN_MODEL_SPACE (1 << 1) +# define RADEON_UCP_ENABLE_0 (1 << 2) +# define RADEON_UCP_ENABLE_1 (1 << 3) +# define RADEON_UCP_ENABLE_2 (1 << 4) +# define RADEON_UCP_ENABLE_3 (1 << 5) +# define RADEON_UCP_ENABLE_4 (1 << 6) +# define RADEON_UCP_ENABLE_5 (1 << 7) +# define RADEON_TCL_FOG_MASK (3 << 8) +# define RADEON_TCL_FOG_DISABLE (0 << 8) +# define RADEON_TCL_FOG_EXP (1 << 8) +# define RADEON_TCL_FOG_EXP2 (2 << 8) +# define RADEON_TCL_FOG_LINEAR (3 << 8) +# define RADEON_RNG_BASED_FOG (1 << 10) +# define RADEON_LIGHT_TWOSIDE (1 << 11) +# define RADEON_BLEND_OP_COUNT_MASK (7 << 12) +# define RADEON_BLEND_OP_COUNT_SHIFT 12 +# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) +# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) +# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (0 << 18) +# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) +# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (0 << 19) +# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) +# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (0 << 20) +# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) +# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (0 << 21) +# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) +# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) +# define RADEON_CULL_FRONT_IS_CW (0 << 28) +# define RADEON_CULL_FRONT_IS_CCW (1 << 28) +# define RADEON_CULL_FRONT (1 << 29) +# define RADEON_CULL_BACK (1 << 30) +# define RADEON_FORCE_W_TO_ONE (1 << 31) + +#define RADEON_SE_VPORT_XSCALE 0x1d98 +#define RADEON_SE_VPORT_XOFFSET 0x1d9c +#define RADEON_SE_VPORT_YSCALE 0x1da0 +#define RADEON_SE_VPORT_YOFFSET 0x1da4 +#define RADEON_SE_VPORT_ZSCALE 0x1da8 +#define RADEON_SE_VPORT_ZOFFSET 0x1dac +#define RADEON_SE_ZBIAS_FACTOR 0x1db0 +#define RADEON_SE_ZBIAS_CONSTANT 0x1db4 + + + + /* Registers for CP and Microcode Engine */ +#define RADEON_CP_ME_RAM_ADDR 0x07d4 +#define RADEON_CP_ME_RAM_RADDR 0x07d8 +#define RADEON_CP_ME_RAM_DATAH 0x07dc +#define RADEON_CP_ME_RAM_DATAL 0x07e0 + +#define RADEON_CP_RB_BASE 0x0700 +#define RADEON_CP_RB_CNTL 0x0704 +#define RADEON_CP_RB_RPTR_ADDR 0x070c +#define RADEON_CP_RB_RPTR 0x0710 +#define RADEON_CP_RB_WPTR 0x0714 + +#define RADEON_CP_IB_BASE 0x0738 +#define RADEON_CP_IB_BUFSZ 0x073c + +#define RADEON_CP_CSQ_CNTL 0x0740 +# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) +# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) +# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) +# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) +# define RADEON_CSQ_PRIBM_INDBM (4 << 28) +# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) +#define RADEON_CP_CSQ_STAT 0x07f8 +# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) +# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) +# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) +#define RADEON_CP_CSQ_ADDR 0x07f0 +#define RADEON_CP_CSQ_DATA 0x07f4 +#define RADEON_CP_CSQ_APER_PRIMARY 0x1000 +#define RADEON_CP_CSQ_APER_INDIRECT 0x1300 + +#define RADEON_CP_RB_WPTR_DELAY 0x0718 +# define RADEON_PRE_WRITE_TIMER_SHIFT 0 +# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 + +#define RADEON_AIC_CNTL 0x01d0 +# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) +#define RADEON_AIC_LO_ADDR 0x01dc + + + + /* Constants */ +#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 +#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 + + + + /* CP packet types */ +#define RADEON_CP_PACKET0 0x00000000 +#define RADEON_CP_PACKET1 0x40000000 +#define RADEON_CP_PACKET2 0x80000000 +#define RADEON_CP_PACKET3 0xC0000000 +# define RADEON_CP_PACKET_MASK 0xC0000000 +# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 +# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) +# define RADEON_CP_PACKET0_REG_MASK 0x000007ff +# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff +# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 + +#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 + +#define RADEON_CP_PACKET3_NOP 0xC0001000 +#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 +#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 +#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 +#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 +#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 +#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 +#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 +#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 +#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 +#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 +#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 +#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 +#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 +#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 +#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 +#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 +#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 +#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 +#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 + + +#define RADEON_CP_VC_FRMT_XY 0x00000000 +#define RADEON_CP_VC_FRMT_W0 0x00000001 +#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 +#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 +#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 +#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 +#define RADEON_CP_VC_FRMT_FPFOG 0x00000020 +#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 +#define RADEON_CP_VC_FRMT_ST0 0x00000080 +#define RADEON_CP_VC_FRMT_ST1 0x00000100 +#define RADEON_CP_VC_FRMT_Q1 0x00000200 +#define RADEON_CP_VC_FRMT_ST2 0x00000400 +#define RADEON_CP_VC_FRMT_Q2 0x00000800 +#define RADEON_CP_VC_FRMT_ST3 0x00001000 +#define RADEON_CP_VC_FRMT_Q3 0x00002000 +#define RADEON_CP_VC_FRMT_Q0 0x00004000 +#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 +#define RADEON_CP_VC_FRMT_N0 0x00040000 +#define RADEON_CP_VC_FRMT_XY1 0x08000000 +#define RADEON_CP_VC_FRMT_Z1 0x10000000 +#define RADEON_CP_VC_FRMT_W1 0x20000000 +#define RADEON_CP_VC_FRMT_N1 0x40000000 +#define RADEON_CP_VC_FRMT_Z 0x80000000 + +#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a +#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 +#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 +#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 +#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 +#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 +#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 +#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 +#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 +#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 + +#define RADEON_VS_MATRIX_0_ADDR 0 +#define RADEON_VS_MATRIX_1_ADDR 4 +#define RADEON_VS_MATRIX_2_ADDR 8 +#define RADEON_VS_MATRIX_3_ADDR 12 +#define RADEON_VS_MATRIX_4_ADDR 16 +#define RADEON_VS_MATRIX_5_ADDR 20 +#define RADEON_VS_MATRIX_6_ADDR 24 +#define RADEON_VS_MATRIX_7_ADDR 28 +#define RADEON_VS_MATRIX_8_ADDR 32 +#define RADEON_VS_MATRIX_9_ADDR 36 +#define RADEON_VS_MATRIX_10_ADDR 40 +#define RADEON_VS_MATRIX_11_ADDR 44 +#define RADEON_VS_MATRIX_12_ADDR 48 +#define RADEON_VS_MATRIX_13_ADDR 52 +#define RADEON_VS_MATRIX_14_ADDR 56 +#define RADEON_VS_MATRIX_15_ADDR 60 +#define RADEON_VS_LIGHT_AMBIENT_ADDR 64 +#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 +#define RADEON_VS_LIGHT_SPECULAR_ADDR 80 +#define RADEON_VS_LIGHT_DIRPOS_ADDR 88 +#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 +#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 +#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 +#define RADEON_VS_UCP_ADDR 116 +#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 +#define RADEON_VS_FOG_PARAM_ADDR 123 +#define RADEON_VS_EYE_VECTOR_ADDR 124 + +#define RADEON_SS_LIGHT_DCD_ADDR 0 +#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 +#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 +#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 +#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 +#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 +#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 +#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 +#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 +#define RADEON_SS_SHININESS 60 + +#define RADEON_TV_MASTER_CNTL 0x0800 +# define RADEON_TVCLK_ALWAYS_ONb (1 << 30) +#define RADEON_TV_DAC_CNTL 0x088c +# define RADEON_TV_DAC_CMPOUT (1 << 5) +#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 +# define RADEON_Y_RED_EN (1 << 0) +# define RADEON_C_GRN_EN (1 << 1) +# define RADEON_CMP_BLU_EN (1 << 2) +# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) +# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) +# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) +# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 +#endif diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/radeon/radeon_screen.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/radeon/radeon_screen.c index aa7fb633dd1..682cf3a5ee5 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/radeon/radeon_screen.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/radeon/radeon_screen.c @@ -53,6 +53,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "r200_context.h" #include "r200_ioctl.h" #include "r200_span.h" +#include "r200_tex.h" #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) #include "r300_context.h" #include "r300_fragprog.h" @@ -973,7 +974,8 @@ static const struct __DriverAPIRec r200API = { .WaitForMSC = driWaitForMSC32, .WaitForSBC = NULL, .SwapBuffersMSC = NULL, - .CopySubBuffer = r200CopySubBuffer + .CopySubBuffer = r200CopySubBuffer, + .setTexOffset = r200SetTexOffset }; #endif diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/unichrome/via_context.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/unichrome/via_context.c index 4d25d328e33..7c738777209 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/unichrome/via_context.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/unichrome/via_context.c @@ -733,14 +733,15 @@ void viaXMesaWindowMoved(struct via_context *vmesa) { __DRIdrawablePrivate *const drawable = vmesa->driDrawable; __DRIdrawablePrivate *const readable = vmesa->driReadable; - struct via_renderbuffer *const draw_buffer = - (struct via_renderbuffer *) drawable->driverPrivate; - struct via_renderbuffer *const read_buffer = - (struct via_renderbuffer *) readable->driverPrivate; + struct via_renderbuffer * draw_buffer; + struct via_renderbuffer * read_buffer; GLuint bytePerPixel = vmesa->viaScreen->bitsPerPixel >> 3; if (!drawable) return; + + draw_buffer = (struct via_renderbuffer *) drawable->driverPrivate; + read_buffer = (struct via_renderbuffer *) readable->driverPrivate; switch (vmesa->glCtx->DrawBuffer->_ColorDrawBufferMask[0]) { case BUFFER_BIT_BACK_LEFT: diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/dri/unichrome/via_tris.c b/reactos/dll/3rdparty/mesa32/src/drivers/dri/unichrome/via_tris.c index 4cc7942b1b6..b97dacde241 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/dri/unichrome/via_tris.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/dri/unichrome/via_tris.c @@ -625,13 +625,12 @@ static void viaFastRenderClippedPoly(GLcontext *ctx, const GLuint *elts, } } + /**********************************************************************/ /* Choose render functions */ /**********************************************************************/ - - #define _VIA_NEW_VERTEX (_NEW_TEXTURE | \ _DD_NEW_SEPARATE_SPECULAR | \ _DD_NEW_TRI_UNFILLED | \ @@ -665,14 +664,17 @@ static void viaChooseRenderState(GLcontext *ctx) vmesa->drawTri = via_draw_triangle; } - if (flags & (ANY_FALLBACK_FLAGS|ANY_RASTER_FLAGS)) { - if (flags & DD_TRI_LIGHT_TWOSIDE) index |= VIA_TWOSIDE_BIT; - if (flags & DD_TRI_OFFSET) index |= VIA_OFFSET_BIT; - if (flags & DD_TRI_UNFILLED) index |= VIA_UNFILLED_BIT; - if (flags & ANY_FALLBACK_FLAGS) index |= VIA_FALLBACK_BIT; + if (flags & (ANY_FALLBACK_FLAGS | ANY_RASTER_FLAGS)) { + if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) + index |= VIA_TWOSIDE_BIT; + if (ctx->Polygon.FrontMode != GL_FILL || ctx->Polygon.BackMode != GL_FILL) + index |= VIA_UNFILLED_BIT; + if (flags & DD_TRI_OFFSET) + index |= VIA_OFFSET_BIT; + if (flags & ANY_FALLBACK_FLAGS) + index |= VIA_FALLBACK_BIT; - /* Hook in fallbacks for specific primitives. - */ + /* Hook in fallbacks for specific primitives. */ if (flags & POINT_FALLBACK) vmesa->drawPoint = via_fallback_point; @@ -683,11 +685,8 @@ static void viaChooseRenderState(GLcontext *ctx) vmesa->drawTri = via_fallback_tri; } - - if ((flags & DD_SEPARATE_SPECULAR) && - ctx->Light.ShadeModel == GL_FLAT) { + if ((flags & DD_SEPARATE_SPECULAR) && ctx->Light.ShadeModel == GL_FLAT) index = VIA_MAX_TRIFUNC; /* flat specular */ - } if (vmesa->renderIndex != index) { vmesa->renderIndex = index; diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/windows/gdi/wmesa.c b/reactos/dll/3rdparty/mesa32/src/drivers/windows/gdi/wmesa.c index 5a197dd8728..e1d8c141079 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/windows/gdi/wmesa.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/windows/gdi/wmesa.c @@ -458,23 +458,84 @@ static void write_rgba_span_front(const GLcontext *ctx, const GLubyte rgba[][4], const GLubyte mask[] ) { - WMesaContext pwc = wmesa_context(ctx); - GLuint i; - - (void) ctx; - y=FLIP(y); - if (mask) { - for (i=0; ihDC, x+i, y, RGB(rgba[i][RCOMP], rgba[i][GCOMP], - rgba[i][BCOMP])); - } - else { - for (i=0; ihDC, x+i, y, RGB(rgba[i][RCOMP], rgba[i][GCOMP], - rgba[i][BCOMP])); - } - + WMesaContext pwc = wmesa_context(ctx); + WMesaFramebuffer pwfb = wmesa_lookup_framebuffer(pwc->hDC); + CONST BITMAPINFO bmi= + { + { + sizeof(BITMAPINFOHEADER), + n, 1, 1, 32, BI_RGB, 0, 1, 1, 0, 0 + } + }; + HBITMAP bmp=0; + HDC mdc=0; + typedef union + { + unsigned i; + struct { + unsigned b:8, g:8, r:8, a:8; + }; + } BGRA; + BGRA *bgra, c; + int i; + + if (n < 16) { // the value 16 is just guessed + y=FLIP(y); + if (mask) { + for (i=0; ihDC, x+i, y, + RGB(rgba[i][RCOMP], rgba[i][GCOMP], rgba[i][BCOMP])); + } + else { + for (i=0; ihDC, x+i, y, + RGB(rgba[i][RCOMP], rgba[i][GCOMP], rgba[i][BCOMP])); + } + } + else { + if (!pwfb) { + _mesa_problem(NULL, "wmesa: write_rgba_span_front on unknown hdc"); + return; + } + bgra=malloc(n*sizeof(BGRA)); + if (!bgra) { + _mesa_problem(NULL, "wmesa: write_rgba_span_front: out of memory"); + return; + } + c.a=0; + if (mask) { + for (i=0; ihDC); + SelectObject(mdc, bmp); + y=FLIP(y); + BitBlt(pwfb->hDC, x, y, n, 1, mdc, 0, 0, SRCCOPY); + SelectObject(mdc, 0); + DeleteObject(bmp); + DeleteDC(mdc); + free(bgra); + } } /* Write a horizontal span of RGB color pixels with a boolean mask. */ diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/windows/icd/mesa.def b/reactos/dll/3rdparty/mesa32/src/drivers/windows/icd/mesa.def index ed7de2ba4dc..34850b25615 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/windows/icd/mesa.def +++ b/reactos/dll/3rdparty/mesa32/src/drivers/windows/icd/mesa.def @@ -1,5 +1,5 @@ DESCRIPTION 'Mesa (OpenGL driver) for Win32' -VERSION 6.1 +VERSION 7.0 EXPORTS ; diff --git a/reactos/dll/3rdparty/mesa32/src/drivers/x11/xm_dd.c b/reactos/dll/3rdparty/mesa32/src/drivers/x11/xm_dd.c index c8546236fbf..4c8bf5f656d 100644 --- a/reactos/dll/3rdparty/mesa32/src/drivers/x11/xm_dd.c +++ b/reactos/dll/3rdparty/mesa32/src/drivers/x11/xm_dd.c @@ -159,7 +159,6 @@ index_mask( GLcontext *ctx, GLuint mask ) m = (unsigned long) mask; } XMesaSetPlaneMask( xmesa->display, xmbuf->cleargc, m ); - XMesaSetPlaneMask( xmesa->display, xmbuf->gc, m ); } } @@ -191,7 +190,6 @@ color_mask(GLcontext *ctx, if (bmask) m |= GET_BLUEMASK(xmesa->xm_visual); } XMesaSetPlaneMask( xmesa->display, xmbuf->cleargc, m ); - XMesaSetPlaneMask( xmesa->display, xmbuf->gc, m ); } } @@ -450,13 +448,13 @@ xmesa_DrawPixels_8R8G8B( GLcontext *ctx, ctx->_ImageTransferState == 0 && /* no color tables, scale/bias, etc */ ctx->Pixel.ZoomX == 1.0 && /* no zooming */ ctx->Pixel.ZoomY == 1.0 && - xrb->pixmap && + xrb->pixmap && /* drawing to pixmap or window */ xrb->Base.AlphaBits == 0) { const XMesaContext xmesa = XMESA_CONTEXT(ctx); XMesaBuffer xmbuf = XMESA_BUFFER(ctx->DrawBuffer); XMesaDisplay *dpy = xmesa->xm_visual->display; - const XMesaGC gc = xmbuf->gc; + const XMesaGC gc = xmbuf->cleargc; /* effected by glColorMask */ int dstX = x; int dstY = y; int w = width; @@ -551,7 +549,7 @@ xmesa_DrawPixels_5R6G5B( GLcontext *ctx, const SWcontext *swrast = SWRAST_CONTEXT( ctx ); XMesaDisplay *dpy = xmesa->xm_visual->display; XMesaBuffer xmbuf = XMESA_BUFFER(ctx->DrawBuffer); - const XMesaGC gc = xmbuf->gc; + const XMesaGC gc = xmbuf->cleargc; /* effected by glColorMask */ ASSERT(dpy); ASSERT(gc); @@ -560,7 +558,7 @@ xmesa_DrawPixels_5R6G5B( GLcontext *ctx, if (swrast->NewState) _swrast_validate_derived( ctx ); - if (xrb->pixmap && + if (xrb->pixmap && /* drawing to pixmap or window */ format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5 && !ctx->Color.DitherFlag && /* no dithering */ @@ -651,7 +649,8 @@ xmesa_CopyPixels( GLcontext *ctx, const XMesaContext xmesa = XMESA_CONTEXT(ctx); const SWcontext *swrast = SWRAST_CONTEXT( ctx ); XMesaDisplay *dpy = xmesa->xm_visual->display; - const XMesaGC gc = ((XMesaBuffer) ctx->DrawBuffer)->gc; + XMesaBuffer xmbuf = XMESA_BUFFER(ctx->DrawBuffer); + const XMesaGC gc = xmbuf->cleargc; /* effected by glColorMask */ struct xmesa_renderbuffer *srcXrb = xmesa_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer->Wrapped); struct xmesa_renderbuffer *dstXrb diff --git a/reactos/dll/3rdparty/mesa32/src/glapi/dispatch.h b/reactos/dll/3rdparty/mesa32/src/glapi/dispatch.h index a128164323a..d073f4a5ea9 100644 --- a/reactos/dll/3rdparty/mesa32/src/glapi/dispatch.h +++ b/reactos/dll/3rdparty/mesa32/src/glapi/dispatch.h @@ -2362,6 +2362,9 @@ #define CALL_BlitFramebufferEXT(disp, parameters) (*((disp)->BlitFramebufferEXT)) parameters #define GET_BlitFramebufferEXT(disp) ((disp)->BlitFramebufferEXT) #define SET_BlitFramebufferEXT(disp, fn) ((disp)->BlitFramebufferEXT = fn) +#define CALL_StencilFuncSeparateATI(disp, parameters) (*((disp)->StencilFuncSeparateATI)) parameters +#define GET_StencilFuncSeparateATI(disp) ((disp)->StencilFuncSeparateATI) +#define SET_StencilFuncSeparateATI(disp, fn) ((disp)->StencilFuncSeparateATI = fn) #define CALL_ProgramEnvParameters4fvEXT(disp, parameters) (*((disp)->ProgramEnvParameters4fvEXT)) parameters #define GET_ProgramEnvParameters4fvEXT(disp) ((disp)->ProgramEnvParameters4fvEXT) #define SET_ProgramEnvParameters4fvEXT(disp, fn) ((disp)->ProgramEnvParameters4fvEXT = fn) @@ -2377,7 +2380,7 @@ #else -#define driDispatchRemapTable_size 364 +#define driDispatchRemapTable_size 365 extern int driDispatchRemapTable[ driDispatchRemapTable_size ]; #define AttachShader_remap_index 0 @@ -2740,10 +2743,11 @@ extern int driDispatchRemapTable[ driDispatchRemapTable_size ]; #define IsRenderbufferEXT_remap_index 357 #define RenderbufferStorageEXT_remap_index 358 #define BlitFramebufferEXT_remap_index 359 -#define ProgramEnvParameters4fvEXT_remap_index 360 -#define ProgramLocalParameters4fvEXT_remap_index 361 -#define GetQueryObjecti64vEXT_remap_index 362 -#define GetQueryObjectui64vEXT_remap_index 363 +#define StencilFuncSeparateATI_remap_index 360 +#define ProgramEnvParameters4fvEXT_remap_index 361 +#define ProgramLocalParameters4fvEXT_remap_index 362 +#define GetQueryObjecti64vEXT_remap_index 363 +#define GetQueryObjectui64vEXT_remap_index 364 #define CALL_AttachShader(disp, parameters) CALL_by_offset(disp, (void (GLAPIENTRYP)(GLuint, GLuint)), driDispatchRemapTable[AttachShader_remap_index], parameters) #define GET_AttachShader(disp) GET_by_offset(disp, driDispatchRemapTable[AttachShader_remap_index]) @@ -3825,6 +3829,9 @@ extern int driDispatchRemapTable[ driDispatchRemapTable_size ]; #define CALL_BlitFramebufferEXT(disp, parameters) CALL_by_offset(disp, (void (GLAPIENTRYP)(GLint, GLint, GLint, GLint, GLint, GLint, GLint, GLint, GLbitfield, GLenum)), driDispatchRemapTable[BlitFramebufferEXT_remap_index], parameters) #define GET_BlitFramebufferEXT(disp) GET_by_offset(disp, driDispatchRemapTable[BlitFramebufferEXT_remap_index]) #define SET_BlitFramebufferEXT(disp, fn) SET_by_offset(disp, driDispatchRemapTable[BlitFramebufferEXT_remap_index], fn) +#define CALL_StencilFuncSeparateATI(disp, parameters) CALL_by_offset(disp, (void (GLAPIENTRYP)(GLenum, GLenum, GLint, GLuint)), driDispatchRemapTable[StencilFuncSeparateATI_remap_index], parameters) +#define GET_StencilFuncSeparateATI(disp) GET_by_offset(disp, driDispatchRemapTable[StencilFuncSeparateATI_remap_index]) +#define SET_StencilFuncSeparateATI(disp, fn) SET_by_offset(disp, driDispatchRemapTable[StencilFuncSeparateATI_remap_index], fn) #define CALL_ProgramEnvParameters4fvEXT(disp, parameters) CALL_by_offset(disp, (void (GLAPIENTRYP)(GLenum, GLuint, GLsizei, const GLfloat *)), driDispatchRemapTable[ProgramEnvParameters4fvEXT_remap_index], parameters) #define GET_ProgramEnvParameters4fvEXT(disp) GET_by_offset(disp, driDispatchRemapTable[ProgramEnvParameters4fvEXT_remap_index]) #define SET_ProgramEnvParameters4fvEXT(disp, fn) SET_by_offset(disp, driDispatchRemapTable[ProgramEnvParameters4fvEXT_remap_index], fn) diff --git a/reactos/dll/3rdparty/mesa32/src/glapi/glapi.c b/reactos/dll/3rdparty/mesa32/src/glapi/glapi.c index e938dc576d0..47c57822732 100644 --- a/reactos/dll/3rdparty/mesa32/src/glapi/glapi.c +++ b/reactos/dll/3rdparty/mesa32/src/glapi/glapi.c @@ -878,10 +878,10 @@ _glapi_get_proc_address(const char *funcName) #ifdef MANGLE if (funcName[0] != 'm' || funcName[1] != 'g' || funcName[2] != 'l') - return NULL; + return NULL; #else if (funcName[0] != 'g' || funcName[1] != 'l') - return NULL; + return NULL; #endif /* search extension functions first */ diff --git a/reactos/dll/3rdparty/mesa32/src/glapi/glapioffsets.h b/reactos/dll/3rdparty/mesa32/src/glapi/glapioffsets.h index cb0d21083ef..4c6dd98a6d9 100644 --- a/reactos/dll/3rdparty/mesa32/src/glapi/glapioffsets.h +++ b/reactos/dll/3rdparty/mesa32/src/glapi/glapioffsets.h @@ -800,11 +800,12 @@ #define _gloffset_IsRenderbufferEXT 765 #define _gloffset_RenderbufferStorageEXT 766 #define _gloffset_BlitFramebufferEXT 767 -#define _gloffset_ProgramEnvParameters4fvEXT 768 -#define _gloffset_ProgramLocalParameters4fvEXT 769 -#define _gloffset_GetQueryObjecti64vEXT 770 -#define _gloffset_GetQueryObjectui64vEXT 771 -#define _gloffset_FIRST_DYNAMIC 772 +#define _gloffset_StencilFuncSeparateATI 768 +#define _gloffset_ProgramEnvParameters4fvEXT 769 +#define _gloffset_ProgramLocalParameters4fvEXT 770 +#define _gloffset_GetQueryObjecti64vEXT 771 +#define _gloffset_GetQueryObjectui64vEXT 772 +#define _gloffset_FIRST_DYNAMIC 773 #else @@ -1168,6 +1169,7 @@ #define _gloffset_IsRenderbufferEXT driDispatchRemapTable[IsRenderbufferEXT_remap_index] #define _gloffset_RenderbufferStorageEXT driDispatchRemapTable[RenderbufferStorageEXT_remap_index] #define _gloffset_BlitFramebufferEXT driDispatchRemapTable[BlitFramebufferEXT_remap_index] +#define _gloffset_StencilFuncSeparateATI driDispatchRemapTable[StencilFuncSeparateATI_remap_index] #define _gloffset_ProgramEnvParameters4fvEXT driDispatchRemapTable[ProgramEnvParameters4fvEXT_remap_index] #define _gloffset_ProgramLocalParameters4fvEXT driDispatchRemapTable[ProgramLocalParameters4fvEXT_remap_index] #define _gloffset_GetQueryObjecti64vEXT driDispatchRemapTable[GetQueryObjecti64vEXT_remap_index] diff --git a/reactos/dll/3rdparty/mesa32/src/glapi/glapitable.h b/reactos/dll/3rdparty/mesa32/src/glapi/glapitable.h index 4af0c2d43b8..a66f6f386e6 100644 --- a/reactos/dll/3rdparty/mesa32/src/glapi/glapitable.h +++ b/reactos/dll/3rdparty/mesa32/src/glapi/glapitable.h @@ -464,7 +464,7 @@ struct _glapi_table GLboolean (GLAPIENTRYP IsShader)(GLuint shader); /* 420 */ void (GLAPIENTRYP StencilFuncSeparate)(GLenum face, GLenum func, GLint ref, GLuint mask); /* 421 */ void (GLAPIENTRYP StencilMaskSeparate)(GLenum face, GLuint mask); /* 422 */ - void (GLAPIENTRYP StencilOpSeparate)(GLenum face, GLenum fail, GLenum zfail, GLenum zpass); /* 423 */ + void (GLAPIENTRYP StencilOpSeparate)(GLenum face, GLenum sfail, GLenum zfail, GLenum zpass); /* 423 */ void (GLAPIENTRYP UniformMatrix2x3fv)(GLint location, GLsizei count, GLboolean transpose, const GLfloat * value); /* 424 */ void (GLAPIENTRYP UniformMatrix2x4fv)(GLint location, GLsizei count, GLboolean transpose, const GLfloat * value); /* 425 */ void (GLAPIENTRYP UniformMatrix3x2fv)(GLint location, GLsizei count, GLboolean transpose, const GLfloat * value); /* 426 */ @@ -809,10 +809,11 @@ struct _glapi_table GLboolean (GLAPIENTRYP IsRenderbufferEXT)(GLuint renderbuffer); /* 765 */ void (GLAPIENTRYP RenderbufferStorageEXT)(GLenum target, GLenum internalformat, GLsizei width, GLsizei height); /* 766 */ void (GLAPIENTRYP BlitFramebufferEXT)(GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, GLbitfield mask, GLenum filter); /* 767 */ - void (GLAPIENTRYP ProgramEnvParameters4fvEXT)(GLenum target, GLuint index, GLsizei count, const GLfloat * params); /* 768 */ - void (GLAPIENTRYP ProgramLocalParameters4fvEXT)(GLenum target, GLuint index, GLsizei count, const GLfloat * params); /* 769 */ - void (GLAPIENTRYP GetQueryObjecti64vEXT)(GLuint id, GLenum pname, GLint64EXT * params); /* 770 */ - void (GLAPIENTRYP GetQueryObjectui64vEXT)(GLuint id, GLenum pname, GLuint64EXT * params); /* 771 */ + void (GLAPIENTRYP StencilFuncSeparateATI)(GLenum frontfunc, GLenum backfunc, GLint ref, GLuint mask); /* 768 */ + void (GLAPIENTRYP ProgramEnvParameters4fvEXT)(GLenum target, GLuint index, GLsizei count, const GLfloat * params); /* 769 */ + void (GLAPIENTRYP ProgramLocalParameters4fvEXT)(GLenum target, GLuint index, GLsizei count, const GLfloat * params); /* 770 */ + void (GLAPIENTRYP GetQueryObjecti64vEXT)(GLuint id, GLenum pname, GLint64EXT * params); /* 771 */ + void (GLAPIENTRYP GetQueryObjectui64vEXT)(GLuint id, GLenum pname, GLuint64EXT * params); /* 772 */ }; #endif /* !defined( _GLAPI_TABLE_H_ ) */ diff --git a/reactos/dll/3rdparty/mesa32/src/glapi/glapitemp.h b/reactos/dll/3rdparty/mesa32/src/glapi/glapitemp.h index 2a8051ff0a9..1a979cf01c1 100644 --- a/reactos/dll/3rdparty/mesa32/src/glapi/glapitemp.h +++ b/reactos/dll/3rdparty/mesa32/src/glapi/glapitemp.h @@ -2754,9 +2754,16 @@ KEYWORD1 void KEYWORD2 NAME(StencilMaskSeparate)(GLenum face, GLuint mask) DISPATCH(StencilMaskSeparate, (face, mask), (F, "glStencilMaskSeparate(0x%x, %d);\n", face, mask)); } -KEYWORD1 void KEYWORD2 NAME(StencilOpSeparate)(GLenum face, GLenum fail, GLenum zfail, GLenum zpass) +KEYWORD1 void KEYWORD2 NAME(StencilOpSeparate)(GLenum face, GLenum sfail, GLenum zfail, GLenum zpass) { - DISPATCH(StencilOpSeparate, (face, fail, zfail, zpass), (F, "glStencilOpSeparate(0x%x, 0x%x, 0x%x, 0x%x);\n", face, fail, zfail, zpass)); + DISPATCH(StencilOpSeparate, (face, sfail, zfail, zpass), (F, "glStencilOpSeparate(0x%x, 0x%x, 0x%x, 0x%x);\n", face, sfail, zfail, zpass)); +} + +KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_423)(GLenum face, GLenum sfail, GLenum zfail, GLenum zpass); + +KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_423)(GLenum face, GLenum sfail, GLenum zfail, GLenum zpass) +{ + DISPATCH(StencilOpSeparate, (face, sfail, zfail, zpass), (F, "glStencilOpSeparateATI(0x%x, 0x%x, 0x%x, 0x%x);\n", face, sfail, zfail, zpass)); } KEYWORD1 void KEYWORD2 NAME(UniformMatrix2x3fv)(GLint location, GLsizei count, GLboolean transpose, const GLfloat * value) @@ -5441,30 +5448,37 @@ KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_767)(GLint srcX0, GLint srcY0, GL DISPATCH(BlitFramebufferEXT, (srcX0, srcY0, srcX1, srcY1, dstX0, dstY0, dstX1, dstY1, mask, filter), (F, "glBlitFramebufferEXT(%d, %d, %d, %d, %d, %d, %d, %d, %d, 0x%x);\n", srcX0, srcY0, srcX1, srcY1, dstX0, dstY0, dstX1, dstY1, mask, filter)); } -KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_768)(GLenum target, GLuint index, GLsizei count, const GLfloat * params); +KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_768)(GLenum frontfunc, GLenum backfunc, GLint ref, GLuint mask); -KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_768)(GLenum target, GLuint index, GLsizei count, const GLfloat * params) +KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_768)(GLenum frontfunc, GLenum backfunc, GLint ref, GLuint mask) { - DISPATCH(ProgramEnvParameters4fvEXT, (target, index, count, params), (F, "glProgramEnvParameters4fvEXT(0x%x, %d, %d, %p);\n", target, index, count, (const void *) params)); + DISPATCH(StencilFuncSeparateATI, (frontfunc, backfunc, ref, mask), (F, "glStencilFuncSeparateATI(0x%x, 0x%x, %d, %d);\n", frontfunc, backfunc, ref, mask)); } KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_769)(GLenum target, GLuint index, GLsizei count, const GLfloat * params); KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_769)(GLenum target, GLuint index, GLsizei count, const GLfloat * params) +{ + DISPATCH(ProgramEnvParameters4fvEXT, (target, index, count, params), (F, "glProgramEnvParameters4fvEXT(0x%x, %d, %d, %p);\n", target, index, count, (const void *) params)); +} + +KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_770)(GLenum target, GLuint index, GLsizei count, const GLfloat * params); + +KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_770)(GLenum target, GLuint index, GLsizei count, const GLfloat * params) { DISPATCH(ProgramLocalParameters4fvEXT, (target, index, count, params), (F, "glProgramLocalParameters4fvEXT(0x%x, %d, %d, %p);\n", target, index, count, (const void *) params)); } -KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_770)(GLuint id, GLenum pname, GLint64EXT * params); +KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_771)(GLuint id, GLenum pname, GLint64EXT * params); -KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_770)(GLuint id, GLenum pname, GLint64EXT * params) +KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_771)(GLuint id, GLenum pname, GLint64EXT * params) { DISPATCH(GetQueryObjecti64vEXT, (id, pname, params), (F, "glGetQueryObjecti64vEXT(%d, 0x%x, %p);\n", id, pname, (const void *) params)); } -KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_771)(GLuint id, GLenum pname, GLuint64EXT * params); +KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_772)(GLuint id, GLenum pname, GLuint64EXT * params); -KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_771)(GLuint id, GLenum pname, GLuint64EXT * params) +KEYWORD1_ALT void KEYWORD2 NAME(_dispatch_stub_772)(GLuint id, GLenum pname, GLuint64EXT * params) { DISPATCH(GetQueryObjectui64vEXT, (id, pname, params), (F, "glGetQueryObjectui64vEXT(%d, 0x%x, %p);\n", id, pname, (const void *) params)); } @@ -6255,6 +6269,7 @@ static _glapi_proc DISPATCH_TABLE_NAME[] = { TABLE_ENTRY(_dispatch_stub_769), TABLE_ENTRY(_dispatch_stub_770), TABLE_ENTRY(_dispatch_stub_771), + TABLE_ENTRY(_dispatch_stub_772), /* A whole bunch of no-op functions. These might be called * when someone tries to call a dynamically-registered * extension function without a current rendering context. diff --git a/reactos/dll/3rdparty/mesa32/src/glapi/glprocs.h b/reactos/dll/3rdparty/mesa32/src/glapi/glprocs.h index 99120bcb687..bc0dc4f9a6c 100644 --- a/reactos/dll/3rdparty/mesa32/src/glapi/glprocs.h +++ b/reactos/dll/3rdparty/mesa32/src/glapi/glprocs.h @@ -820,6 +820,7 @@ static const char gl_string_table[] = "glIsRenderbufferEXT\0" "glRenderbufferStorageEXT\0" "glBlitFramebufferEXT\0" + "glStencilFuncSeparateATI\0" "glProgramEnvParameters4fvEXT\0" "glProgramLocalParameters4fvEXT\0" "glGetQueryObjecti64vEXT\0" @@ -915,6 +916,7 @@ static const char gl_string_table[] = "glMultiTexCoord4iv\0" "glMultiTexCoord4s\0" "glMultiTexCoord4sv\0" + "glStencilOpSeparateATI\0" "glLoadTransposeMatrixd\0" "glLoadTransposeMatrixf\0" "glMultTransposeMatrixd\0" @@ -1147,6 +1149,7 @@ static const char gl_string_table[] = #define gl_dispatch_stub_769 mgl_dispatch_stub_769 #define gl_dispatch_stub_770 mgl_dispatch_stub_770 #define gl_dispatch_stub_771 mgl_dispatch_stub_771 +#define gl_dispatch_stub_772 mgl_dispatch_stub_772 #endif /* USE_MGL_NAMESPACE */ @@ -1197,6 +1200,7 @@ extern void gl_dispatch_stub_768(void); extern void gl_dispatch_stub_769(void); extern void gl_dispatch_stub_770(void); extern void gl_dispatch_stub_771(void); +extern void gl_dispatch_stub_772(void); #endif /* defined(NEED_FUNCTION_POINTER) || defined(GLX_INDIRECT_RENDERING) */ static const glprocs_table_t static_functions[] = { @@ -1968,284 +1972,286 @@ static const glprocs_table_t static_functions[] = { NAME_FUNC_OFFSET(13404, glIsRenderbufferEXT, glIsRenderbufferEXT, NULL, _gloffset_IsRenderbufferEXT), NAME_FUNC_OFFSET(13424, glRenderbufferStorageEXT, glRenderbufferStorageEXT, NULL, _gloffset_RenderbufferStorageEXT), NAME_FUNC_OFFSET(13449, gl_dispatch_stub_767, gl_dispatch_stub_767, NULL, _gloffset_BlitFramebufferEXT), - NAME_FUNC_OFFSET(13470, gl_dispatch_stub_768, gl_dispatch_stub_768, NULL, _gloffset_ProgramEnvParameters4fvEXT), - NAME_FUNC_OFFSET(13499, gl_dispatch_stub_769, gl_dispatch_stub_769, NULL, _gloffset_ProgramLocalParameters4fvEXT), - NAME_FUNC_OFFSET(13530, gl_dispatch_stub_770, gl_dispatch_stub_770, NULL, _gloffset_GetQueryObjecti64vEXT), - NAME_FUNC_OFFSET(13554, gl_dispatch_stub_771, gl_dispatch_stub_771, NULL, _gloffset_GetQueryObjectui64vEXT), - NAME_FUNC_OFFSET(13579, glArrayElement, glArrayElement, NULL, _gloffset_ArrayElement), - NAME_FUNC_OFFSET(13597, glBindTexture, glBindTexture, NULL, _gloffset_BindTexture), - NAME_FUNC_OFFSET(13614, glDrawArrays, glDrawArrays, NULL, _gloffset_DrawArrays), - NAME_FUNC_OFFSET(13630, glAreTexturesResident, glAreTexturesResidentEXT, glAreTexturesResidentEXT, _gloffset_AreTexturesResident), - NAME_FUNC_OFFSET(13655, glCopyTexImage1D, glCopyTexImage1D, NULL, _gloffset_CopyTexImage1D), - NAME_FUNC_OFFSET(13675, glCopyTexImage2D, glCopyTexImage2D, NULL, _gloffset_CopyTexImage2D), - NAME_FUNC_OFFSET(13695, glCopyTexSubImage1D, glCopyTexSubImage1D, NULL, _gloffset_CopyTexSubImage1D), - NAME_FUNC_OFFSET(13718, glCopyTexSubImage2D, glCopyTexSubImage2D, NULL, _gloffset_CopyTexSubImage2D), - NAME_FUNC_OFFSET(13741, glDeleteTextures, glDeleteTexturesEXT, glDeleteTexturesEXT, _gloffset_DeleteTextures), - NAME_FUNC_OFFSET(13761, glGenTextures, glGenTexturesEXT, glGenTexturesEXT, _gloffset_GenTextures), - NAME_FUNC_OFFSET(13778, glGetPointerv, glGetPointerv, NULL, _gloffset_GetPointerv), - NAME_FUNC_OFFSET(13795, glIsTexture, glIsTextureEXT, glIsTextureEXT, _gloffset_IsTexture), - NAME_FUNC_OFFSET(13810, glPrioritizeTextures, glPrioritizeTextures, NULL, _gloffset_PrioritizeTextures), - NAME_FUNC_OFFSET(13834, glTexSubImage1D, glTexSubImage1D, NULL, _gloffset_TexSubImage1D), - NAME_FUNC_OFFSET(13853, glTexSubImage2D, glTexSubImage2D, NULL, _gloffset_TexSubImage2D), - NAME_FUNC_OFFSET(13872, glBlendColor, glBlendColor, NULL, _gloffset_BlendColor), - NAME_FUNC_OFFSET(13888, glBlendEquation, glBlendEquation, NULL, _gloffset_BlendEquation), - NAME_FUNC_OFFSET(13907, glDrawRangeElements, glDrawRangeElements, NULL, _gloffset_DrawRangeElements), - NAME_FUNC_OFFSET(13930, glColorTable, glColorTable, NULL, _gloffset_ColorTable), - NAME_FUNC_OFFSET(13946, glColorTable, glColorTable, NULL, _gloffset_ColorTable), - NAME_FUNC_OFFSET(13962, glColorTableParameterfv, glColorTableParameterfv, NULL, _gloffset_ColorTableParameterfv), - NAME_FUNC_OFFSET(13989, glColorTableParameteriv, glColorTableParameteriv, NULL, _gloffset_ColorTableParameteriv), - NAME_FUNC_OFFSET(14016, glCopyColorTable, glCopyColorTable, NULL, _gloffset_CopyColorTable), - NAME_FUNC_OFFSET(14036, glGetColorTable, glGetColorTableEXT, glGetColorTableEXT, _gloffset_GetColorTable), - NAME_FUNC_OFFSET(14055, glGetColorTable, glGetColorTableEXT, glGetColorTableEXT, _gloffset_GetColorTable), - NAME_FUNC_OFFSET(14074, glGetColorTableParameterfv, glGetColorTableParameterfvEXT, glGetColorTableParameterfvEXT, _gloffset_GetColorTableParameterfv), - NAME_FUNC_OFFSET(14104, glGetColorTableParameterfv, glGetColorTableParameterfvEXT, glGetColorTableParameterfvEXT, _gloffset_GetColorTableParameterfv), - NAME_FUNC_OFFSET(14134, glGetColorTableParameteriv, glGetColorTableParameterivEXT, glGetColorTableParameterivEXT, _gloffset_GetColorTableParameteriv), - NAME_FUNC_OFFSET(14164, glGetColorTableParameteriv, glGetColorTableParameterivEXT, glGetColorTableParameterivEXT, _gloffset_GetColorTableParameteriv), - NAME_FUNC_OFFSET(14194, glColorSubTable, glColorSubTable, NULL, _gloffset_ColorSubTable), - NAME_FUNC_OFFSET(14213, glCopyColorSubTable, glCopyColorSubTable, NULL, _gloffset_CopyColorSubTable), - NAME_FUNC_OFFSET(14236, glConvolutionFilter1D, glConvolutionFilter1D, NULL, _gloffset_ConvolutionFilter1D), - NAME_FUNC_OFFSET(14261, glConvolutionFilter2D, glConvolutionFilter2D, NULL, _gloffset_ConvolutionFilter2D), - NAME_FUNC_OFFSET(14286, glConvolutionParameterf, glConvolutionParameterf, NULL, _gloffset_ConvolutionParameterf), - NAME_FUNC_OFFSET(14313, glConvolutionParameterfv, glConvolutionParameterfv, NULL, _gloffset_ConvolutionParameterfv), - NAME_FUNC_OFFSET(14341, glConvolutionParameteri, glConvolutionParameteri, NULL, _gloffset_ConvolutionParameteri), - NAME_FUNC_OFFSET(14368, glConvolutionParameteriv, glConvolutionParameteriv, NULL, _gloffset_ConvolutionParameteriv), - NAME_FUNC_OFFSET(14396, glCopyConvolutionFilter1D, glCopyConvolutionFilter1D, NULL, _gloffset_CopyConvolutionFilter1D), - NAME_FUNC_OFFSET(14425, glCopyConvolutionFilter2D, glCopyConvolutionFilter2D, NULL, _gloffset_CopyConvolutionFilter2D), - NAME_FUNC_OFFSET(14454, glGetConvolutionFilter, gl_dispatch_stub_356, gl_dispatch_stub_356, _gloffset_GetConvolutionFilter), - NAME_FUNC_OFFSET(14480, glGetConvolutionParameterfv, gl_dispatch_stub_357, gl_dispatch_stub_357, _gloffset_GetConvolutionParameterfv), - NAME_FUNC_OFFSET(14511, glGetConvolutionParameteriv, gl_dispatch_stub_358, gl_dispatch_stub_358, _gloffset_GetConvolutionParameteriv), - NAME_FUNC_OFFSET(14542, glGetSeparableFilter, gl_dispatch_stub_359, gl_dispatch_stub_359, _gloffset_GetSeparableFilter), - NAME_FUNC_OFFSET(14566, glSeparableFilter2D, glSeparableFilter2D, NULL, _gloffset_SeparableFilter2D), - NAME_FUNC_OFFSET(14589, glGetHistogram, gl_dispatch_stub_361, gl_dispatch_stub_361, _gloffset_GetHistogram), - NAME_FUNC_OFFSET(14607, glGetHistogramParameterfv, gl_dispatch_stub_362, gl_dispatch_stub_362, _gloffset_GetHistogramParameterfv), - NAME_FUNC_OFFSET(14636, glGetHistogramParameteriv, gl_dispatch_stub_363, gl_dispatch_stub_363, _gloffset_GetHistogramParameteriv), - NAME_FUNC_OFFSET(14665, glGetMinmax, gl_dispatch_stub_364, gl_dispatch_stub_364, _gloffset_GetMinmax), - NAME_FUNC_OFFSET(14680, glGetMinmaxParameterfv, gl_dispatch_stub_365, gl_dispatch_stub_365, _gloffset_GetMinmaxParameterfv), - NAME_FUNC_OFFSET(14706, glGetMinmaxParameteriv, gl_dispatch_stub_366, gl_dispatch_stub_366, _gloffset_GetMinmaxParameteriv), - NAME_FUNC_OFFSET(14732, glHistogram, glHistogram, NULL, _gloffset_Histogram), - NAME_FUNC_OFFSET(14747, glMinmax, glMinmax, NULL, _gloffset_Minmax), - NAME_FUNC_OFFSET(14759, glResetHistogram, glResetHistogram, NULL, _gloffset_ResetHistogram), - NAME_FUNC_OFFSET(14779, glResetMinmax, glResetMinmax, NULL, _gloffset_ResetMinmax), - NAME_FUNC_OFFSET(14796, glTexImage3D, glTexImage3D, NULL, _gloffset_TexImage3D), - NAME_FUNC_OFFSET(14812, glTexSubImage3D, glTexSubImage3D, NULL, _gloffset_TexSubImage3D), - NAME_FUNC_OFFSET(14831, glCopyTexSubImage3D, glCopyTexSubImage3D, NULL, _gloffset_CopyTexSubImage3D), - NAME_FUNC_OFFSET(14854, glActiveTextureARB, glActiveTextureARB, NULL, _gloffset_ActiveTextureARB), - NAME_FUNC_OFFSET(14870, glClientActiveTextureARB, glClientActiveTextureARB, NULL, _gloffset_ClientActiveTextureARB), - NAME_FUNC_OFFSET(14892, glMultiTexCoord1dARB, glMultiTexCoord1dARB, NULL, _gloffset_MultiTexCoord1dARB), - NAME_FUNC_OFFSET(14910, glMultiTexCoord1dvARB, glMultiTexCoord1dvARB, NULL, _gloffset_MultiTexCoord1dvARB), - NAME_FUNC_OFFSET(14929, glMultiTexCoord1fARB, glMultiTexCoord1fARB, NULL, _gloffset_MultiTexCoord1fARB), - NAME_FUNC_OFFSET(14947, glMultiTexCoord1fvARB, glMultiTexCoord1fvARB, NULL, _gloffset_MultiTexCoord1fvARB), - NAME_FUNC_OFFSET(14966, glMultiTexCoord1iARB, glMultiTexCoord1iARB, NULL, _gloffset_MultiTexCoord1iARB), - NAME_FUNC_OFFSET(14984, glMultiTexCoord1ivARB, glMultiTexCoord1ivARB, NULL, _gloffset_MultiTexCoord1ivARB), - NAME_FUNC_OFFSET(15003, glMultiTexCoord1sARB, glMultiTexCoord1sARB, NULL, _gloffset_MultiTexCoord1sARB), - NAME_FUNC_OFFSET(15021, glMultiTexCoord1svARB, glMultiTexCoord1svARB, NULL, _gloffset_MultiTexCoord1svARB), - NAME_FUNC_OFFSET(15040, glMultiTexCoord2dARB, glMultiTexCoord2dARB, NULL, _gloffset_MultiTexCoord2dARB), - NAME_FUNC_OFFSET(15058, glMultiTexCoord2dvARB, glMultiTexCoord2dvARB, NULL, _gloffset_MultiTexCoord2dvARB), - NAME_FUNC_OFFSET(15077, glMultiTexCoord2fARB, glMultiTexCoord2fARB, NULL, _gloffset_MultiTexCoord2fARB), - NAME_FUNC_OFFSET(15095, glMultiTexCoord2fvARB, glMultiTexCoord2fvARB, NULL, _gloffset_MultiTexCoord2fvARB), - NAME_FUNC_OFFSET(15114, glMultiTexCoord2iARB, glMultiTexCoord2iARB, NULL, _gloffset_MultiTexCoord2iARB), - NAME_FUNC_OFFSET(15132, glMultiTexCoord2ivARB, glMultiTexCoord2ivARB, NULL, _gloffset_MultiTexCoord2ivARB), - NAME_FUNC_OFFSET(15151, glMultiTexCoord2sARB, glMultiTexCoord2sARB, NULL, _gloffset_MultiTexCoord2sARB), - NAME_FUNC_OFFSET(15169, glMultiTexCoord2svARB, glMultiTexCoord2svARB, NULL, _gloffset_MultiTexCoord2svARB), - NAME_FUNC_OFFSET(15188, glMultiTexCoord3dARB, glMultiTexCoord3dARB, NULL, _gloffset_MultiTexCoord3dARB), - NAME_FUNC_OFFSET(15206, glMultiTexCoord3dvARB, glMultiTexCoord3dvARB, NULL, _gloffset_MultiTexCoord3dvARB), - NAME_FUNC_OFFSET(15225, glMultiTexCoord3fARB, glMultiTexCoord3fARB, NULL, _gloffset_MultiTexCoord3fARB), - NAME_FUNC_OFFSET(15243, glMultiTexCoord3fvARB, glMultiTexCoord3fvARB, NULL, _gloffset_MultiTexCoord3fvARB), - NAME_FUNC_OFFSET(15262, glMultiTexCoord3iARB, glMultiTexCoord3iARB, NULL, _gloffset_MultiTexCoord3iARB), - NAME_FUNC_OFFSET(15280, glMultiTexCoord3ivARB, glMultiTexCoord3ivARB, NULL, _gloffset_MultiTexCoord3ivARB), - NAME_FUNC_OFFSET(15299, glMultiTexCoord3sARB, glMultiTexCoord3sARB, NULL, _gloffset_MultiTexCoord3sARB), - NAME_FUNC_OFFSET(15317, glMultiTexCoord3svARB, glMultiTexCoord3svARB, NULL, _gloffset_MultiTexCoord3svARB), - NAME_FUNC_OFFSET(15336, glMultiTexCoord4dARB, glMultiTexCoord4dARB, NULL, _gloffset_MultiTexCoord4dARB), - NAME_FUNC_OFFSET(15354, glMultiTexCoord4dvARB, glMultiTexCoord4dvARB, NULL, _gloffset_MultiTexCoord4dvARB), - NAME_FUNC_OFFSET(15373, glMultiTexCoord4fARB, glMultiTexCoord4fARB, NULL, _gloffset_MultiTexCoord4fARB), - NAME_FUNC_OFFSET(15391, glMultiTexCoord4fvARB, glMultiTexCoord4fvARB, NULL, _gloffset_MultiTexCoord4fvARB), - NAME_FUNC_OFFSET(15410, glMultiTexCoord4iARB, glMultiTexCoord4iARB, NULL, _gloffset_MultiTexCoord4iARB), - NAME_FUNC_OFFSET(15428, glMultiTexCoord4ivARB, glMultiTexCoord4ivARB, NULL, _gloffset_MultiTexCoord4ivARB), - NAME_FUNC_OFFSET(15447, glMultiTexCoord4sARB, glMultiTexCoord4sARB, NULL, _gloffset_MultiTexCoord4sARB), - NAME_FUNC_OFFSET(15465, glMultiTexCoord4svARB, glMultiTexCoord4svARB, NULL, _gloffset_MultiTexCoord4svARB), - NAME_FUNC_OFFSET(15484, glLoadTransposeMatrixdARB, glLoadTransposeMatrixdARB, NULL, _gloffset_LoadTransposeMatrixdARB), - NAME_FUNC_OFFSET(15507, glLoadTransposeMatrixfARB, glLoadTransposeMatrixfARB, NULL, _gloffset_LoadTransposeMatrixfARB), - NAME_FUNC_OFFSET(15530, glMultTransposeMatrixdARB, glMultTransposeMatrixdARB, NULL, _gloffset_MultTransposeMatrixdARB), - NAME_FUNC_OFFSET(15553, glMultTransposeMatrixfARB, glMultTransposeMatrixfARB, NULL, _gloffset_MultTransposeMatrixfARB), - NAME_FUNC_OFFSET(15576, glSampleCoverageARB, glSampleCoverageARB, NULL, _gloffset_SampleCoverageARB), - NAME_FUNC_OFFSET(15593, glCompressedTexImage1DARB, glCompressedTexImage1DARB, NULL, _gloffset_CompressedTexImage1DARB), - NAME_FUNC_OFFSET(15616, glCompressedTexImage2DARB, glCompressedTexImage2DARB, NULL, _gloffset_CompressedTexImage2DARB), - NAME_FUNC_OFFSET(15639, glCompressedTexImage3DARB, glCompressedTexImage3DARB, NULL, _gloffset_CompressedTexImage3DARB), - NAME_FUNC_OFFSET(15662, glCompressedTexSubImage1DARB, glCompressedTexSubImage1DARB, NULL, _gloffset_CompressedTexSubImage1DARB), - NAME_FUNC_OFFSET(15688, glCompressedTexSubImage2DARB, glCompressedTexSubImage2DARB, NULL, _gloffset_CompressedTexSubImage2DARB), - NAME_FUNC_OFFSET(15714, glCompressedTexSubImage3DARB, glCompressedTexSubImage3DARB, NULL, _gloffset_CompressedTexSubImage3DARB), - NAME_FUNC_OFFSET(15740, glGetCompressedTexImageARB, glGetCompressedTexImageARB, NULL, _gloffset_GetCompressedTexImageARB), - NAME_FUNC_OFFSET(15764, glDisableVertexAttribArrayARB, glDisableVertexAttribArrayARB, NULL, _gloffset_DisableVertexAttribArrayARB), - NAME_FUNC_OFFSET(15791, glEnableVertexAttribArrayARB, glEnableVertexAttribArrayARB, NULL, _gloffset_EnableVertexAttribArrayARB), - NAME_FUNC_OFFSET(15817, glGetVertexAttribdvARB, glGetVertexAttribdvARB, NULL, _gloffset_GetVertexAttribdvARB), - NAME_FUNC_OFFSET(15837, glGetVertexAttribfvARB, glGetVertexAttribfvARB, NULL, _gloffset_GetVertexAttribfvARB), - NAME_FUNC_OFFSET(15857, glGetVertexAttribivARB, glGetVertexAttribivARB, NULL, _gloffset_GetVertexAttribivARB), - NAME_FUNC_OFFSET(15877, glVertexAttrib1dARB, glVertexAttrib1dARB, NULL, _gloffset_VertexAttrib1dARB), - NAME_FUNC_OFFSET(15894, glVertexAttrib1dvARB, glVertexAttrib1dvARB, NULL, _gloffset_VertexAttrib1dvARB), - NAME_FUNC_OFFSET(15912, glVertexAttrib1fARB, glVertexAttrib1fARB, NULL, _gloffset_VertexAttrib1fARB), - NAME_FUNC_OFFSET(15929, glVertexAttrib1fvARB, glVertexAttrib1fvARB, NULL, _gloffset_VertexAttrib1fvARB), - NAME_FUNC_OFFSET(15947, glVertexAttrib1sARB, glVertexAttrib1sARB, NULL, _gloffset_VertexAttrib1sARB), - NAME_FUNC_OFFSET(15964, glVertexAttrib1svARB, glVertexAttrib1svARB, NULL, _gloffset_VertexAttrib1svARB), - NAME_FUNC_OFFSET(15982, glVertexAttrib2dARB, glVertexAttrib2dARB, NULL, _gloffset_VertexAttrib2dARB), - NAME_FUNC_OFFSET(15999, glVertexAttrib2dvARB, glVertexAttrib2dvARB, NULL, _gloffset_VertexAttrib2dvARB), - NAME_FUNC_OFFSET(16017, glVertexAttrib2fARB, glVertexAttrib2fARB, NULL, _gloffset_VertexAttrib2fARB), - NAME_FUNC_OFFSET(16034, glVertexAttrib2fvARB, glVertexAttrib2fvARB, NULL, _gloffset_VertexAttrib2fvARB), - NAME_FUNC_OFFSET(16052, glVertexAttrib2sARB, glVertexAttrib2sARB, NULL, _gloffset_VertexAttrib2sARB), - NAME_FUNC_OFFSET(16069, glVertexAttrib2svARB, glVertexAttrib2svARB, NULL, _gloffset_VertexAttrib2svARB), - NAME_FUNC_OFFSET(16087, glVertexAttrib3dARB, glVertexAttrib3dARB, NULL, _gloffset_VertexAttrib3dARB), - NAME_FUNC_OFFSET(16104, glVertexAttrib3dvARB, glVertexAttrib3dvARB, NULL, _gloffset_VertexAttrib3dvARB), - NAME_FUNC_OFFSET(16122, glVertexAttrib3fARB, glVertexAttrib3fARB, NULL, _gloffset_VertexAttrib3fARB), - NAME_FUNC_OFFSET(16139, glVertexAttrib3fvARB, glVertexAttrib3fvARB, NULL, _gloffset_VertexAttrib3fvARB), - NAME_FUNC_OFFSET(16157, glVertexAttrib3sARB, glVertexAttrib3sARB, NULL, _gloffset_VertexAttrib3sARB), - NAME_FUNC_OFFSET(16174, glVertexAttrib3svARB, glVertexAttrib3svARB, NULL, _gloffset_VertexAttrib3svARB), - NAME_FUNC_OFFSET(16192, glVertexAttrib4NbvARB, glVertexAttrib4NbvARB, NULL, _gloffset_VertexAttrib4NbvARB), - NAME_FUNC_OFFSET(16211, glVertexAttrib4NivARB, glVertexAttrib4NivARB, NULL, _gloffset_VertexAttrib4NivARB), - NAME_FUNC_OFFSET(16230, glVertexAttrib4NsvARB, glVertexAttrib4NsvARB, NULL, _gloffset_VertexAttrib4NsvARB), - NAME_FUNC_OFFSET(16249, glVertexAttrib4NubARB, glVertexAttrib4NubARB, NULL, _gloffset_VertexAttrib4NubARB), - NAME_FUNC_OFFSET(16268, glVertexAttrib4NubvARB, glVertexAttrib4NubvARB, NULL, _gloffset_VertexAttrib4NubvARB), - NAME_FUNC_OFFSET(16288, glVertexAttrib4NuivARB, glVertexAttrib4NuivARB, NULL, _gloffset_VertexAttrib4NuivARB), - NAME_FUNC_OFFSET(16308, glVertexAttrib4NusvARB, glVertexAttrib4NusvARB, NULL, _gloffset_VertexAttrib4NusvARB), - NAME_FUNC_OFFSET(16328, glVertexAttrib4bvARB, glVertexAttrib4bvARB, NULL, _gloffset_VertexAttrib4bvARB), - NAME_FUNC_OFFSET(16346, glVertexAttrib4dARB, glVertexAttrib4dARB, NULL, _gloffset_VertexAttrib4dARB), - NAME_FUNC_OFFSET(16363, glVertexAttrib4dvARB, glVertexAttrib4dvARB, NULL, _gloffset_VertexAttrib4dvARB), - NAME_FUNC_OFFSET(16381, glVertexAttrib4fARB, glVertexAttrib4fARB, NULL, _gloffset_VertexAttrib4fARB), - NAME_FUNC_OFFSET(16398, glVertexAttrib4fvARB, glVertexAttrib4fvARB, NULL, _gloffset_VertexAttrib4fvARB), - NAME_FUNC_OFFSET(16416, glVertexAttrib4ivARB, glVertexAttrib4ivARB, NULL, _gloffset_VertexAttrib4ivARB), - NAME_FUNC_OFFSET(16434, glVertexAttrib4sARB, glVertexAttrib4sARB, NULL, _gloffset_VertexAttrib4sARB), - NAME_FUNC_OFFSET(16451, glVertexAttrib4svARB, glVertexAttrib4svARB, NULL, _gloffset_VertexAttrib4svARB), - NAME_FUNC_OFFSET(16469, glVertexAttrib4ubvARB, glVertexAttrib4ubvARB, NULL, _gloffset_VertexAttrib4ubvARB), - NAME_FUNC_OFFSET(16488, glVertexAttrib4uivARB, glVertexAttrib4uivARB, NULL, _gloffset_VertexAttrib4uivARB), - NAME_FUNC_OFFSET(16507, glVertexAttrib4usvARB, glVertexAttrib4usvARB, NULL, _gloffset_VertexAttrib4usvARB), - NAME_FUNC_OFFSET(16526, glVertexAttribPointerARB, glVertexAttribPointerARB, NULL, _gloffset_VertexAttribPointerARB), - NAME_FUNC_OFFSET(16548, glBindBufferARB, glBindBufferARB, NULL, _gloffset_BindBufferARB), - NAME_FUNC_OFFSET(16561, glBufferDataARB, glBufferDataARB, NULL, _gloffset_BufferDataARB), - NAME_FUNC_OFFSET(16574, glBufferSubDataARB, glBufferSubDataARB, NULL, _gloffset_BufferSubDataARB), - NAME_FUNC_OFFSET(16590, glDeleteBuffersARB, glDeleteBuffersARB, NULL, _gloffset_DeleteBuffersARB), - NAME_FUNC_OFFSET(16606, glGenBuffersARB, glGenBuffersARB, NULL, _gloffset_GenBuffersARB), - NAME_FUNC_OFFSET(16619, glGetBufferParameterivARB, glGetBufferParameterivARB, NULL, _gloffset_GetBufferParameterivARB), - NAME_FUNC_OFFSET(16642, glGetBufferPointervARB, glGetBufferPointervARB, NULL, _gloffset_GetBufferPointervARB), - NAME_FUNC_OFFSET(16662, glGetBufferSubDataARB, glGetBufferSubDataARB, NULL, _gloffset_GetBufferSubDataARB), - NAME_FUNC_OFFSET(16681, glIsBufferARB, glIsBufferARB, NULL, _gloffset_IsBufferARB), - NAME_FUNC_OFFSET(16692, glMapBufferARB, glMapBufferARB, NULL, _gloffset_MapBufferARB), - NAME_FUNC_OFFSET(16704, glUnmapBufferARB, glUnmapBufferARB, NULL, _gloffset_UnmapBufferARB), - NAME_FUNC_OFFSET(16718, glBeginQueryARB, glBeginQueryARB, NULL, _gloffset_BeginQueryARB), - NAME_FUNC_OFFSET(16731, glDeleteQueriesARB, glDeleteQueriesARB, NULL, _gloffset_DeleteQueriesARB), - NAME_FUNC_OFFSET(16747, glEndQueryARB, glEndQueryARB, NULL, _gloffset_EndQueryARB), - NAME_FUNC_OFFSET(16758, glGenQueriesARB, glGenQueriesARB, NULL, _gloffset_GenQueriesARB), - NAME_FUNC_OFFSET(16771, glGetQueryObjectivARB, glGetQueryObjectivARB, NULL, _gloffset_GetQueryObjectivARB), - NAME_FUNC_OFFSET(16790, glGetQueryObjectuivARB, glGetQueryObjectuivARB, NULL, _gloffset_GetQueryObjectuivARB), - NAME_FUNC_OFFSET(16810, glGetQueryivARB, glGetQueryivARB, NULL, _gloffset_GetQueryivARB), - NAME_FUNC_OFFSET(16823, glIsQueryARB, glIsQueryARB, NULL, _gloffset_IsQueryARB), - NAME_FUNC_OFFSET(16833, glCompileShaderARB, glCompileShaderARB, NULL, _gloffset_CompileShaderARB), - NAME_FUNC_OFFSET(16849, glGetActiveUniformARB, glGetActiveUniformARB, NULL, _gloffset_GetActiveUniformARB), - NAME_FUNC_OFFSET(16868, glGetShaderSourceARB, glGetShaderSourceARB, NULL, _gloffset_GetShaderSourceARB), - NAME_FUNC_OFFSET(16886, glGetUniformLocationARB, glGetUniformLocationARB, NULL, _gloffset_GetUniformLocationARB), - NAME_FUNC_OFFSET(16907, glGetUniformfvARB, glGetUniformfvARB, NULL, _gloffset_GetUniformfvARB), - NAME_FUNC_OFFSET(16922, glGetUniformivARB, glGetUniformivARB, NULL, _gloffset_GetUniformivARB), - NAME_FUNC_OFFSET(16937, glLinkProgramARB, glLinkProgramARB, NULL, _gloffset_LinkProgramARB), - NAME_FUNC_OFFSET(16951, glShaderSourceARB, glShaderSourceARB, NULL, _gloffset_ShaderSourceARB), - NAME_FUNC_OFFSET(16966, glUniform1fARB, glUniform1fARB, NULL, _gloffset_Uniform1fARB), - NAME_FUNC_OFFSET(16978, glUniform1fvARB, glUniform1fvARB, NULL, _gloffset_Uniform1fvARB), - NAME_FUNC_OFFSET(16991, glUniform1iARB, glUniform1iARB, NULL, _gloffset_Uniform1iARB), - NAME_FUNC_OFFSET(17003, glUniform1ivARB, glUniform1ivARB, NULL, _gloffset_Uniform1ivARB), - NAME_FUNC_OFFSET(17016, glUniform2fARB, glUniform2fARB, NULL, _gloffset_Uniform2fARB), - NAME_FUNC_OFFSET(17028, glUniform2fvARB, glUniform2fvARB, NULL, _gloffset_Uniform2fvARB), - NAME_FUNC_OFFSET(17041, glUniform2iARB, glUniform2iARB, NULL, _gloffset_Uniform2iARB), - NAME_FUNC_OFFSET(17053, glUniform2ivARB, glUniform2ivARB, NULL, _gloffset_Uniform2ivARB), - NAME_FUNC_OFFSET(17066, glUniform3fARB, glUniform3fARB, NULL, _gloffset_Uniform3fARB), - NAME_FUNC_OFFSET(17078, glUniform3fvARB, glUniform3fvARB, NULL, _gloffset_Uniform3fvARB), - NAME_FUNC_OFFSET(17091, glUniform3iARB, glUniform3iARB, NULL, _gloffset_Uniform3iARB), - NAME_FUNC_OFFSET(17103, glUniform3ivARB, glUniform3ivARB, NULL, _gloffset_Uniform3ivARB), - NAME_FUNC_OFFSET(17116, glUniform4fARB, glUniform4fARB, NULL, _gloffset_Uniform4fARB), - NAME_FUNC_OFFSET(17128, glUniform4fvARB, glUniform4fvARB, NULL, _gloffset_Uniform4fvARB), - NAME_FUNC_OFFSET(17141, glUniform4iARB, glUniform4iARB, NULL, _gloffset_Uniform4iARB), - NAME_FUNC_OFFSET(17153, glUniform4ivARB, glUniform4ivARB, NULL, _gloffset_Uniform4ivARB), - NAME_FUNC_OFFSET(17166, glUniformMatrix2fvARB, glUniformMatrix2fvARB, NULL, _gloffset_UniformMatrix2fvARB), - NAME_FUNC_OFFSET(17185, glUniformMatrix3fvARB, glUniformMatrix3fvARB, NULL, _gloffset_UniformMatrix3fvARB), - NAME_FUNC_OFFSET(17204, glUniformMatrix4fvARB, glUniformMatrix4fvARB, NULL, _gloffset_UniformMatrix4fvARB), - NAME_FUNC_OFFSET(17223, glUseProgramObjectARB, glUseProgramObjectARB, NULL, _gloffset_UseProgramObjectARB), - NAME_FUNC_OFFSET(17236, glValidateProgramARB, glValidateProgramARB, NULL, _gloffset_ValidateProgramARB), - NAME_FUNC_OFFSET(17254, glBindAttribLocationARB, glBindAttribLocationARB, NULL, _gloffset_BindAttribLocationARB), - NAME_FUNC_OFFSET(17275, glGetActiveAttribARB, glGetActiveAttribARB, NULL, _gloffset_GetActiveAttribARB), - NAME_FUNC_OFFSET(17293, glGetAttribLocationARB, glGetAttribLocationARB, NULL, _gloffset_GetAttribLocationARB), - NAME_FUNC_OFFSET(17313, glDrawBuffersARB, glDrawBuffersARB, NULL, _gloffset_DrawBuffersARB), - NAME_FUNC_OFFSET(17327, glDrawBuffersARB, glDrawBuffersARB, NULL, _gloffset_DrawBuffersARB), - NAME_FUNC_OFFSET(17344, gl_dispatch_stub_568, gl_dispatch_stub_568, NULL, _gloffset_SampleMaskSGIS), - NAME_FUNC_OFFSET(17360, gl_dispatch_stub_569, gl_dispatch_stub_569, NULL, _gloffset_SamplePatternSGIS), - NAME_FUNC_OFFSET(17379, glPointParameterfEXT, glPointParameterfEXT, NULL, _gloffset_PointParameterfEXT), - NAME_FUNC_OFFSET(17397, glPointParameterfEXT, glPointParameterfEXT, NULL, _gloffset_PointParameterfEXT), - NAME_FUNC_OFFSET(17418, glPointParameterfEXT, glPointParameterfEXT, NULL, _gloffset_PointParameterfEXT), - NAME_FUNC_OFFSET(17440, glPointParameterfvEXT, glPointParameterfvEXT, NULL, _gloffset_PointParameterfvEXT), - NAME_FUNC_OFFSET(17459, glPointParameterfvEXT, glPointParameterfvEXT, NULL, _gloffset_PointParameterfvEXT), - NAME_FUNC_OFFSET(17481, glPointParameterfvEXT, glPointParameterfvEXT, NULL, _gloffset_PointParameterfvEXT), - NAME_FUNC_OFFSET(17504, glSecondaryColor3bEXT, glSecondaryColor3bEXT, NULL, _gloffset_SecondaryColor3bEXT), - NAME_FUNC_OFFSET(17523, glSecondaryColor3bvEXT, glSecondaryColor3bvEXT, NULL, _gloffset_SecondaryColor3bvEXT), - NAME_FUNC_OFFSET(17543, glSecondaryColor3dEXT, glSecondaryColor3dEXT, NULL, _gloffset_SecondaryColor3dEXT), - NAME_FUNC_OFFSET(17562, glSecondaryColor3dvEXT, glSecondaryColor3dvEXT, NULL, _gloffset_SecondaryColor3dvEXT), - NAME_FUNC_OFFSET(17582, glSecondaryColor3fEXT, glSecondaryColor3fEXT, NULL, _gloffset_SecondaryColor3fEXT), - NAME_FUNC_OFFSET(17601, glSecondaryColor3fvEXT, glSecondaryColor3fvEXT, NULL, _gloffset_SecondaryColor3fvEXT), - NAME_FUNC_OFFSET(17621, glSecondaryColor3iEXT, glSecondaryColor3iEXT, NULL, _gloffset_SecondaryColor3iEXT), - NAME_FUNC_OFFSET(17640, glSecondaryColor3ivEXT, glSecondaryColor3ivEXT, NULL, _gloffset_SecondaryColor3ivEXT), - NAME_FUNC_OFFSET(17660, glSecondaryColor3sEXT, glSecondaryColor3sEXT, NULL, _gloffset_SecondaryColor3sEXT), - NAME_FUNC_OFFSET(17679, glSecondaryColor3svEXT, glSecondaryColor3svEXT, NULL, _gloffset_SecondaryColor3svEXT), - NAME_FUNC_OFFSET(17699, glSecondaryColor3ubEXT, glSecondaryColor3ubEXT, NULL, _gloffset_SecondaryColor3ubEXT), - NAME_FUNC_OFFSET(17719, glSecondaryColor3ubvEXT, glSecondaryColor3ubvEXT, NULL, _gloffset_SecondaryColor3ubvEXT), - NAME_FUNC_OFFSET(17740, glSecondaryColor3uiEXT, glSecondaryColor3uiEXT, NULL, _gloffset_SecondaryColor3uiEXT), - NAME_FUNC_OFFSET(17760, glSecondaryColor3uivEXT, glSecondaryColor3uivEXT, NULL, _gloffset_SecondaryColor3uivEXT), - NAME_FUNC_OFFSET(17781, glSecondaryColor3usEXT, glSecondaryColor3usEXT, NULL, _gloffset_SecondaryColor3usEXT), - NAME_FUNC_OFFSET(17801, glSecondaryColor3usvEXT, glSecondaryColor3usvEXT, NULL, _gloffset_SecondaryColor3usvEXT), - NAME_FUNC_OFFSET(17822, glSecondaryColorPointerEXT, glSecondaryColorPointerEXT, NULL, _gloffset_SecondaryColorPointerEXT), - NAME_FUNC_OFFSET(17846, glMultiDrawArraysEXT, glMultiDrawArraysEXT, NULL, _gloffset_MultiDrawArraysEXT), - NAME_FUNC_OFFSET(17864, glMultiDrawElementsEXT, glMultiDrawElementsEXT, NULL, _gloffset_MultiDrawElementsEXT), - NAME_FUNC_OFFSET(17884, glFogCoordPointerEXT, glFogCoordPointerEXT, NULL, _gloffset_FogCoordPointerEXT), - NAME_FUNC_OFFSET(17902, glFogCoorddEXT, glFogCoorddEXT, NULL, _gloffset_FogCoorddEXT), - NAME_FUNC_OFFSET(17914, glFogCoorddvEXT, glFogCoorddvEXT, NULL, _gloffset_FogCoorddvEXT), - NAME_FUNC_OFFSET(17927, glFogCoordfEXT, glFogCoordfEXT, NULL, _gloffset_FogCoordfEXT), - NAME_FUNC_OFFSET(17939, glFogCoordfvEXT, glFogCoordfvEXT, NULL, _gloffset_FogCoordfvEXT), - NAME_FUNC_OFFSET(17952, glBlendFuncSeparateEXT, glBlendFuncSeparateEXT, NULL, _gloffset_BlendFuncSeparateEXT), - NAME_FUNC_OFFSET(17972, glBlendFuncSeparateEXT, glBlendFuncSeparateEXT, NULL, _gloffset_BlendFuncSeparateEXT), - NAME_FUNC_OFFSET(17996, glWindowPos2dMESA, glWindowPos2dMESA, NULL, _gloffset_WindowPos2dMESA), - NAME_FUNC_OFFSET(18010, glWindowPos2dMESA, glWindowPos2dMESA, NULL, _gloffset_WindowPos2dMESA), - NAME_FUNC_OFFSET(18027, glWindowPos2dvMESA, glWindowPos2dvMESA, NULL, _gloffset_WindowPos2dvMESA), - NAME_FUNC_OFFSET(18042, glWindowPos2dvMESA, glWindowPos2dvMESA, NULL, _gloffset_WindowPos2dvMESA), - NAME_FUNC_OFFSET(18060, glWindowPos2fMESA, glWindowPos2fMESA, NULL, _gloffset_WindowPos2fMESA), - NAME_FUNC_OFFSET(18074, glWindowPos2fMESA, glWindowPos2fMESA, NULL, _gloffset_WindowPos2fMESA), - NAME_FUNC_OFFSET(18091, glWindowPos2fvMESA, glWindowPos2fvMESA, NULL, _gloffset_WindowPos2fvMESA), - NAME_FUNC_OFFSET(18106, glWindowPos2fvMESA, glWindowPos2fvMESA, NULL, _gloffset_WindowPos2fvMESA), - NAME_FUNC_OFFSET(18124, glWindowPos2iMESA, glWindowPos2iMESA, NULL, _gloffset_WindowPos2iMESA), - NAME_FUNC_OFFSET(18138, glWindowPos2iMESA, glWindowPos2iMESA, NULL, _gloffset_WindowPos2iMESA), - NAME_FUNC_OFFSET(18155, glWindowPos2ivMESA, glWindowPos2ivMESA, NULL, _gloffset_WindowPos2ivMESA), - NAME_FUNC_OFFSET(18170, glWindowPos2ivMESA, glWindowPos2ivMESA, NULL, _gloffset_WindowPos2ivMESA), - NAME_FUNC_OFFSET(18188, glWindowPos2sMESA, glWindowPos2sMESA, NULL, _gloffset_WindowPos2sMESA), - NAME_FUNC_OFFSET(18202, glWindowPos2sMESA, glWindowPos2sMESA, NULL, _gloffset_WindowPos2sMESA), - NAME_FUNC_OFFSET(18219, glWindowPos2svMESA, glWindowPos2svMESA, NULL, _gloffset_WindowPos2svMESA), - NAME_FUNC_OFFSET(18234, glWindowPos2svMESA, glWindowPos2svMESA, NULL, _gloffset_WindowPos2svMESA), - NAME_FUNC_OFFSET(18252, glWindowPos3dMESA, glWindowPos3dMESA, NULL, _gloffset_WindowPos3dMESA), - NAME_FUNC_OFFSET(18266, glWindowPos3dMESA, glWindowPos3dMESA, NULL, _gloffset_WindowPos3dMESA), - NAME_FUNC_OFFSET(18283, glWindowPos3dvMESA, glWindowPos3dvMESA, NULL, _gloffset_WindowPos3dvMESA), - NAME_FUNC_OFFSET(18298, glWindowPos3dvMESA, glWindowPos3dvMESA, NULL, _gloffset_WindowPos3dvMESA), - NAME_FUNC_OFFSET(18316, glWindowPos3fMESA, glWindowPos3fMESA, NULL, _gloffset_WindowPos3fMESA), - NAME_FUNC_OFFSET(18330, glWindowPos3fMESA, glWindowPos3fMESA, NULL, _gloffset_WindowPos3fMESA), - NAME_FUNC_OFFSET(18347, glWindowPos3fvMESA, glWindowPos3fvMESA, NULL, _gloffset_WindowPos3fvMESA), - NAME_FUNC_OFFSET(18362, glWindowPos3fvMESA, glWindowPos3fvMESA, NULL, _gloffset_WindowPos3fvMESA), - NAME_FUNC_OFFSET(18380, glWindowPos3iMESA, glWindowPos3iMESA, NULL, _gloffset_WindowPos3iMESA), - NAME_FUNC_OFFSET(18394, glWindowPos3iMESA, glWindowPos3iMESA, NULL, _gloffset_WindowPos3iMESA), - NAME_FUNC_OFFSET(18411, glWindowPos3ivMESA, glWindowPos3ivMESA, NULL, _gloffset_WindowPos3ivMESA), - NAME_FUNC_OFFSET(18426, glWindowPos3ivMESA, glWindowPos3ivMESA, NULL, _gloffset_WindowPos3ivMESA), - NAME_FUNC_OFFSET(18444, glWindowPos3sMESA, glWindowPos3sMESA, NULL, _gloffset_WindowPos3sMESA), - NAME_FUNC_OFFSET(18458, glWindowPos3sMESA, glWindowPos3sMESA, NULL, _gloffset_WindowPos3sMESA), - NAME_FUNC_OFFSET(18475, glWindowPos3svMESA, glWindowPos3svMESA, NULL, _gloffset_WindowPos3svMESA), - NAME_FUNC_OFFSET(18490, glWindowPos3svMESA, glWindowPos3svMESA, NULL, _gloffset_WindowPos3svMESA), - NAME_FUNC_OFFSET(18508, glBindProgramNV, glBindProgramNV, NULL, _gloffset_BindProgramNV), - NAME_FUNC_OFFSET(18525, glDeleteProgramsNV, glDeleteProgramsNV, NULL, _gloffset_DeleteProgramsNV), - NAME_FUNC_OFFSET(18545, glGenProgramsNV, glGenProgramsNV, NULL, _gloffset_GenProgramsNV), - NAME_FUNC_OFFSET(18562, glGetVertexAttribPointervNV, glGetVertexAttribPointervNV, NULL, _gloffset_GetVertexAttribPointervNV), - NAME_FUNC_OFFSET(18588, glGetVertexAttribPointervNV, glGetVertexAttribPointervNV, NULL, _gloffset_GetVertexAttribPointervNV), - NAME_FUNC_OFFSET(18617, glIsProgramNV, glIsProgramNV, NULL, _gloffset_IsProgramNV), - NAME_FUNC_OFFSET(18632, glPointParameteriNV, glPointParameteriNV, NULL, _gloffset_PointParameteriNV), - NAME_FUNC_OFFSET(18650, glPointParameterivNV, glPointParameterivNV, NULL, _gloffset_PointParameterivNV), - NAME_FUNC_OFFSET(18669, gl_dispatch_stub_749, gl_dispatch_stub_749, NULL, _gloffset_BlendEquationSeparateEXT), - NAME_FUNC_OFFSET(18693, gl_dispatch_stub_749, gl_dispatch_stub_749, NULL, _gloffset_BlendEquationSeparateEXT), + NAME_FUNC_OFFSET(13470, gl_dispatch_stub_768, gl_dispatch_stub_768, NULL, _gloffset_StencilFuncSeparateATI), + NAME_FUNC_OFFSET(13495, gl_dispatch_stub_769, gl_dispatch_stub_769, NULL, _gloffset_ProgramEnvParameters4fvEXT), + NAME_FUNC_OFFSET(13524, gl_dispatch_stub_770, gl_dispatch_stub_770, NULL, _gloffset_ProgramLocalParameters4fvEXT), + NAME_FUNC_OFFSET(13555, gl_dispatch_stub_771, gl_dispatch_stub_771, NULL, _gloffset_GetQueryObjecti64vEXT), + NAME_FUNC_OFFSET(13579, gl_dispatch_stub_772, gl_dispatch_stub_772, NULL, _gloffset_GetQueryObjectui64vEXT), + NAME_FUNC_OFFSET(13604, glArrayElement, glArrayElement, NULL, _gloffset_ArrayElement), + NAME_FUNC_OFFSET(13622, glBindTexture, glBindTexture, NULL, _gloffset_BindTexture), + NAME_FUNC_OFFSET(13639, glDrawArrays, glDrawArrays, NULL, _gloffset_DrawArrays), + NAME_FUNC_OFFSET(13655, glAreTexturesResident, glAreTexturesResidentEXT, glAreTexturesResidentEXT, _gloffset_AreTexturesResident), + NAME_FUNC_OFFSET(13680, glCopyTexImage1D, glCopyTexImage1D, NULL, _gloffset_CopyTexImage1D), + NAME_FUNC_OFFSET(13700, glCopyTexImage2D, glCopyTexImage2D, NULL, _gloffset_CopyTexImage2D), + NAME_FUNC_OFFSET(13720, glCopyTexSubImage1D, glCopyTexSubImage1D, NULL, _gloffset_CopyTexSubImage1D), + NAME_FUNC_OFFSET(13743, glCopyTexSubImage2D, glCopyTexSubImage2D, NULL, _gloffset_CopyTexSubImage2D), + NAME_FUNC_OFFSET(13766, glDeleteTextures, glDeleteTexturesEXT, glDeleteTexturesEXT, _gloffset_DeleteTextures), + NAME_FUNC_OFFSET(13786, glGenTextures, glGenTexturesEXT, glGenTexturesEXT, _gloffset_GenTextures), + NAME_FUNC_OFFSET(13803, glGetPointerv, glGetPointerv, NULL, _gloffset_GetPointerv), + NAME_FUNC_OFFSET(13820, glIsTexture, glIsTextureEXT, glIsTextureEXT, _gloffset_IsTexture), + NAME_FUNC_OFFSET(13835, glPrioritizeTextures, glPrioritizeTextures, NULL, _gloffset_PrioritizeTextures), + NAME_FUNC_OFFSET(13859, glTexSubImage1D, glTexSubImage1D, NULL, _gloffset_TexSubImage1D), + NAME_FUNC_OFFSET(13878, glTexSubImage2D, glTexSubImage2D, NULL, _gloffset_TexSubImage2D), + NAME_FUNC_OFFSET(13897, glBlendColor, glBlendColor, NULL, _gloffset_BlendColor), + NAME_FUNC_OFFSET(13913, glBlendEquation, glBlendEquation, NULL, _gloffset_BlendEquation), + NAME_FUNC_OFFSET(13932, glDrawRangeElements, glDrawRangeElements, NULL, _gloffset_DrawRangeElements), + NAME_FUNC_OFFSET(13955, glColorTable, glColorTable, NULL, _gloffset_ColorTable), + NAME_FUNC_OFFSET(13971, glColorTable, glColorTable, NULL, _gloffset_ColorTable), + NAME_FUNC_OFFSET(13987, glColorTableParameterfv, glColorTableParameterfv, NULL, _gloffset_ColorTableParameterfv), + NAME_FUNC_OFFSET(14014, glColorTableParameteriv, glColorTableParameteriv, NULL, _gloffset_ColorTableParameteriv), + NAME_FUNC_OFFSET(14041, glCopyColorTable, glCopyColorTable, NULL, _gloffset_CopyColorTable), + NAME_FUNC_OFFSET(14061, glGetColorTable, glGetColorTableEXT, glGetColorTableEXT, _gloffset_GetColorTable), + NAME_FUNC_OFFSET(14080, glGetColorTable, glGetColorTableEXT, glGetColorTableEXT, _gloffset_GetColorTable), + NAME_FUNC_OFFSET(14099, glGetColorTableParameterfv, glGetColorTableParameterfvEXT, glGetColorTableParameterfvEXT, _gloffset_GetColorTableParameterfv), + NAME_FUNC_OFFSET(14129, glGetColorTableParameterfv, glGetColorTableParameterfvEXT, glGetColorTableParameterfvEXT, _gloffset_GetColorTableParameterfv), + NAME_FUNC_OFFSET(14159, glGetColorTableParameteriv, glGetColorTableParameterivEXT, glGetColorTableParameterivEXT, _gloffset_GetColorTableParameteriv), + NAME_FUNC_OFFSET(14189, glGetColorTableParameteriv, glGetColorTableParameterivEXT, glGetColorTableParameterivEXT, _gloffset_GetColorTableParameteriv), + NAME_FUNC_OFFSET(14219, glColorSubTable, glColorSubTable, NULL, _gloffset_ColorSubTable), + NAME_FUNC_OFFSET(14238, glCopyColorSubTable, glCopyColorSubTable, NULL, _gloffset_CopyColorSubTable), + NAME_FUNC_OFFSET(14261, glConvolutionFilter1D, glConvolutionFilter1D, NULL, _gloffset_ConvolutionFilter1D), + NAME_FUNC_OFFSET(14286, glConvolutionFilter2D, glConvolutionFilter2D, NULL, _gloffset_ConvolutionFilter2D), + NAME_FUNC_OFFSET(14311, glConvolutionParameterf, glConvolutionParameterf, NULL, _gloffset_ConvolutionParameterf), + NAME_FUNC_OFFSET(14338, glConvolutionParameterfv, glConvolutionParameterfv, NULL, _gloffset_ConvolutionParameterfv), + NAME_FUNC_OFFSET(14366, glConvolutionParameteri, glConvolutionParameteri, NULL, _gloffset_ConvolutionParameteri), + NAME_FUNC_OFFSET(14393, glConvolutionParameteriv, glConvolutionParameteriv, NULL, _gloffset_ConvolutionParameteriv), + NAME_FUNC_OFFSET(14421, glCopyConvolutionFilter1D, glCopyConvolutionFilter1D, NULL, _gloffset_CopyConvolutionFilter1D), + NAME_FUNC_OFFSET(14450, glCopyConvolutionFilter2D, glCopyConvolutionFilter2D, NULL, _gloffset_CopyConvolutionFilter2D), + NAME_FUNC_OFFSET(14479, glGetConvolutionFilter, gl_dispatch_stub_356, gl_dispatch_stub_356, _gloffset_GetConvolutionFilter), + NAME_FUNC_OFFSET(14505, glGetConvolutionParameterfv, gl_dispatch_stub_357, gl_dispatch_stub_357, _gloffset_GetConvolutionParameterfv), + NAME_FUNC_OFFSET(14536, glGetConvolutionParameteriv, gl_dispatch_stub_358, gl_dispatch_stub_358, _gloffset_GetConvolutionParameteriv), + NAME_FUNC_OFFSET(14567, glGetSeparableFilter, gl_dispatch_stub_359, gl_dispatch_stub_359, _gloffset_GetSeparableFilter), + NAME_FUNC_OFFSET(14591, glSeparableFilter2D, glSeparableFilter2D, NULL, _gloffset_SeparableFilter2D), + NAME_FUNC_OFFSET(14614, glGetHistogram, gl_dispatch_stub_361, gl_dispatch_stub_361, _gloffset_GetHistogram), + NAME_FUNC_OFFSET(14632, glGetHistogramParameterfv, gl_dispatch_stub_362, gl_dispatch_stub_362, _gloffset_GetHistogramParameterfv), + NAME_FUNC_OFFSET(14661, glGetHistogramParameteriv, gl_dispatch_stub_363, gl_dispatch_stub_363, _gloffset_GetHistogramParameteriv), + NAME_FUNC_OFFSET(14690, glGetMinmax, gl_dispatch_stub_364, gl_dispatch_stub_364, _gloffset_GetMinmax), + NAME_FUNC_OFFSET(14705, glGetMinmaxParameterfv, gl_dispatch_stub_365, gl_dispatch_stub_365, _gloffset_GetMinmaxParameterfv), + NAME_FUNC_OFFSET(14731, glGetMinmaxParameteriv, gl_dispatch_stub_366, gl_dispatch_stub_366, _gloffset_GetMinmaxParameteriv), + NAME_FUNC_OFFSET(14757, glHistogram, glHistogram, NULL, _gloffset_Histogram), + NAME_FUNC_OFFSET(14772, glMinmax, glMinmax, NULL, _gloffset_Minmax), + NAME_FUNC_OFFSET(14784, glResetHistogram, glResetHistogram, NULL, _gloffset_ResetHistogram), + NAME_FUNC_OFFSET(14804, glResetMinmax, glResetMinmax, NULL, _gloffset_ResetMinmax), + NAME_FUNC_OFFSET(14821, glTexImage3D, glTexImage3D, NULL, _gloffset_TexImage3D), + NAME_FUNC_OFFSET(14837, glTexSubImage3D, glTexSubImage3D, NULL, _gloffset_TexSubImage3D), + NAME_FUNC_OFFSET(14856, glCopyTexSubImage3D, glCopyTexSubImage3D, NULL, _gloffset_CopyTexSubImage3D), + NAME_FUNC_OFFSET(14879, glActiveTextureARB, glActiveTextureARB, NULL, _gloffset_ActiveTextureARB), + NAME_FUNC_OFFSET(14895, glClientActiveTextureARB, glClientActiveTextureARB, NULL, _gloffset_ClientActiveTextureARB), + NAME_FUNC_OFFSET(14917, glMultiTexCoord1dARB, glMultiTexCoord1dARB, NULL, _gloffset_MultiTexCoord1dARB), + NAME_FUNC_OFFSET(14935, glMultiTexCoord1dvARB, glMultiTexCoord1dvARB, NULL, _gloffset_MultiTexCoord1dvARB), + NAME_FUNC_OFFSET(14954, glMultiTexCoord1fARB, glMultiTexCoord1fARB, NULL, _gloffset_MultiTexCoord1fARB), + NAME_FUNC_OFFSET(14972, glMultiTexCoord1fvARB, glMultiTexCoord1fvARB, NULL, _gloffset_MultiTexCoord1fvARB), + NAME_FUNC_OFFSET(14991, glMultiTexCoord1iARB, glMultiTexCoord1iARB, NULL, _gloffset_MultiTexCoord1iARB), + NAME_FUNC_OFFSET(15009, glMultiTexCoord1ivARB, glMultiTexCoord1ivARB, NULL, _gloffset_MultiTexCoord1ivARB), + NAME_FUNC_OFFSET(15028, glMultiTexCoord1sARB, glMultiTexCoord1sARB, NULL, _gloffset_MultiTexCoord1sARB), + NAME_FUNC_OFFSET(15046, glMultiTexCoord1svARB, glMultiTexCoord1svARB, NULL, _gloffset_MultiTexCoord1svARB), + NAME_FUNC_OFFSET(15065, glMultiTexCoord2dARB, glMultiTexCoord2dARB, NULL, _gloffset_MultiTexCoord2dARB), + NAME_FUNC_OFFSET(15083, glMultiTexCoord2dvARB, glMultiTexCoord2dvARB, NULL, _gloffset_MultiTexCoord2dvARB), + NAME_FUNC_OFFSET(15102, glMultiTexCoord2fARB, glMultiTexCoord2fARB, NULL, _gloffset_MultiTexCoord2fARB), + NAME_FUNC_OFFSET(15120, glMultiTexCoord2fvARB, glMultiTexCoord2fvARB, NULL, _gloffset_MultiTexCoord2fvARB), + NAME_FUNC_OFFSET(15139, glMultiTexCoord2iARB, glMultiTexCoord2iARB, NULL, _gloffset_MultiTexCoord2iARB), + NAME_FUNC_OFFSET(15157, glMultiTexCoord2ivARB, glMultiTexCoord2ivARB, NULL, _gloffset_MultiTexCoord2ivARB), + NAME_FUNC_OFFSET(15176, glMultiTexCoord2sARB, glMultiTexCoord2sARB, NULL, _gloffset_MultiTexCoord2sARB), + NAME_FUNC_OFFSET(15194, glMultiTexCoord2svARB, glMultiTexCoord2svARB, NULL, _gloffset_MultiTexCoord2svARB), + NAME_FUNC_OFFSET(15213, glMultiTexCoord3dARB, glMultiTexCoord3dARB, NULL, _gloffset_MultiTexCoord3dARB), + NAME_FUNC_OFFSET(15231, glMultiTexCoord3dvARB, glMultiTexCoord3dvARB, NULL, _gloffset_MultiTexCoord3dvARB), + NAME_FUNC_OFFSET(15250, glMultiTexCoord3fARB, glMultiTexCoord3fARB, NULL, _gloffset_MultiTexCoord3fARB), + NAME_FUNC_OFFSET(15268, glMultiTexCoord3fvARB, glMultiTexCoord3fvARB, NULL, _gloffset_MultiTexCoord3fvARB), + NAME_FUNC_OFFSET(15287, glMultiTexCoord3iARB, glMultiTexCoord3iARB, NULL, _gloffset_MultiTexCoord3iARB), + NAME_FUNC_OFFSET(15305, glMultiTexCoord3ivARB, glMultiTexCoord3ivARB, NULL, _gloffset_MultiTexCoord3ivARB), + NAME_FUNC_OFFSET(15324, glMultiTexCoord3sARB, glMultiTexCoord3sARB, NULL, _gloffset_MultiTexCoord3sARB), + NAME_FUNC_OFFSET(15342, glMultiTexCoord3svARB, glMultiTexCoord3svARB, NULL, _gloffset_MultiTexCoord3svARB), + NAME_FUNC_OFFSET(15361, glMultiTexCoord4dARB, glMultiTexCoord4dARB, NULL, _gloffset_MultiTexCoord4dARB), + NAME_FUNC_OFFSET(15379, glMultiTexCoord4dvARB, glMultiTexCoord4dvARB, NULL, _gloffset_MultiTexCoord4dvARB), + NAME_FUNC_OFFSET(15398, glMultiTexCoord4fARB, glMultiTexCoord4fARB, NULL, _gloffset_MultiTexCoord4fARB), + NAME_FUNC_OFFSET(15416, glMultiTexCoord4fvARB, glMultiTexCoord4fvARB, NULL, _gloffset_MultiTexCoord4fvARB), + NAME_FUNC_OFFSET(15435, glMultiTexCoord4iARB, glMultiTexCoord4iARB, NULL, _gloffset_MultiTexCoord4iARB), + NAME_FUNC_OFFSET(15453, glMultiTexCoord4ivARB, glMultiTexCoord4ivARB, NULL, _gloffset_MultiTexCoord4ivARB), + NAME_FUNC_OFFSET(15472, glMultiTexCoord4sARB, glMultiTexCoord4sARB, NULL, _gloffset_MultiTexCoord4sARB), + NAME_FUNC_OFFSET(15490, glMultiTexCoord4svARB, glMultiTexCoord4svARB, NULL, _gloffset_MultiTexCoord4svARB), + NAME_FUNC_OFFSET(15509, glStencilOpSeparate, glStencilOpSeparate, NULL, _gloffset_StencilOpSeparate), + NAME_FUNC_OFFSET(15532, glLoadTransposeMatrixdARB, glLoadTransposeMatrixdARB, NULL, _gloffset_LoadTransposeMatrixdARB), + NAME_FUNC_OFFSET(15555, glLoadTransposeMatrixfARB, glLoadTransposeMatrixfARB, NULL, _gloffset_LoadTransposeMatrixfARB), + NAME_FUNC_OFFSET(15578, glMultTransposeMatrixdARB, glMultTransposeMatrixdARB, NULL, _gloffset_MultTransposeMatrixdARB), + NAME_FUNC_OFFSET(15601, glMultTransposeMatrixfARB, glMultTransposeMatrixfARB, NULL, _gloffset_MultTransposeMatrixfARB), + NAME_FUNC_OFFSET(15624, glSampleCoverageARB, glSampleCoverageARB, NULL, _gloffset_SampleCoverageARB), + NAME_FUNC_OFFSET(15641, glCompressedTexImage1DARB, glCompressedTexImage1DARB, NULL, _gloffset_CompressedTexImage1DARB), + NAME_FUNC_OFFSET(15664, glCompressedTexImage2DARB, glCompressedTexImage2DARB, NULL, _gloffset_CompressedTexImage2DARB), + NAME_FUNC_OFFSET(15687, glCompressedTexImage3DARB, glCompressedTexImage3DARB, NULL, _gloffset_CompressedTexImage3DARB), + NAME_FUNC_OFFSET(15710, glCompressedTexSubImage1DARB, glCompressedTexSubImage1DARB, NULL, _gloffset_CompressedTexSubImage1DARB), + NAME_FUNC_OFFSET(15736, glCompressedTexSubImage2DARB, glCompressedTexSubImage2DARB, NULL, _gloffset_CompressedTexSubImage2DARB), + NAME_FUNC_OFFSET(15762, glCompressedTexSubImage3DARB, glCompressedTexSubImage3DARB, NULL, _gloffset_CompressedTexSubImage3DARB), + NAME_FUNC_OFFSET(15788, glGetCompressedTexImageARB, glGetCompressedTexImageARB, NULL, _gloffset_GetCompressedTexImageARB), + NAME_FUNC_OFFSET(15812, glDisableVertexAttribArrayARB, glDisableVertexAttribArrayARB, NULL, _gloffset_DisableVertexAttribArrayARB), + NAME_FUNC_OFFSET(15839, glEnableVertexAttribArrayARB, glEnableVertexAttribArrayARB, NULL, _gloffset_EnableVertexAttribArrayARB), + NAME_FUNC_OFFSET(15865, glGetVertexAttribdvARB, glGetVertexAttribdvARB, NULL, _gloffset_GetVertexAttribdvARB), + NAME_FUNC_OFFSET(15885, glGetVertexAttribfvARB, glGetVertexAttribfvARB, NULL, _gloffset_GetVertexAttribfvARB), + NAME_FUNC_OFFSET(15905, glGetVertexAttribivARB, glGetVertexAttribivARB, NULL, _gloffset_GetVertexAttribivARB), + NAME_FUNC_OFFSET(15925, glVertexAttrib1dARB, glVertexAttrib1dARB, NULL, _gloffset_VertexAttrib1dARB), + NAME_FUNC_OFFSET(15942, glVertexAttrib1dvARB, glVertexAttrib1dvARB, NULL, _gloffset_VertexAttrib1dvARB), + NAME_FUNC_OFFSET(15960, glVertexAttrib1fARB, glVertexAttrib1fARB, NULL, _gloffset_VertexAttrib1fARB), + NAME_FUNC_OFFSET(15977, glVertexAttrib1fvARB, glVertexAttrib1fvARB, NULL, _gloffset_VertexAttrib1fvARB), + NAME_FUNC_OFFSET(15995, glVertexAttrib1sARB, glVertexAttrib1sARB, NULL, _gloffset_VertexAttrib1sARB), + NAME_FUNC_OFFSET(16012, glVertexAttrib1svARB, glVertexAttrib1svARB, NULL, _gloffset_VertexAttrib1svARB), + NAME_FUNC_OFFSET(16030, glVertexAttrib2dARB, glVertexAttrib2dARB, NULL, _gloffset_VertexAttrib2dARB), + NAME_FUNC_OFFSET(16047, glVertexAttrib2dvARB, glVertexAttrib2dvARB, NULL, _gloffset_VertexAttrib2dvARB), + NAME_FUNC_OFFSET(16065, glVertexAttrib2fARB, glVertexAttrib2fARB, NULL, _gloffset_VertexAttrib2fARB), + NAME_FUNC_OFFSET(16082, glVertexAttrib2fvARB, glVertexAttrib2fvARB, NULL, _gloffset_VertexAttrib2fvARB), + NAME_FUNC_OFFSET(16100, glVertexAttrib2sARB, glVertexAttrib2sARB, NULL, _gloffset_VertexAttrib2sARB), + NAME_FUNC_OFFSET(16117, glVertexAttrib2svARB, glVertexAttrib2svARB, NULL, _gloffset_VertexAttrib2svARB), + NAME_FUNC_OFFSET(16135, glVertexAttrib3dARB, glVertexAttrib3dARB, NULL, _gloffset_VertexAttrib3dARB), + NAME_FUNC_OFFSET(16152, glVertexAttrib3dvARB, glVertexAttrib3dvARB, NULL, _gloffset_VertexAttrib3dvARB), + NAME_FUNC_OFFSET(16170, glVertexAttrib3fARB, glVertexAttrib3fARB, NULL, _gloffset_VertexAttrib3fARB), + NAME_FUNC_OFFSET(16187, glVertexAttrib3fvARB, glVertexAttrib3fvARB, NULL, _gloffset_VertexAttrib3fvARB), + NAME_FUNC_OFFSET(16205, glVertexAttrib3sARB, glVertexAttrib3sARB, NULL, _gloffset_VertexAttrib3sARB), + NAME_FUNC_OFFSET(16222, glVertexAttrib3svARB, glVertexAttrib3svARB, NULL, _gloffset_VertexAttrib3svARB), + NAME_FUNC_OFFSET(16240, glVertexAttrib4NbvARB, glVertexAttrib4NbvARB, NULL, _gloffset_VertexAttrib4NbvARB), + NAME_FUNC_OFFSET(16259, glVertexAttrib4NivARB, glVertexAttrib4NivARB, NULL, _gloffset_VertexAttrib4NivARB), + NAME_FUNC_OFFSET(16278, glVertexAttrib4NsvARB, glVertexAttrib4NsvARB, NULL, _gloffset_VertexAttrib4NsvARB), + NAME_FUNC_OFFSET(16297, glVertexAttrib4NubARB, glVertexAttrib4NubARB, NULL, _gloffset_VertexAttrib4NubARB), + NAME_FUNC_OFFSET(16316, glVertexAttrib4NubvARB, glVertexAttrib4NubvARB, NULL, _gloffset_VertexAttrib4NubvARB), + NAME_FUNC_OFFSET(16336, glVertexAttrib4NuivARB, glVertexAttrib4NuivARB, NULL, _gloffset_VertexAttrib4NuivARB), + NAME_FUNC_OFFSET(16356, glVertexAttrib4NusvARB, glVertexAttrib4NusvARB, NULL, _gloffset_VertexAttrib4NusvARB), + NAME_FUNC_OFFSET(16376, glVertexAttrib4bvARB, glVertexAttrib4bvARB, NULL, _gloffset_VertexAttrib4bvARB), + NAME_FUNC_OFFSET(16394, glVertexAttrib4dARB, glVertexAttrib4dARB, NULL, _gloffset_VertexAttrib4dARB), + NAME_FUNC_OFFSET(16411, glVertexAttrib4dvARB, glVertexAttrib4dvARB, NULL, _gloffset_VertexAttrib4dvARB), + NAME_FUNC_OFFSET(16429, glVertexAttrib4fARB, glVertexAttrib4fARB, NULL, _gloffset_VertexAttrib4fARB), + NAME_FUNC_OFFSET(16446, glVertexAttrib4fvARB, glVertexAttrib4fvARB, NULL, _gloffset_VertexAttrib4fvARB), + NAME_FUNC_OFFSET(16464, glVertexAttrib4ivARB, glVertexAttrib4ivARB, NULL, _gloffset_VertexAttrib4ivARB), + NAME_FUNC_OFFSET(16482, glVertexAttrib4sARB, glVertexAttrib4sARB, NULL, _gloffset_VertexAttrib4sARB), + NAME_FUNC_OFFSET(16499, glVertexAttrib4svARB, glVertexAttrib4svARB, NULL, _gloffset_VertexAttrib4svARB), + NAME_FUNC_OFFSET(16517, glVertexAttrib4ubvARB, glVertexAttrib4ubvARB, NULL, _gloffset_VertexAttrib4ubvARB), + NAME_FUNC_OFFSET(16536, glVertexAttrib4uivARB, glVertexAttrib4uivARB, NULL, _gloffset_VertexAttrib4uivARB), + NAME_FUNC_OFFSET(16555, glVertexAttrib4usvARB, glVertexAttrib4usvARB, NULL, _gloffset_VertexAttrib4usvARB), + NAME_FUNC_OFFSET(16574, glVertexAttribPointerARB, glVertexAttribPointerARB, NULL, _gloffset_VertexAttribPointerARB), + NAME_FUNC_OFFSET(16596, glBindBufferARB, glBindBufferARB, NULL, _gloffset_BindBufferARB), + NAME_FUNC_OFFSET(16609, glBufferDataARB, glBufferDataARB, NULL, _gloffset_BufferDataARB), + NAME_FUNC_OFFSET(16622, glBufferSubDataARB, glBufferSubDataARB, NULL, _gloffset_BufferSubDataARB), + NAME_FUNC_OFFSET(16638, glDeleteBuffersARB, glDeleteBuffersARB, NULL, _gloffset_DeleteBuffersARB), + NAME_FUNC_OFFSET(16654, glGenBuffersARB, glGenBuffersARB, NULL, _gloffset_GenBuffersARB), + NAME_FUNC_OFFSET(16667, glGetBufferParameterivARB, glGetBufferParameterivARB, NULL, _gloffset_GetBufferParameterivARB), + NAME_FUNC_OFFSET(16690, glGetBufferPointervARB, glGetBufferPointervARB, NULL, _gloffset_GetBufferPointervARB), + NAME_FUNC_OFFSET(16710, glGetBufferSubDataARB, glGetBufferSubDataARB, NULL, _gloffset_GetBufferSubDataARB), + NAME_FUNC_OFFSET(16729, glIsBufferARB, glIsBufferARB, NULL, _gloffset_IsBufferARB), + NAME_FUNC_OFFSET(16740, glMapBufferARB, glMapBufferARB, NULL, _gloffset_MapBufferARB), + NAME_FUNC_OFFSET(16752, glUnmapBufferARB, glUnmapBufferARB, NULL, _gloffset_UnmapBufferARB), + NAME_FUNC_OFFSET(16766, glBeginQueryARB, glBeginQueryARB, NULL, _gloffset_BeginQueryARB), + NAME_FUNC_OFFSET(16779, glDeleteQueriesARB, glDeleteQueriesARB, NULL, _gloffset_DeleteQueriesARB), + NAME_FUNC_OFFSET(16795, glEndQueryARB, glEndQueryARB, NULL, _gloffset_EndQueryARB), + NAME_FUNC_OFFSET(16806, glGenQueriesARB, glGenQueriesARB, NULL, _gloffset_GenQueriesARB), + NAME_FUNC_OFFSET(16819, glGetQueryObjectivARB, glGetQueryObjectivARB, NULL, _gloffset_GetQueryObjectivARB), + NAME_FUNC_OFFSET(16838, glGetQueryObjectuivARB, glGetQueryObjectuivARB, NULL, _gloffset_GetQueryObjectuivARB), + NAME_FUNC_OFFSET(16858, glGetQueryivARB, glGetQueryivARB, NULL, _gloffset_GetQueryivARB), + NAME_FUNC_OFFSET(16871, glIsQueryARB, glIsQueryARB, NULL, _gloffset_IsQueryARB), + NAME_FUNC_OFFSET(16881, glCompileShaderARB, glCompileShaderARB, NULL, _gloffset_CompileShaderARB), + NAME_FUNC_OFFSET(16897, glGetActiveUniformARB, glGetActiveUniformARB, NULL, _gloffset_GetActiveUniformARB), + NAME_FUNC_OFFSET(16916, glGetShaderSourceARB, glGetShaderSourceARB, NULL, _gloffset_GetShaderSourceARB), + NAME_FUNC_OFFSET(16934, glGetUniformLocationARB, glGetUniformLocationARB, NULL, _gloffset_GetUniformLocationARB), + NAME_FUNC_OFFSET(16955, glGetUniformfvARB, glGetUniformfvARB, NULL, _gloffset_GetUniformfvARB), + NAME_FUNC_OFFSET(16970, glGetUniformivARB, glGetUniformivARB, NULL, _gloffset_GetUniformivARB), + NAME_FUNC_OFFSET(16985, glLinkProgramARB, glLinkProgramARB, NULL, _gloffset_LinkProgramARB), + NAME_FUNC_OFFSET(16999, glShaderSourceARB, glShaderSourceARB, NULL, _gloffset_ShaderSourceARB), + NAME_FUNC_OFFSET(17014, glUniform1fARB, glUniform1fARB, NULL, _gloffset_Uniform1fARB), + NAME_FUNC_OFFSET(17026, glUniform1fvARB, glUniform1fvARB, NULL, _gloffset_Uniform1fvARB), + NAME_FUNC_OFFSET(17039, glUniform1iARB, glUniform1iARB, NULL, _gloffset_Uniform1iARB), + NAME_FUNC_OFFSET(17051, glUniform1ivARB, glUniform1ivARB, NULL, _gloffset_Uniform1ivARB), + NAME_FUNC_OFFSET(17064, glUniform2fARB, glUniform2fARB, NULL, _gloffset_Uniform2fARB), + NAME_FUNC_OFFSET(17076, glUniform2fvARB, glUniform2fvARB, NULL, _gloffset_Uniform2fvARB), + NAME_FUNC_OFFSET(17089, glUniform2iARB, glUniform2iARB, NULL, _gloffset_Uniform2iARB), + NAME_FUNC_OFFSET(17101, glUniform2ivARB, glUniform2ivARB, NULL, _gloffset_Uniform2ivARB), + NAME_FUNC_OFFSET(17114, glUniform3fARB, glUniform3fARB, NULL, _gloffset_Uniform3fARB), + NAME_FUNC_OFFSET(17126, glUniform3fvARB, glUniform3fvARB, NULL, _gloffset_Uniform3fvARB), + NAME_FUNC_OFFSET(17139, glUniform3iARB, glUniform3iARB, NULL, _gloffset_Uniform3iARB), + NAME_FUNC_OFFSET(17151, glUniform3ivARB, glUniform3ivARB, NULL, _gloffset_Uniform3ivARB), + NAME_FUNC_OFFSET(17164, glUniform4fARB, glUniform4fARB, NULL, _gloffset_Uniform4fARB), + NAME_FUNC_OFFSET(17176, glUniform4fvARB, glUniform4fvARB, NULL, _gloffset_Uniform4fvARB), + NAME_FUNC_OFFSET(17189, glUniform4iARB, glUniform4iARB, NULL, _gloffset_Uniform4iARB), + NAME_FUNC_OFFSET(17201, glUniform4ivARB, glUniform4ivARB, NULL, _gloffset_Uniform4ivARB), + NAME_FUNC_OFFSET(17214, glUniformMatrix2fvARB, glUniformMatrix2fvARB, NULL, _gloffset_UniformMatrix2fvARB), + NAME_FUNC_OFFSET(17233, glUniformMatrix3fvARB, glUniformMatrix3fvARB, NULL, _gloffset_UniformMatrix3fvARB), + NAME_FUNC_OFFSET(17252, glUniformMatrix4fvARB, glUniformMatrix4fvARB, NULL, _gloffset_UniformMatrix4fvARB), + NAME_FUNC_OFFSET(17271, glUseProgramObjectARB, glUseProgramObjectARB, NULL, _gloffset_UseProgramObjectARB), + NAME_FUNC_OFFSET(17284, glValidateProgramARB, glValidateProgramARB, NULL, _gloffset_ValidateProgramARB), + NAME_FUNC_OFFSET(17302, glBindAttribLocationARB, glBindAttribLocationARB, NULL, _gloffset_BindAttribLocationARB), + NAME_FUNC_OFFSET(17323, glGetActiveAttribARB, glGetActiveAttribARB, NULL, _gloffset_GetActiveAttribARB), + NAME_FUNC_OFFSET(17341, glGetAttribLocationARB, glGetAttribLocationARB, NULL, _gloffset_GetAttribLocationARB), + NAME_FUNC_OFFSET(17361, glDrawBuffersARB, glDrawBuffersARB, NULL, _gloffset_DrawBuffersARB), + NAME_FUNC_OFFSET(17375, glDrawBuffersARB, glDrawBuffersARB, NULL, _gloffset_DrawBuffersARB), + NAME_FUNC_OFFSET(17392, gl_dispatch_stub_568, gl_dispatch_stub_568, NULL, _gloffset_SampleMaskSGIS), + NAME_FUNC_OFFSET(17408, gl_dispatch_stub_569, gl_dispatch_stub_569, NULL, _gloffset_SamplePatternSGIS), + NAME_FUNC_OFFSET(17427, glPointParameterfEXT, glPointParameterfEXT, NULL, _gloffset_PointParameterfEXT), + NAME_FUNC_OFFSET(17445, glPointParameterfEXT, glPointParameterfEXT, NULL, _gloffset_PointParameterfEXT), + NAME_FUNC_OFFSET(17466, glPointParameterfEXT, glPointParameterfEXT, NULL, _gloffset_PointParameterfEXT), + NAME_FUNC_OFFSET(17488, glPointParameterfvEXT, glPointParameterfvEXT, NULL, _gloffset_PointParameterfvEXT), + NAME_FUNC_OFFSET(17507, glPointParameterfvEXT, glPointParameterfvEXT, NULL, _gloffset_PointParameterfvEXT), + NAME_FUNC_OFFSET(17529, glPointParameterfvEXT, glPointParameterfvEXT, NULL, _gloffset_PointParameterfvEXT), + NAME_FUNC_OFFSET(17552, glSecondaryColor3bEXT, glSecondaryColor3bEXT, NULL, _gloffset_SecondaryColor3bEXT), + NAME_FUNC_OFFSET(17571, glSecondaryColor3bvEXT, glSecondaryColor3bvEXT, NULL, _gloffset_SecondaryColor3bvEXT), + NAME_FUNC_OFFSET(17591, glSecondaryColor3dEXT, glSecondaryColor3dEXT, NULL, _gloffset_SecondaryColor3dEXT), + NAME_FUNC_OFFSET(17610, glSecondaryColor3dvEXT, glSecondaryColor3dvEXT, NULL, _gloffset_SecondaryColor3dvEXT), + NAME_FUNC_OFFSET(17630, glSecondaryColor3fEXT, glSecondaryColor3fEXT, NULL, _gloffset_SecondaryColor3fEXT), + NAME_FUNC_OFFSET(17649, glSecondaryColor3fvEXT, glSecondaryColor3fvEXT, NULL, _gloffset_SecondaryColor3fvEXT), + NAME_FUNC_OFFSET(17669, glSecondaryColor3iEXT, glSecondaryColor3iEXT, NULL, _gloffset_SecondaryColor3iEXT), + NAME_FUNC_OFFSET(17688, glSecondaryColor3ivEXT, glSecondaryColor3ivEXT, NULL, _gloffset_SecondaryColor3ivEXT), + NAME_FUNC_OFFSET(17708, glSecondaryColor3sEXT, glSecondaryColor3sEXT, NULL, _gloffset_SecondaryColor3sEXT), + NAME_FUNC_OFFSET(17727, glSecondaryColor3svEXT, glSecondaryColor3svEXT, NULL, _gloffset_SecondaryColor3svEXT), + NAME_FUNC_OFFSET(17747, glSecondaryColor3ubEXT, glSecondaryColor3ubEXT, NULL, _gloffset_SecondaryColor3ubEXT), + NAME_FUNC_OFFSET(17767, glSecondaryColor3ubvEXT, glSecondaryColor3ubvEXT, NULL, _gloffset_SecondaryColor3ubvEXT), + NAME_FUNC_OFFSET(17788, glSecondaryColor3uiEXT, glSecondaryColor3uiEXT, NULL, _gloffset_SecondaryColor3uiEXT), + NAME_FUNC_OFFSET(17808, glSecondaryColor3uivEXT, glSecondaryColor3uivEXT, NULL, _gloffset_SecondaryColor3uivEXT), + NAME_FUNC_OFFSET(17829, glSecondaryColor3usEXT, glSecondaryColor3usEXT, NULL, _gloffset_SecondaryColor3usEXT), + NAME_FUNC_OFFSET(17849, glSecondaryColor3usvEXT, glSecondaryColor3usvEXT, NULL, _gloffset_SecondaryColor3usvEXT), + NAME_FUNC_OFFSET(17870, glSecondaryColorPointerEXT, glSecondaryColorPointerEXT, NULL, _gloffset_SecondaryColorPointerEXT), + NAME_FUNC_OFFSET(17894, glMultiDrawArraysEXT, glMultiDrawArraysEXT, NULL, _gloffset_MultiDrawArraysEXT), + NAME_FUNC_OFFSET(17912, glMultiDrawElementsEXT, glMultiDrawElementsEXT, NULL, _gloffset_MultiDrawElementsEXT), + NAME_FUNC_OFFSET(17932, glFogCoordPointerEXT, glFogCoordPointerEXT, NULL, _gloffset_FogCoordPointerEXT), + NAME_FUNC_OFFSET(17950, glFogCoorddEXT, glFogCoorddEXT, NULL, _gloffset_FogCoorddEXT), + NAME_FUNC_OFFSET(17962, glFogCoorddvEXT, glFogCoorddvEXT, NULL, _gloffset_FogCoorddvEXT), + NAME_FUNC_OFFSET(17975, glFogCoordfEXT, glFogCoordfEXT, NULL, _gloffset_FogCoordfEXT), + NAME_FUNC_OFFSET(17987, glFogCoordfvEXT, glFogCoordfvEXT, NULL, _gloffset_FogCoordfvEXT), + NAME_FUNC_OFFSET(18000, glBlendFuncSeparateEXT, glBlendFuncSeparateEXT, NULL, _gloffset_BlendFuncSeparateEXT), + NAME_FUNC_OFFSET(18020, glBlendFuncSeparateEXT, glBlendFuncSeparateEXT, NULL, _gloffset_BlendFuncSeparateEXT), + NAME_FUNC_OFFSET(18044, glWindowPos2dMESA, glWindowPos2dMESA, NULL, _gloffset_WindowPos2dMESA), + NAME_FUNC_OFFSET(18058, glWindowPos2dMESA, glWindowPos2dMESA, NULL, _gloffset_WindowPos2dMESA), + NAME_FUNC_OFFSET(18075, glWindowPos2dvMESA, glWindowPos2dvMESA, NULL, _gloffset_WindowPos2dvMESA), + NAME_FUNC_OFFSET(18090, glWindowPos2dvMESA, glWindowPos2dvMESA, NULL, _gloffset_WindowPos2dvMESA), + NAME_FUNC_OFFSET(18108, glWindowPos2fMESA, glWindowPos2fMESA, NULL, _gloffset_WindowPos2fMESA), + NAME_FUNC_OFFSET(18122, glWindowPos2fMESA, glWindowPos2fMESA, NULL, _gloffset_WindowPos2fMESA), + NAME_FUNC_OFFSET(18139, glWindowPos2fvMESA, glWindowPos2fvMESA, NULL, _gloffset_WindowPos2fvMESA), + NAME_FUNC_OFFSET(18154, glWindowPos2fvMESA, glWindowPos2fvMESA, NULL, _gloffset_WindowPos2fvMESA), + NAME_FUNC_OFFSET(18172, glWindowPos2iMESA, glWindowPos2iMESA, NULL, _gloffset_WindowPos2iMESA), + NAME_FUNC_OFFSET(18186, glWindowPos2iMESA, glWindowPos2iMESA, NULL, _gloffset_WindowPos2iMESA), + NAME_FUNC_OFFSET(18203, glWindowPos2ivMESA, glWindowPos2ivMESA, NULL, _gloffset_WindowPos2ivMESA), + NAME_FUNC_OFFSET(18218, glWindowPos2ivMESA, glWindowPos2ivMESA, NULL, _gloffset_WindowPos2ivMESA), + NAME_FUNC_OFFSET(18236, glWindowPos2sMESA, glWindowPos2sMESA, NULL, _gloffset_WindowPos2sMESA), + NAME_FUNC_OFFSET(18250, glWindowPos2sMESA, glWindowPos2sMESA, NULL, _gloffset_WindowPos2sMESA), + NAME_FUNC_OFFSET(18267, glWindowPos2svMESA, glWindowPos2svMESA, NULL, _gloffset_WindowPos2svMESA), + NAME_FUNC_OFFSET(18282, glWindowPos2svMESA, glWindowPos2svMESA, NULL, _gloffset_WindowPos2svMESA), + NAME_FUNC_OFFSET(18300, glWindowPos3dMESA, glWindowPos3dMESA, NULL, _gloffset_WindowPos3dMESA), + NAME_FUNC_OFFSET(18314, glWindowPos3dMESA, glWindowPos3dMESA, NULL, _gloffset_WindowPos3dMESA), + NAME_FUNC_OFFSET(18331, glWindowPos3dvMESA, glWindowPos3dvMESA, NULL, _gloffset_WindowPos3dvMESA), + NAME_FUNC_OFFSET(18346, glWindowPos3dvMESA, glWindowPos3dvMESA, NULL, _gloffset_WindowPos3dvMESA), + NAME_FUNC_OFFSET(18364, glWindowPos3fMESA, glWindowPos3fMESA, NULL, _gloffset_WindowPos3fMESA), + NAME_FUNC_OFFSET(18378, glWindowPos3fMESA, glWindowPos3fMESA, NULL, _gloffset_WindowPos3fMESA), + NAME_FUNC_OFFSET(18395, glWindowPos3fvMESA, glWindowPos3fvMESA, NULL, _gloffset_WindowPos3fvMESA), + NAME_FUNC_OFFSET(18410, glWindowPos3fvMESA, glWindowPos3fvMESA, NULL, _gloffset_WindowPos3fvMESA), + NAME_FUNC_OFFSET(18428, glWindowPos3iMESA, glWindowPos3iMESA, NULL, _gloffset_WindowPos3iMESA), + NAME_FUNC_OFFSET(18442, glWindowPos3iMESA, glWindowPos3iMESA, NULL, _gloffset_WindowPos3iMESA), + NAME_FUNC_OFFSET(18459, glWindowPos3ivMESA, glWindowPos3ivMESA, NULL, _gloffset_WindowPos3ivMESA), + NAME_FUNC_OFFSET(18474, glWindowPos3ivMESA, glWindowPos3ivMESA, NULL, _gloffset_WindowPos3ivMESA), + NAME_FUNC_OFFSET(18492, glWindowPos3sMESA, glWindowPos3sMESA, NULL, _gloffset_WindowPos3sMESA), + NAME_FUNC_OFFSET(18506, glWindowPos3sMESA, glWindowPos3sMESA, NULL, _gloffset_WindowPos3sMESA), + NAME_FUNC_OFFSET(18523, glWindowPos3svMESA, glWindowPos3svMESA, NULL, _gloffset_WindowPos3svMESA), + NAME_FUNC_OFFSET(18538, glWindowPos3svMESA, glWindowPos3svMESA, NULL, _gloffset_WindowPos3svMESA), + NAME_FUNC_OFFSET(18556, glBindProgramNV, glBindProgramNV, NULL, _gloffset_BindProgramNV), + NAME_FUNC_OFFSET(18573, glDeleteProgramsNV, glDeleteProgramsNV, NULL, _gloffset_DeleteProgramsNV), + NAME_FUNC_OFFSET(18593, glGenProgramsNV, glGenProgramsNV, NULL, _gloffset_GenProgramsNV), + NAME_FUNC_OFFSET(18610, glGetVertexAttribPointervNV, glGetVertexAttribPointervNV, NULL, _gloffset_GetVertexAttribPointervNV), + NAME_FUNC_OFFSET(18636, glGetVertexAttribPointervNV, glGetVertexAttribPointervNV, NULL, _gloffset_GetVertexAttribPointervNV), + NAME_FUNC_OFFSET(18665, glIsProgramNV, glIsProgramNV, NULL, _gloffset_IsProgramNV), + NAME_FUNC_OFFSET(18680, glPointParameteriNV, glPointParameteriNV, NULL, _gloffset_PointParameteriNV), + NAME_FUNC_OFFSET(18698, glPointParameterivNV, glPointParameterivNV, NULL, _gloffset_PointParameterivNV), + NAME_FUNC_OFFSET(18717, gl_dispatch_stub_749, gl_dispatch_stub_749, NULL, _gloffset_BlendEquationSeparateEXT), + NAME_FUNC_OFFSET(18741, gl_dispatch_stub_749, gl_dispatch_stub_749, NULL, _gloffset_BlendEquationSeparateEXT), NAME_FUNC_OFFSET(-1, NULL, NULL, NULL, 0) }; diff --git a/reactos/dll/3rdparty/mesa32/src/main/api_validate.c b/reactos/dll/3rdparty/mesa32/src/main/api_validate.c index 841c6a53026..7d75cd796bc 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/api_validate.c +++ b/reactos/dll/3rdparty/mesa32/src/main/api_validate.c @@ -1,6 +1,6 @@ /* * Mesa 3-D graphics library - * Version: 7.0.1 + * Version: 7.0.2 * * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. * @@ -30,6 +30,55 @@ #include "state.h" +/** + * Find the max index in the given element/index buffer + */ +static GLuint +max_buffer_index(GLcontext *ctx, GLuint count, GLenum type, + const void *indices, + struct gl_buffer_object *elementBuf) +{ + const GLubyte *map = NULL; + GLuint max = 0; + GLint i; + + if (elementBuf->Name) { + /* elements are in a user-defined buffer object. need to map it */ + map = ctx->Driver.MapBuffer(ctx, + GL_ELEMENT_ARRAY_BUFFER_ARB, + GL_READ_ONLY, + elementBuf); + /* Actual address is the sum of pointers */ + indices = (const GLvoid *) ADD_POINTERS(map, (const GLubyte *) indices); + } + + if (type == GL_UNSIGNED_INT) { + for (i = 0; i < count; i++) + if (((GLuint *) indices)[i] > max) + max = ((GLuint *) indices)[i]; + } + else if (type == GL_UNSIGNED_SHORT) { + for (i = 0; i < count; i++) + if (((GLushort *) indices)[i] > max) + max = ((GLushort *) indices)[i]; + } + else { + ASSERT(type == GL_UNSIGNED_BYTE); + for (i = 0; i < count; i++) + if (((GLubyte *) indices)[i] > max) + max = ((GLubyte *) indices)[i]; + } + + if (map) { + ctx->Driver.UnmapBuffer(ctx, + GL_ELEMENT_ARRAY_BUFFER_ARB, + ctx->Array.ElementArrayBufferObj); + } + + return max; +} + + GLboolean _mesa_validate_DrawElements(GLcontext *ctx, GLenum mode, GLsizei count, GLenum type, @@ -61,20 +110,15 @@ _mesa_validate_DrawElements(GLcontext *ctx, /* Always need vertex positions */ if (!ctx->Array.ArrayObj->Vertex.Enabled - && !(ctx->VertexProgram._Enabled && ctx->Array.ArrayObj->VertexAttrib[0].Enabled)) + && !(ctx->VertexProgram._Enabled + && ctx->Array.ArrayObj->VertexAttrib[0].Enabled)) return GL_FALSE; /* Vertex buffer object tests */ if (ctx->Array.ElementArrayBufferObj->Name) { + /* use indices in the buffer object */ GLuint indexBytes; - /* use indices in the buffer object */ - if (!ctx->Array.ElementArrayBufferObj->Data) { - _mesa_warning(ctx, "DrawElements with empty vertex elements buffer!"); - return GL_FALSE; - } - - /* make sure count doesn't go outside buffer bounds */ if (type == GL_UNSIGNED_INT) { indexBytes = count * sizeof(GLuint); } @@ -86,19 +130,11 @@ _mesa_validate_DrawElements(GLcontext *ctx, indexBytes = count * sizeof(GLushort); } - if ((GLubyte *) indices + indexBytes > - ctx->Array.ElementArrayBufferObj->Data + - ctx->Array.ElementArrayBufferObj->Size) { + /* make sure count doesn't go outside buffer bounds */ + if (indexBytes > ctx->Array.ElementArrayBufferObj->Size) { _mesa_warning(ctx, "glDrawElements index out of buffer bounds"); return GL_FALSE; } - - /* Actual address is the sum of pointers. Indices may be used below. */ - if (ctx->Const.CheckArrayBounds) { - indices = (const GLvoid *) - ADD_POINTERS(ctx->Array.ElementArrayBufferObj->Data, - (const GLubyte *) indices); - } } else { /* not using a VBO */ @@ -108,24 +144,8 @@ _mesa_validate_DrawElements(GLcontext *ctx, if (ctx->Const.CheckArrayBounds) { /* find max array index */ - GLuint max = 0; - GLint i; - if (type == GL_UNSIGNED_INT) { - for (i = 0; i < count; i++) - if (((GLuint *) indices)[i] > max) - max = ((GLuint *) indices)[i]; - } - else if (type == GL_UNSIGNED_SHORT) { - for (i = 0; i < count; i++) - if (((GLushort *) indices)[i] > max) - max = ((GLushort *) indices)[i]; - } - else { - ASSERT(type == GL_UNSIGNED_BYTE); - for (i = 0; i < count; i++) - if (((GLubyte *) indices)[i] > max) - max = ((GLubyte *) indices)[i]; - } + GLuint max = max_buffer_index(ctx, count, type, indices, + ctx->Array.ElementArrayBufferObj); if (max >= ctx->Array._MaxElement) { /* the max element is out of bounds of one or more enabled arrays */ return GL_FALSE; @@ -172,41 +192,41 @@ _mesa_validate_DrawRangeElements(GLcontext *ctx, GLenum mode, /* Always need vertex positions */ if (!ctx->Array.ArrayObj->Vertex.Enabled - && !(ctx->VertexProgram._Enabled && ctx->Array.ArrayObj->VertexAttrib[0].Enabled)) + && !(ctx->VertexProgram._Enabled + && ctx->Array.ArrayObj->VertexAttrib[0].Enabled)) return GL_FALSE; /* Vertex buffer object tests */ if (ctx->Array.ElementArrayBufferObj->Name) { - /* XXX re-use code from above? */ + /* use indices in the buffer object */ + GLuint indexBytes; + + if (type == GL_UNSIGNED_INT) { + indexBytes = count * sizeof(GLuint); + } + else if (type == GL_UNSIGNED_BYTE) { + indexBytes = count * sizeof(GLubyte); + } + else { + ASSERT(type == GL_UNSIGNED_SHORT); + indexBytes = count * sizeof(GLushort); + } + + /* make sure count doesn't go outside buffer bounds */ + if (indexBytes > ctx->Array.ElementArrayBufferObj->Size) { + _mesa_warning(ctx, "glDrawRangeElements index out of buffer bounds"); + return GL_FALSE; + } } else { - /* not using VBO */ + /* not using a VBO */ if (!indices) return GL_FALSE; } if (ctx->Const.CheckArrayBounds) { - /* Find max array index. - * We don't trust the user's start and end values. - */ - GLuint max = 0; - GLint i; - if (type == GL_UNSIGNED_INT) { - for (i = 0; i < count; i++) - if (((GLuint *) indices)[i] > max) - max = ((GLuint *) indices)[i]; - } - else if (type == GL_UNSIGNED_SHORT) { - for (i = 0; i < count; i++) - if (((GLushort *) indices)[i] > max) - max = ((GLushort *) indices)[i]; - } - else { - ASSERT(type == GL_UNSIGNED_BYTE); - for (i = 0; i < count; i++) - if (((GLubyte *) indices)[i] > max) - max = ((GLubyte *) indices)[i]; - } + GLuint max = max_buffer_index(ctx, count, type, indices, + ctx->Array.ElementArrayBufferObj); if (max >= ctx->Array._MaxElement) { /* the max element is out of bounds of one or more enabled arrays */ return GL_FALSE; @@ -227,8 +247,9 @@ _mesa_validate_DrawArrays(GLcontext *ctx, { ASSERT_OUTSIDE_BEGIN_END_WITH_RETVAL(ctx, GL_FALSE); - if (count < 0) { - _mesa_error(ctx, GL_INVALID_VALUE, "glDrawArrays(count)" ); + if (count <= 0) { + if (count < 0) + _mesa_error(ctx, GL_INVALID_VALUE, "glDrawArrays(count)" ); return GL_FALSE; } @@ -241,7 +262,8 @@ _mesa_validate_DrawArrays(GLcontext *ctx, _mesa_update_state(ctx); /* Always need vertex positions */ - if (!ctx->Array.ArrayObj->Vertex.Enabled && !ctx->Array.ArrayObj->VertexAttrib[0].Enabled) + if (!ctx->Array.ArrayObj->Vertex.Enabled + && !ctx->Array.ArrayObj->VertexAttrib[0].Enabled) return GL_FALSE; if (ctx->Const.CheckArrayBounds) { diff --git a/reactos/dll/3rdparty/mesa32/src/main/attrib.c b/reactos/dll/3rdparty/mesa32/src/main/attrib.c index 0b821cff44d..8ddfda8ba04 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/attrib.c +++ b/reactos/dll/3rdparty/mesa32/src/main/attrib.c @@ -1,6 +1,6 @@ /* * Mesa 3-D graphics library - * Version: 6.5.3 + * Version: 7.0.2 * * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. * @@ -51,6 +51,32 @@ #include "math/m_xform.h" +/** + * Special struct for saving/restoring texture state (GL_TEXTURE_BIT) + */ +struct texture_state +{ + struct gl_texture_attrib Texture; /**< The usual context state */ + + /** to save per texture object state (wrap modes, filters, etc): */ + struct gl_texture_object Saved1D[MAX_TEXTURE_UNITS]; + struct gl_texture_object Saved2D[MAX_TEXTURE_UNITS]; + struct gl_texture_object Saved3D[MAX_TEXTURE_UNITS]; + struct gl_texture_object SavedCube[MAX_TEXTURE_UNITS]; + struct gl_texture_object SavedRect[MAX_TEXTURE_UNITS]; + + /** + * To save references to texture objects (so they don't get accidentally + * deleted while saved in the attribute stack). + */ + struct gl_texture_object *SavedRef1D[MAX_TEXTURE_UNITS]; + struct gl_texture_object *SavedRef2D[MAX_TEXTURE_UNITS]; + struct gl_texture_object *SavedRef3D[MAX_TEXTURE_UNITS]; + struct gl_texture_object *SavedRefCube[MAX_TEXTURE_UNITS]; + struct gl_texture_object *SavedRefRect[MAX_TEXTURE_UNITS]; +}; + + /** * Allocate a new attribute state node. These nodes have a * "kind" value and a pointer to a struct of state data. @@ -335,40 +361,48 @@ _mesa_PushAttrib(GLbitfield mask) } if (mask & GL_TEXTURE_BIT) { - struct gl_texture_attrib *attr; + struct texture_state *texstate = CALLOC_STRUCT( texture_state ); GLuint u; + if (!texstate) { + _mesa_error(ctx, GL_OUT_OF_MEMORY, "glPushAttrib(GL_TEXTURE_BIT)"); + goto end; + } + _mesa_lock_context_textures(ctx); - /* Bump the texture object reference counts so that they don't - * inadvertantly get deleted. + + /* copy/save the bulk of texture state here */ + _mesa_memcpy(&texstate->Texture, &ctx->Texture, sizeof(ctx->Texture)); + + /* Save references to the currently bound texture objects so they don't + * accidentally get deleted while referenced in the attribute stack. */ for (u = 0; u < ctx->Const.MaxTextureUnits; u++) { - ctx->Texture.Unit[u].Current1D->RefCount++; - ctx->Texture.Unit[u].Current2D->RefCount++; - ctx->Texture.Unit[u].Current3D->RefCount++; - ctx->Texture.Unit[u].CurrentCubeMap->RefCount++; - ctx->Texture.Unit[u].CurrentRect->RefCount++; + _mesa_reference_texobj(&texstate->SavedRef1D[u], ctx->Texture.Unit[u].Current1D); + _mesa_reference_texobj(&texstate->SavedRef2D[u], ctx->Texture.Unit[u].Current2D); + _mesa_reference_texobj(&texstate->SavedRef3D[u], ctx->Texture.Unit[u].Current3D); + _mesa_reference_texobj(&texstate->SavedRefCube[u], ctx->Texture.Unit[u].CurrentCubeMap); + _mesa_reference_texobj(&texstate->SavedRefRect[u], ctx->Texture.Unit[u].CurrentRect); } - attr = MALLOC_STRUCT( gl_texture_attrib ); - MEMCPY( attr, &ctx->Texture, sizeof(struct gl_texture_attrib) ); - /* copy state of the currently bound texture objects */ + + /* copy state/contents of the currently bound texture objects */ for (u = 0; u < ctx->Const.MaxTextureUnits; u++) { - _mesa_copy_texture_object(&attr->Unit[u].Saved1D, - attr->Unit[u].Current1D); - _mesa_copy_texture_object(&attr->Unit[u].Saved2D, - attr->Unit[u].Current2D); - _mesa_copy_texture_object(&attr->Unit[u].Saved3D, - attr->Unit[u].Current3D); - _mesa_copy_texture_object(&attr->Unit[u].SavedCubeMap, - attr->Unit[u].CurrentCubeMap); - _mesa_copy_texture_object(&attr->Unit[u].SavedRect, - attr->Unit[u].CurrentRect); + _mesa_copy_texture_object(&texstate->Saved1D[u], + ctx->Texture.Unit[u].Current1D); + _mesa_copy_texture_object(&texstate->Saved2D[u], + ctx->Texture.Unit[u].Current2D); + _mesa_copy_texture_object(&texstate->Saved3D[u], + ctx->Texture.Unit[u].Current3D); + _mesa_copy_texture_object(&texstate->SavedCube[u], + ctx->Texture.Unit[u].CurrentCubeMap); + _mesa_copy_texture_object(&texstate->SavedRect[u], + ctx->Texture.Unit[u].CurrentRect); } _mesa_unlock_context_textures(ctx); newnode = new_attrib_node( GL_TEXTURE_BIT ); - newnode->data = attr; + newnode->data = texstate; newnode->next = head; head = newnode; } @@ -404,6 +438,7 @@ _mesa_PushAttrib(GLbitfield mask) head = newnode; } +end: ctx->AttribStack[ctx->AttribStackDepth] = head; ctx->AttribStackDepth++; } @@ -613,14 +648,19 @@ pop_enable_group(GLcontext *ctx, const struct gl_enable_attrib *enable) } +/** + * Pop/restore texture attribute/group state. + */ static void -pop_texture_group(GLcontext *ctx, const struct gl_texture_attrib *texAttrib) +pop_texture_group(GLcontext *ctx, struct texture_state *texstate) { GLuint u; + _mesa_lock_context_textures(ctx); + for (u = 0; u < ctx->Const.MaxTextureUnits; u++) { - const struct gl_texture_unit *unit = &texAttrib->Unit[u]; - GLuint i; + const struct gl_texture_unit *unit = &texstate->Texture.Unit[u]; + GLuint tgt; _mesa_ActiveTextureARB(GL_TEXTURE0_ARB + u); _mesa_set_enable(ctx, GL_TEXTURE_1D, @@ -713,41 +753,44 @@ pop_texture_group(GLcontext *ctx, const struct gl_texture_attrib *texAttrib) 1 << unit->Combine.ScaleShiftA); } - /* Restore texture object state */ - for (i = 0; i < NUM_TEXTURE_TARGETS; i++) { - GLenum target = 0; + /* Restore texture object state for each target */ + for (tgt = 0; tgt < NUM_TEXTURE_TARGETS; tgt++) { const struct gl_texture_object *obj = NULL; GLfloat bordColor[4]; + GLenum target; - switch (i) { - case 0: - target = GL_TEXTURE_1D; - obj = &unit->Saved1D; + switch (tgt) { + case TEXTURE_1D_INDEX: + obj = &texstate->Saved1D[u]; + ASSERT(obj->Target == GL_TEXTURE_1D); break; - case 1: - target = GL_TEXTURE_2D; - obj = &unit->Saved2D; + case TEXTURE_2D_INDEX: + obj = &texstate->Saved2D[u]; + ASSERT(obj->Target == GL_TEXTURE_2D); break; - case 2: - target = GL_TEXTURE_3D; - obj = &unit->Saved3D; + case TEXTURE_3D_INDEX: + obj = &texstate->Saved3D[u]; + ASSERT(obj->Target == GL_TEXTURE_3D); break; - case 3: + case TEXTURE_CUBE_INDEX: if (!ctx->Extensions.ARB_texture_cube_map) continue; - target = GL_TEXTURE_CUBE_MAP_ARB; - obj = &unit->SavedCubeMap; + obj = &texstate->SavedCube[u]; + ASSERT(obj->Target == GL_TEXTURE_CUBE_MAP_ARB); break; - case 4: + case TEXTURE_RECT_INDEX: if (!ctx->Extensions.NV_texture_rectangle) continue; - target = GL_TEXTURE_RECTANGLE_NV; - obj = &unit->SavedRect; + obj = &texstate->SavedRect[u]; + ASSERT(obj->Target == GL_TEXTURE_RECTANGLE_NV); break; default: - ; /* silence warnings */ + _mesa_problem(ctx, "bad texture index in pop_texture_group"); + continue; } + target = obj->Target; + _mesa_BindTexture(target, obj->Name); bordColor[0] = CHAN_TO_FLOAT(obj->BorderColor[0]); @@ -782,23 +825,19 @@ pop_texture_group(GLcontext *ctx, const struct gl_texture_attrib *texAttrib) _mesa_TexParameterf(target, GL_SHADOW_AMBIENT_SGIX, obj->ShadowAmbient); } - } - } - _mesa_ActiveTextureARB(GL_TEXTURE0_ARB - + texAttrib->CurrentUnit); - /* "un-bump" the texture object reference counts. We did that so they - * wouldn't inadvertantly get deleted while they were still referenced - * inside the attribute state stack. - */ - for (u = 0; u < ctx->Const.MaxTextureUnits; u++) { - ctx->Texture.Unit[u].Current1D->RefCount--; - ctx->Texture.Unit[u].Current2D->RefCount--; - ctx->Texture.Unit[u].Current3D->RefCount--; - ctx->Texture.Unit[u].CurrentCubeMap->RefCount--; - ctx->Texture.Unit[u].CurrentRect->RefCount--; + /* remove saved references to the texture objects */ + _mesa_reference_texobj(&texstate->SavedRef1D[u], NULL); + _mesa_reference_texobj(&texstate->SavedRef2D[u], NULL); + _mesa_reference_texobj(&texstate->SavedRef3D[u], NULL); + _mesa_reference_texobj(&texstate->SavedRefCube[u], NULL); + _mesa_reference_texobj(&texstate->SavedRefRect[u], NULL); } + + _mesa_ActiveTextureARB(GL_TEXTURE0_ARB + texstate->Texture.CurrentUnit); + + _mesa_unlock_context_textures(ctx); } @@ -1067,7 +1106,8 @@ _mesa_PopAttrib(void) (GLint) point->CoordReplace[u]); } _mesa_set_enable(ctx, GL_POINT_SPRITE_NV,point->PointSprite); - _mesa_PointParameteriNV(GL_POINT_SPRITE_R_MODE_NV, + if (ctx->Extensions.NV_point_sprite) + _mesa_PointParameteriNV(GL_POINT_SPRITE_R_MODE_NV, ctx->Point.SpriteRMode); _mesa_PointParameterfEXT(GL_POINT_SPRITE_COORD_ORIGIN, (GLfloat)ctx->Point.SpriteOrigin); @@ -1177,9 +1217,9 @@ _mesa_PopAttrib(void) case GL_TEXTURE_BIT: /* Take care of texture object reference counters */ { - const struct gl_texture_attrib *texture; - texture = (const struct gl_texture_attrib *) attr->data; - pop_texture_group(ctx, texture); + struct texture_state *texstate + = (struct texture_state *) attr->data; + pop_texture_group(ctx, texstate); ctx->NewState |= _NEW_TEXTURE; } break; @@ -1401,6 +1441,41 @@ _mesa_PopClientAttrib(void) } +void +_mesa_free_attrib_data(GLcontext *ctx) +{ + while (ctx->AttribStackDepth > 0) { + struct gl_attrib_node *attr, *next; + + ctx->AttribStackDepth--; + attr = ctx->AttribStack[ctx->AttribStackDepth]; + + while (attr) { + if (attr->kind == GL_TEXTURE_BIT) { + struct texture_state *texstate = (struct texture_state*)attr->data; + GLuint u; + /* clear references to the saved texture objects */ + for (u = 0; u < ctx->Const.MaxTextureUnits; u++) { + _mesa_reference_texobj(&texstate->SavedRef1D[u], NULL); + _mesa_reference_texobj(&texstate->SavedRef2D[u], NULL); + _mesa_reference_texobj(&texstate->SavedRef3D[u], NULL); + _mesa_reference_texobj(&texstate->SavedRefCube[u], NULL); + _mesa_reference_texobj(&texstate->SavedRefRect[u], NULL); + } + } + else { + /* any other chunks of state that requires special handling? */ + } + + next = attr->next; + _mesa_free(attr->data); + _mesa_free(attr); + attr = next; + } + } +} + + void _mesa_init_attrib( GLcontext *ctx ) { /* Renderer and client attribute stacks */ diff --git a/reactos/dll/3rdparty/mesa32/src/main/attrib.h b/reactos/dll/3rdparty/mesa32/src/main/attrib.h index 09d75196b23..ea28859e9ff 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/attrib.h +++ b/reactos/dll/3rdparty/mesa32/src/main/attrib.h @@ -58,10 +58,14 @@ _mesa_PopClientAttrib( void ); extern void _mesa_init_attrib( GLcontext *ctx ); +extern void +_mesa_free_attrib_data( GLcontext *ctx ); + #else /** No-op */ #define _mesa_init_attrib( c ) ((void)0) +#define _mesa_free_attrib_data( c ) ((void)0) #endif diff --git a/reactos/dll/3rdparty/mesa32/src/main/context.c b/reactos/dll/3rdparty/mesa32/src/main/context.c index e067840e2fe..754b1a7d823 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/context.c +++ b/reactos/dll/3rdparty/mesa32/src/main/context.c @@ -6,7 +6,7 @@ /* * Mesa 3-D graphics library - * Version: 7.0 + * Version: 7.0.2 * * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. * @@ -467,17 +467,12 @@ alloc_shared_state( GLcontext *ctx ) if (!ss->DefaultRect) goto cleanup; - /* Effectively bind the default textures to all texture units */ - ss->Default1D->RefCount += MAX_TEXTURE_IMAGE_UNITS; - ss->Default2D->RefCount += MAX_TEXTURE_IMAGE_UNITS; - ss->Default3D->RefCount += MAX_TEXTURE_IMAGE_UNITS; - ss->DefaultCubeMap->RefCount += MAX_TEXTURE_IMAGE_UNITS; - ss->DefaultRect->RefCount += MAX_TEXTURE_IMAGE_UNITS; + /* sanity check */ + assert(ss->Default1D->RefCount == 1); _glthread_INIT_MUTEX(ss->TexMutex); ss->TextureStateStamp = 0; - #if FEATURE_EXT_framebuffer_object ss->FrameBuffers = _mesa_NewHashTable(); if (!ss->FrameBuffers) @@ -487,10 +482,9 @@ alloc_shared_state( GLcontext *ctx ) goto cleanup; #endif - return GL_TRUE; - cleanup: +cleanup: /* Ran out of memory at some point. Free everything and return NULL */ if (ss->DisplayList) _mesa_DeleteHashTable(ss->DisplayList); @@ -634,6 +628,33 @@ delete_shader_cb(GLuint id, void *data, void *userData) } } +/** + * Callback for deleting a framebuffer object. Called by _mesa_HashDeleteAll() + */ +static void +delete_framebuffer_cb(GLuint id, void *data, void *userData) +{ + struct gl_framebuffer *fb = (struct gl_framebuffer *) data; + /* The fact that the framebuffer is in the hashtable means its refcount + * is one, but we're removing from the hashtable now. So clear refcount. + */ + /*assert(fb->RefCount == 1);*/ + fb->RefCount = 0; + fb->Delete(fb); +} + +/** + * Callback for deleting a renderbuffer object. Called by _mesa_HashDeleteAll() + */ +static void +delete_renderbuffer_cb(GLuint id, void *data, void *userData) +{ + struct gl_renderbuffer *rb = (struct gl_renderbuffer *) data; + rb->RefCount = 0; /* see comment for FBOs above */ + rb->Delete(rb); +} + + /** * Deallocate a shared state object and all children structures. @@ -656,20 +677,6 @@ free_shared_state( GLcontext *ctx, struct gl_shared_state *ss ) _mesa_HashDeleteAll(ss->DisplayList, delete_displaylist_cb, ctx); _mesa_DeleteHashTable(ss->DisplayList); - /* - * Free texture objects - */ - ASSERT(ctx->Driver.DeleteTexture); - /* the default textures */ - ctx->Driver.DeleteTexture(ctx, ss->Default1D); - ctx->Driver.DeleteTexture(ctx, ss->Default2D); - ctx->Driver.DeleteTexture(ctx, ss->Default3D); - ctx->Driver.DeleteTexture(ctx, ss->DefaultCubeMap); - ctx->Driver.DeleteTexture(ctx, ss->DefaultRect); - /* all other textures */ - _mesa_HashDeleteAll(ss->TexObjects, delete_texture_cb, ctx); - _mesa_DeleteHashTable(ss->TexObjects); - #if defined(FEATURE_NV_vertex_program) || defined(FEATURE_NV_fragment_program) _mesa_HashDeleteAll(ss->Programs, delete_program_cb, ctx); _mesa_DeleteHashTable(ss->Programs); @@ -701,10 +708,27 @@ free_shared_state( GLcontext *ctx, struct gl_shared_state *ss ) #endif #if FEATURE_EXT_framebuffer_object + _mesa_HashDeleteAll(ss->FrameBuffers, delete_framebuffer_cb, ctx); _mesa_DeleteHashTable(ss->FrameBuffers); + _mesa_HashDeleteAll(ss->RenderBuffers, delete_renderbuffer_cb, ctx); _mesa_DeleteHashTable(ss->RenderBuffers); #endif + /* + * Free texture objects (after FBOs since some textures might have + * been bound to FBOs). + */ + ASSERT(ctx->Driver.DeleteTexture); + /* the default textures */ + ctx->Driver.DeleteTexture(ctx, ss->Default1D); + ctx->Driver.DeleteTexture(ctx, ss->Default2D); + ctx->Driver.DeleteTexture(ctx, ss->Default3D); + ctx->Driver.DeleteTexture(ctx, ss->DefaultCubeMap); + ctx->Driver.DeleteTexture(ctx, ss->DefaultRect); + /* all other textures */ + _mesa_HashDeleteAll(ss->TexObjects, delete_texture_cb, ctx); + _mesa_DeleteHashTable(ss->TexObjects); + _glthread_DESTROY_MUTEX(ss->Mutex); _mesa_free(ss); @@ -1157,18 +1181,20 @@ _mesa_create_context(const GLvisual *visual, void _mesa_free_context_data( GLcontext *ctx ) { - /* if we're destroying the current context, unbind it first */ - if (ctx == _mesa_get_current_context()) { - _mesa_make_current(NULL, NULL, NULL); - } - else { - /* unreference WinSysDraw/Read buffers */ - _mesa_unreference_framebuffer(&ctx->WinSysDrawBuffer); - _mesa_unreference_framebuffer(&ctx->WinSysReadBuffer); - _mesa_unreference_framebuffer(&ctx->DrawBuffer); - _mesa_unreference_framebuffer(&ctx->ReadBuffer); + if (!_mesa_get_current_context()){ + /* No current context, but we may need one in order to delete + * texture objs, etc. So temporarily bind the context now. + */ + _mesa_make_current(ctx, NULL, NULL); } + /* unreference WinSysDraw/Read buffers */ + _mesa_unreference_framebuffer(&ctx->WinSysDrawBuffer); + _mesa_unreference_framebuffer(&ctx->WinSysReadBuffer); + _mesa_unreference_framebuffer(&ctx->DrawBuffer); + _mesa_unreference_framebuffer(&ctx->ReadBuffer); + + _mesa_free_attrib_data(ctx); _mesa_free_lighting_data( ctx ); _mesa_free_eval_data( ctx ); _mesa_free_texture_data( ctx ); @@ -1200,6 +1226,11 @@ _mesa_free_context_data( GLcontext *ctx ) if (ctx->Extensions.String) _mesa_free((void *) ctx->Extensions.String); + + /* unbind the context if it's currently bound */ + if (ctx == _mesa_get_current_context()) { + _mesa_make_current(NULL, NULL, NULL); + } } @@ -1431,8 +1462,6 @@ void _mesa_make_current( GLcontext *newCtx, GLframebuffer *drawBuffer, GLframebuffer *readBuffer ) { - GET_CURRENT_CONTEXT(oldCtx); - if (MESA_VERBOSE & VERBOSE_API) _mesa_debug(newCtx, "_mesa_make_current()\n"); @@ -1457,13 +1486,6 @@ _mesa_make_current( GLcontext *newCtx, GLframebuffer *drawBuffer, _glapi_set_context((void *) newCtx); ASSERT(_mesa_get_current_context() == newCtx); - if (oldCtx) { - _mesa_unreference_framebuffer(&oldCtx->WinSysDrawBuffer); - _mesa_unreference_framebuffer(&oldCtx->WinSysReadBuffer); - _mesa_unreference_framebuffer(&oldCtx->DrawBuffer); - _mesa_unreference_framebuffer(&oldCtx->ReadBuffer); - } - if (!newCtx) { _glapi_set_dispatch(NULL); /* none current */ } diff --git a/reactos/dll/3rdparty/mesa32/src/main/dlist.c b/reactos/dll/3rdparty/mesa32/src/main/dlist.c index 7813c7ab135..844db6b9d2d 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/dlist.c +++ b/reactos/dll/3rdparty/mesa32/src/main/dlist.c @@ -1,6 +1,6 @@ /* * Mesa 3-D graphics library - * Version: 7.0.1 + * Version: 7.0.2 * * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. * @@ -5737,7 +5737,7 @@ execute_list(GLcontext *ctx, GLuint list) if (!dlist) return; - ctx->ListState.CallStack[ctx->ListState.CallDepth++] = dlist; + ctx->ListState.CallDepth++; if (ctx->Driver.BeginCallList) ctx->Driver.BeginCallList(ctx, dlist); @@ -6629,7 +6629,7 @@ execute_list(GLcontext *ctx, GLuint list) if (ctx->Driver.EndCallList) ctx->Driver.EndCallList(ctx); - ctx->ListState.CallStack[ctx->ListState.CallDepth--] = NULL; + ctx->ListState.CallDepth--; } diff --git a/reactos/dll/3rdparty/mesa32/src/main/enable.c b/reactos/dll/3rdparty/mesa32/src/main/enable.c index 0e14345e730..1c6167b7994 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/enable.c +++ b/reactos/dll/3rdparty/mesa32/src/main/enable.c @@ -364,6 +364,10 @@ _mesa_set_enable(GLcontext *ctx, GLenum cap, GLboolean state) case GL_LIGHTING: if (ctx->Light.Enabled == state) return; + if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) + ctx->_TriangleCaps |= DD_TRI_LIGHT_TWOSIDE; + else + ctx->_TriangleCaps &= ~DD_TRI_LIGHT_TWOSIDE; FLUSH_VERTICES(ctx, _NEW_LIGHT); ctx->Light.Enabled = state; break; @@ -372,12 +376,14 @@ _mesa_set_enable(GLcontext *ctx, GLenum cap, GLboolean state) return; FLUSH_VERTICES(ctx, _NEW_LINE); ctx->Line.SmoothFlag = state; + ctx->_TriangleCaps ^= DD_LINE_SMOOTH; break; case GL_LINE_STIPPLE: if (ctx->Line.StippleFlag == state) return; FLUSH_VERTICES(ctx, _NEW_LINE); ctx->Line.StippleFlag = state; + ctx->_TriangleCaps ^= DD_LINE_STIPPLE; break; case GL_INDEX_LOGIC_OP: if (ctx->Color.IndexLogicOpEnabled == state) @@ -516,18 +522,21 @@ _mesa_set_enable(GLcontext *ctx, GLenum cap, GLboolean state) return; FLUSH_VERTICES(ctx, _NEW_POINT); ctx->Point.SmoothFlag = state; + ctx->_TriangleCaps ^= DD_POINT_SMOOTH; break; case GL_POLYGON_SMOOTH: if (ctx->Polygon.SmoothFlag == state) return; FLUSH_VERTICES(ctx, _NEW_POLYGON); ctx->Polygon.SmoothFlag = state; + ctx->_TriangleCaps ^= DD_TRI_SMOOTH; break; case GL_POLYGON_STIPPLE: if (ctx->Polygon.StippleFlag == state) return; FLUSH_VERTICES(ctx, _NEW_POLYGON); ctx->Polygon.StippleFlag = state; + ctx->_TriangleCaps ^= DD_TRI_STIPPLE; break; case GL_POLYGON_OFFSET_POINT: if (ctx->Polygon.OffsetPoint == state) @@ -877,6 +886,10 @@ _mesa_set_enable(GLcontext *ctx, GLenum cap, GLboolean state) return; FLUSH_VERTICES(ctx, _NEW_STENCIL); ctx->Stencil.TestTwoSide = state; + if (state) + ctx->_TriangleCaps |= DD_TRI_TWOSTENCIL; + else + ctx->_TriangleCaps &= ~DD_TRI_TWOSTENCIL; break; #if FEATURE_ARB_fragment_program diff --git a/reactos/dll/3rdparty/mesa32/src/main/enums.c b/reactos/dll/3rdparty/mesa32/src/main/enums.c index bad33f7f642..e4e8611f437 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/enums.c +++ b/reactos/dll/3rdparty/mesa32/src/main/enums.c @@ -1428,9 +1428,13 @@ LONGSTRING static const char enum_string_table[] = "GL_STENCIL\0" "GL_STENCIL_ATTACHMENT_EXT\0" "GL_STENCIL_BACK_FAIL\0" + "GL_STENCIL_BACK_FAIL_ATI\0" "GL_STENCIL_BACK_FUNC\0" + "GL_STENCIL_BACK_FUNC_ATI\0" "GL_STENCIL_BACK_PASS_DEPTH_FAIL\0" + "GL_STENCIL_BACK_PASS_DEPTH_FAIL_ATI\0" "GL_STENCIL_BACK_PASS_DEPTH_PASS\0" + "GL_STENCIL_BACK_PASS_DEPTH_PASS_ATI\0" "GL_STENCIL_BACK_REF\0" "GL_STENCIL_BACK_VALUE_MASK\0" "GL_STENCIL_BACK_WRITEMASK\0" @@ -1774,7 +1778,7 @@ LONGSTRING static const char enum_string_table[] = "GL_ZOOM_Y\0" ; -static const enum_elt all_enums[1737] = +static const enum_elt all_enums[1741] = { { 0, 0x00000600 }, /* GL_2D */ { 6, 0x00001407 }, /* GL_2_BYTES */ @@ -3169,350 +3173,354 @@ static const enum_elt all_enums[1737] = { 29503, 0x00001802 }, /* GL_STENCIL */ { 29514, 0x00008D20 }, /* GL_STENCIL_ATTACHMENT_EXT */ { 29540, 0x00008801 }, /* GL_STENCIL_BACK_FAIL */ - { 29561, 0x00008800 }, /* GL_STENCIL_BACK_FUNC */ - { 29582, 0x00008802 }, /* GL_STENCIL_BACK_PASS_DEPTH_FAIL */ - { 29614, 0x00008803 }, /* GL_STENCIL_BACK_PASS_DEPTH_PASS */ - { 29646, 0x00008CA3 }, /* GL_STENCIL_BACK_REF */ - { 29666, 0x00008CA4 }, /* GL_STENCIL_BACK_VALUE_MASK */ - { 29693, 0x00008CA5 }, /* GL_STENCIL_BACK_WRITEMASK */ - { 29719, 0x00000D57 }, /* GL_STENCIL_BITS */ - { 29735, 0x00000400 }, /* GL_STENCIL_BUFFER_BIT */ - { 29757, 0x00000B91 }, /* GL_STENCIL_CLEAR_VALUE */ - { 29780, 0x00000B94 }, /* GL_STENCIL_FAIL */ - { 29796, 0x00000B92 }, /* GL_STENCIL_FUNC */ - { 29812, 0x00001901 }, /* GL_STENCIL_INDEX */ - { 29829, 0x00008D49 }, /* GL_STENCIL_INDEX16_EXT */ - { 29852, 0x00008D46 }, /* GL_STENCIL_INDEX1_EXT */ - { 29874, 0x00008D47 }, /* GL_STENCIL_INDEX4_EXT */ - { 29896, 0x00008D48 }, /* GL_STENCIL_INDEX8_EXT */ - { 29918, 0x00008D45 }, /* GL_STENCIL_INDEX_EXT */ - { 29939, 0x00000B95 }, /* GL_STENCIL_PASS_DEPTH_FAIL */ - { 29966, 0x00000B96 }, /* GL_STENCIL_PASS_DEPTH_PASS */ - { 29993, 0x00000B97 }, /* GL_STENCIL_REF */ - { 30008, 0x00000B90 }, /* GL_STENCIL_TEST */ - { 30024, 0x00008910 }, /* GL_STENCIL_TEST_TWO_SIDE_EXT */ - { 30053, 0x00000B93 }, /* GL_STENCIL_VALUE_MASK */ - { 30075, 0x00000B98 }, /* GL_STENCIL_WRITEMASK */ - { 30096, 0x00000C33 }, /* GL_STEREO */ - { 30106, 0x000088E2 }, /* GL_STREAM_COPY */ - { 30121, 0x000088E2 }, /* GL_STREAM_COPY_ARB */ - { 30140, 0x000088E0 }, /* GL_STREAM_DRAW */ - { 30155, 0x000088E0 }, /* GL_STREAM_DRAW_ARB */ - { 30174, 0x000088E1 }, /* GL_STREAM_READ */ - { 30189, 0x000088E1 }, /* GL_STREAM_READ_ARB */ - { 30208, 0x00000D50 }, /* GL_SUBPIXEL_BITS */ - { 30225, 0x000084E7 }, /* GL_SUBTRACT */ - { 30237, 0x000084E7 }, /* GL_SUBTRACT_ARB */ - { 30253, 0x00002001 }, /* GL_T */ - { 30258, 0x00002A2A }, /* GL_T2F_C3F_V3F */ - { 30273, 0x00002A2C }, /* GL_T2F_C4F_N3F_V3F */ - { 30292, 0x00002A29 }, /* GL_T2F_C4UB_V3F */ - { 30308, 0x00002A2B }, /* GL_T2F_N3F_V3F */ - { 30323, 0x00002A27 }, /* GL_T2F_V3F */ - { 30334, 0x00002A2D }, /* GL_T4F_C4F_N3F_V4F */ - { 30353, 0x00002A28 }, /* GL_T4F_V4F */ - { 30364, 0x00008031 }, /* GL_TABLE_TOO_LARGE_EXT */ - { 30387, 0x00001702 }, /* GL_TEXTURE */ - { 30398, 0x000084C0 }, /* GL_TEXTURE0 */ - { 30410, 0x000084C0 }, /* GL_TEXTURE0_ARB */ - { 30426, 0x000084C1 }, /* GL_TEXTURE1 */ - { 30438, 0x000084CA }, /* GL_TEXTURE10 */ - { 30451, 0x000084CA }, /* GL_TEXTURE10_ARB */ - { 30468, 0x000084CB }, /* GL_TEXTURE11 */ - { 30481, 0x000084CB }, /* GL_TEXTURE11_ARB */ - { 30498, 0x000084CC }, /* GL_TEXTURE12 */ - { 30511, 0x000084CC }, /* GL_TEXTURE12_ARB */ - { 30528, 0x000084CD }, /* GL_TEXTURE13 */ - { 30541, 0x000084CD }, /* GL_TEXTURE13_ARB */ - { 30558, 0x000084CE }, /* GL_TEXTURE14 */ - { 30571, 0x000084CE }, /* GL_TEXTURE14_ARB */ - { 30588, 0x000084CF }, /* GL_TEXTURE15 */ - { 30601, 0x000084CF }, /* GL_TEXTURE15_ARB */ - { 30618, 0x000084D0 }, /* GL_TEXTURE16 */ - { 30631, 0x000084D0 }, /* GL_TEXTURE16_ARB */ - { 30648, 0x000084D1 }, /* GL_TEXTURE17 */ - { 30661, 0x000084D1 }, /* GL_TEXTURE17_ARB */ - { 30678, 0x000084D2 }, /* GL_TEXTURE18 */ - { 30691, 0x000084D2 }, /* GL_TEXTURE18_ARB */ - { 30708, 0x000084D3 }, /* GL_TEXTURE19 */ - { 30721, 0x000084D3 }, /* GL_TEXTURE19_ARB */ - { 30738, 0x000084C1 }, /* GL_TEXTURE1_ARB */ - { 30754, 0x000084C2 }, /* GL_TEXTURE2 */ - { 30766, 0x000084D4 }, /* GL_TEXTURE20 */ - { 30779, 0x000084D4 }, /* GL_TEXTURE20_ARB */ - { 30796, 0x000084D5 }, /* GL_TEXTURE21 */ - { 30809, 0x000084D5 }, /* GL_TEXTURE21_ARB */ - { 30826, 0x000084D6 }, /* GL_TEXTURE22 */ - { 30839, 0x000084D6 }, /* GL_TEXTURE22_ARB */ - { 30856, 0x000084D7 }, /* GL_TEXTURE23 */ - { 30869, 0x000084D7 }, /* GL_TEXTURE23_ARB */ - { 30886, 0x000084D8 }, /* GL_TEXTURE24 */ - { 30899, 0x000084D8 }, /* GL_TEXTURE24_ARB */ - { 30916, 0x000084D9 }, /* GL_TEXTURE25 */ - { 30929, 0x000084D9 }, /* GL_TEXTURE25_ARB */ - { 30946, 0x000084DA }, /* GL_TEXTURE26 */ - { 30959, 0x000084DA }, /* GL_TEXTURE26_ARB */ - { 30976, 0x000084DB }, /* GL_TEXTURE27 */ - { 30989, 0x000084DB }, /* GL_TEXTURE27_ARB */ - { 31006, 0x000084DC }, /* GL_TEXTURE28 */ - { 31019, 0x000084DC }, /* GL_TEXTURE28_ARB */ - { 31036, 0x000084DD }, /* GL_TEXTURE29 */ - { 31049, 0x000084DD }, /* GL_TEXTURE29_ARB */ - { 31066, 0x000084C2 }, /* GL_TEXTURE2_ARB */ - { 31082, 0x000084C3 }, /* GL_TEXTURE3 */ - { 31094, 0x000084DE }, /* GL_TEXTURE30 */ - { 31107, 0x000084DE }, /* GL_TEXTURE30_ARB */ - { 31124, 0x000084DF }, /* GL_TEXTURE31 */ - { 31137, 0x000084DF }, /* GL_TEXTURE31_ARB */ - { 31154, 0x000084C3 }, /* GL_TEXTURE3_ARB */ - { 31170, 0x000084C4 }, /* GL_TEXTURE4 */ - { 31182, 0x000084C4 }, /* GL_TEXTURE4_ARB */ - { 31198, 0x000084C5 }, /* GL_TEXTURE5 */ - { 31210, 0x000084C5 }, /* GL_TEXTURE5_ARB */ - { 31226, 0x000084C6 }, /* GL_TEXTURE6 */ - { 31238, 0x000084C6 }, /* GL_TEXTURE6_ARB */ - { 31254, 0x000084C7 }, /* GL_TEXTURE7 */ - { 31266, 0x000084C7 }, /* GL_TEXTURE7_ARB */ - { 31282, 0x000084C8 }, /* GL_TEXTURE8 */ - { 31294, 0x000084C8 }, /* GL_TEXTURE8_ARB */ - { 31310, 0x000084C9 }, /* GL_TEXTURE9 */ - { 31322, 0x000084C9 }, /* GL_TEXTURE9_ARB */ - { 31338, 0x00000DE0 }, /* GL_TEXTURE_1D */ - { 31352, 0x00000DE1 }, /* GL_TEXTURE_2D */ - { 31366, 0x0000806F }, /* GL_TEXTURE_3D */ - { 31380, 0x0000805F }, /* GL_TEXTURE_ALPHA_SIZE */ - { 31402, 0x0000805F }, /* GL_TEXTURE_ALPHA_SIZE_EXT */ - { 31428, 0x0000813C }, /* GL_TEXTURE_BASE_LEVEL */ - { 31450, 0x00008068 }, /* GL_TEXTURE_BINDING_1D */ - { 31472, 0x00008069 }, /* GL_TEXTURE_BINDING_2D */ - { 31494, 0x0000806A }, /* GL_TEXTURE_BINDING_3D */ - { 31516, 0x00008514 }, /* GL_TEXTURE_BINDING_CUBE_MAP */ - { 31544, 0x00008514 }, /* GL_TEXTURE_BINDING_CUBE_MAP_ARB */ - { 31576, 0x000084F6 }, /* GL_TEXTURE_BINDING_RECTANGLE_ARB */ - { 31609, 0x000084F6 }, /* GL_TEXTURE_BINDING_RECTANGLE_NV */ - { 31641, 0x00040000 }, /* GL_TEXTURE_BIT */ - { 31656, 0x0000805E }, /* GL_TEXTURE_BLUE_SIZE */ - { 31677, 0x0000805E }, /* GL_TEXTURE_BLUE_SIZE_EXT */ - { 31702, 0x00001005 }, /* GL_TEXTURE_BORDER */ - { 31720, 0x00001004 }, /* GL_TEXTURE_BORDER_COLOR */ - { 31744, 0x00008171 }, /* GL_TEXTURE_CLIPMAP_CENTER_SGIX */ - { 31775, 0x00008176 }, /* GL_TEXTURE_CLIPMAP_DEPTH_SGIX */ - { 31805, 0x00008172 }, /* GL_TEXTURE_CLIPMAP_FRAME_SGIX */ - { 31835, 0x00008175 }, /* GL_TEXTURE_CLIPMAP_LOD_OFFSET_SGIX */ - { 31870, 0x00008173 }, /* GL_TEXTURE_CLIPMAP_OFFSET_SGIX */ - { 31901, 0x00008174 }, /* GL_TEXTURE_CLIPMAP_VIRTUAL_DEPTH_SGIX */ - { 31939, 0x000080BC }, /* GL_TEXTURE_COLOR_TABLE_SGI */ - { 31966, 0x000081EF }, /* GL_TEXTURE_COLOR_WRITEMASK_SGIS */ - { 31998, 0x000080BF }, /* GL_TEXTURE_COMPARE_FAIL_VALUE_ARB */ - { 32032, 0x0000884D }, /* GL_TEXTURE_COMPARE_FUNC */ - { 32056, 0x0000884D }, /* GL_TEXTURE_COMPARE_FUNC_ARB */ - { 32084, 0x0000884C }, /* GL_TEXTURE_COMPARE_MODE */ - { 32108, 0x0000884C }, /* GL_TEXTURE_COMPARE_MODE_ARB */ - { 32136, 0x0000819B }, /* GL_TEXTURE_COMPARE_OPERATOR_SGIX */ - { 32169, 0x0000819A }, /* GL_TEXTURE_COMPARE_SGIX */ - { 32193, 0x00001003 }, /* GL_TEXTURE_COMPONENTS */ - { 32215, 0x000086A1 }, /* GL_TEXTURE_COMPRESSED */ - { 32237, 0x000086A1 }, /* GL_TEXTURE_COMPRESSED_ARB */ - { 32263, 0x000086A3 }, /* GL_TEXTURE_COMPRESSED_FORMATS_ARB */ - { 32297, 0x000086A0 }, /* GL_TEXTURE_COMPRESSED_IMAGE_SIZE */ - { 32330, 0x000086A0 }, /* GL_TEXTURE_COMPRESSED_IMAGE_SIZE_ARB */ - { 32367, 0x000084EF }, /* GL_TEXTURE_COMPRESSION_HINT */ - { 32395, 0x000084EF }, /* GL_TEXTURE_COMPRESSION_HINT_ARB */ - { 32427, 0x00008078 }, /* GL_TEXTURE_COORD_ARRAY */ - { 32450, 0x0000889A }, /* GL_TEXTURE_COORD_ARRAY_BUFFER_BINDING */ - { 32488, 0x0000889A }, /* GL_TEXTURE_COORD_ARRAY_BUFFER_BINDING_ARB */ - { 32530, 0x00008092 }, /* GL_TEXTURE_COORD_ARRAY_POINTER */ - { 32561, 0x00008088 }, /* GL_TEXTURE_COORD_ARRAY_SIZE */ - { 32589, 0x0000808A }, /* GL_TEXTURE_COORD_ARRAY_STRIDE */ - { 32619, 0x00008089 }, /* GL_TEXTURE_COORD_ARRAY_TYPE */ - { 32647, 0x00008513 }, /* GL_TEXTURE_CUBE_MAP */ - { 32667, 0x00008513 }, /* GL_TEXTURE_CUBE_MAP_ARB */ - { 32691, 0x00008516 }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_X */ - { 32722, 0x00008516 }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB */ - { 32757, 0x00008518 }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Y */ - { 32788, 0x00008518 }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB */ - { 32823, 0x0000851A }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Z */ - { 32854, 0x0000851A }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB */ - { 32889, 0x00008515 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_X */ - { 32920, 0x00008515 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB */ - { 32955, 0x00008517 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Y */ - { 32986, 0x00008517 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB */ - { 33021, 0x00008519 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Z */ - { 33052, 0x00008519 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB */ - { 33087, 0x00008071 }, /* GL_TEXTURE_DEPTH */ - { 33104, 0x0000884A }, /* GL_TEXTURE_DEPTH_SIZE */ - { 33126, 0x0000884A }, /* GL_TEXTURE_DEPTH_SIZE_ARB */ - { 33152, 0x00002300 }, /* GL_TEXTURE_ENV */ - { 33167, 0x00002201 }, /* GL_TEXTURE_ENV_COLOR */ - { 33188, 0x00002200 }, /* GL_TEXTURE_ENV_MODE */ - { 33208, 0x00008500 }, /* GL_TEXTURE_FILTER_CONTROL */ - { 33234, 0x00002500 }, /* GL_TEXTURE_GEN_MODE */ - { 33254, 0x00000C63 }, /* GL_TEXTURE_GEN_Q */ - { 33271, 0x00000C62 }, /* GL_TEXTURE_GEN_R */ - { 33288, 0x00000C60 }, /* GL_TEXTURE_GEN_S */ - { 33305, 0x00000C61 }, /* GL_TEXTURE_GEN_T */ - { 33322, 0x0000819D }, /* GL_TEXTURE_GEQUAL_R_SGIX */ - { 33347, 0x0000805D }, /* GL_TEXTURE_GREEN_SIZE */ - { 33369, 0x0000805D }, /* GL_TEXTURE_GREEN_SIZE_EXT */ - { 33395, 0x00001001 }, /* GL_TEXTURE_HEIGHT */ - { 33413, 0x000080ED }, /* GL_TEXTURE_INDEX_SIZE_EXT */ - { 33439, 0x00008061 }, /* GL_TEXTURE_INTENSITY_SIZE */ - { 33465, 0x00008061 }, /* GL_TEXTURE_INTENSITY_SIZE_EXT */ - { 33495, 0x00001003 }, /* GL_TEXTURE_INTERNAL_FORMAT */ - { 33522, 0x0000819C }, /* GL_TEXTURE_LEQUAL_R_SGIX */ - { 33547, 0x00008501 }, /* GL_TEXTURE_LOD_BIAS */ - { 33567, 0x00008501 }, /* GL_TEXTURE_LOD_BIAS_EXT */ - { 33591, 0x00008190 }, /* GL_TEXTURE_LOD_BIAS_R_SGIX */ - { 33618, 0x0000818E }, /* GL_TEXTURE_LOD_BIAS_S_SGIX */ - { 33645, 0x0000818F }, /* GL_TEXTURE_LOD_BIAS_T_SGIX */ - { 33672, 0x00008060 }, /* GL_TEXTURE_LUMINANCE_SIZE */ - { 33698, 0x00008060 }, /* GL_TEXTURE_LUMINANCE_SIZE_EXT */ - { 33728, 0x00002800 }, /* GL_TEXTURE_MAG_FILTER */ - { 33750, 0x00000BA8 }, /* GL_TEXTURE_MATRIX */ - { 33768, 0x000084FE }, /* GL_TEXTURE_MAX_ANISOTROPY_EXT */ - { 33798, 0x0000836B }, /* GL_TEXTURE_MAX_CLAMP_R_SGIX */ - { 33826, 0x00008369 }, /* GL_TEXTURE_MAX_CLAMP_S_SGIX */ - { 33854, 0x0000836A }, /* GL_TEXTURE_MAX_CLAMP_T_SGIX */ - { 33882, 0x0000813D }, /* GL_TEXTURE_MAX_LEVEL */ - { 33903, 0x0000813B }, /* GL_TEXTURE_MAX_LOD */ - { 33922, 0x00002801 }, /* GL_TEXTURE_MIN_FILTER */ - { 33944, 0x0000813A }, /* GL_TEXTURE_MIN_LOD */ - { 33963, 0x00008066 }, /* GL_TEXTURE_PRIORITY */ - { 33983, 0x000084F5 }, /* GL_TEXTURE_RECTANGLE_ARB */ - { 34008, 0x000084F5 }, /* GL_TEXTURE_RECTANGLE_NV */ - { 34032, 0x0000805C }, /* GL_TEXTURE_RED_SIZE */ - { 34052, 0x0000805C }, /* GL_TEXTURE_RED_SIZE_EXT */ - { 34076, 0x00008067 }, /* GL_TEXTURE_RESIDENT */ - { 34096, 0x00000BA5 }, /* GL_TEXTURE_STACK_DEPTH */ - { 34119, 0x00008065 }, /* GL_TEXTURE_TOO_LARGE_EXT */ - { 34144, 0x0000888F }, /* GL_TEXTURE_UNSIGNED_REMAP_MODE_NV */ - { 34178, 0x00001000 }, /* GL_TEXTURE_WIDTH */ - { 34195, 0x00008072 }, /* GL_TEXTURE_WRAP_R */ - { 34213, 0x00002802 }, /* GL_TEXTURE_WRAP_S */ - { 34231, 0x00002803 }, /* GL_TEXTURE_WRAP_T */ - { 34249, 0x000088BF }, /* GL_TIME_ELAPSED_EXT */ - { 34269, 0x00008648 }, /* GL_TRACK_MATRIX_NV */ - { 34288, 0x00008649 }, /* GL_TRACK_MATRIX_TRANSFORM_NV */ - { 34317, 0x00001000 }, /* GL_TRANSFORM_BIT */ - { 34334, 0x000084E6 }, /* GL_TRANSPOSE_COLOR_MATRIX */ - { 34360, 0x000084E6 }, /* GL_TRANSPOSE_COLOR_MATRIX_ARB */ - { 34390, 0x000088B7 }, /* GL_TRANSPOSE_CURRENT_MATRIX_ARB */ - { 34422, 0x000084E3 }, /* GL_TRANSPOSE_MODELVIEW_MATRIX */ - { 34452, 0x000084E3 }, /* GL_TRANSPOSE_MODELVIEW_MATRIX_ARB */ - { 34486, 0x0000862C }, /* GL_TRANSPOSE_NV */ - { 34502, 0x000084E4 }, /* GL_TRANSPOSE_PROJECTION_MATRIX */ - { 34533, 0x000084E4 }, /* GL_TRANSPOSE_PROJECTION_MATRIX_ARB */ - { 34568, 0x000084E5 }, /* GL_TRANSPOSE_TEXTURE_MATRIX */ - { 34596, 0x000084E5 }, /* GL_TRANSPOSE_TEXTURE_MATRIX_ARB */ - { 34628, 0x00000004 }, /* GL_TRIANGLES */ - { 34641, 0x00000006 }, /* GL_TRIANGLE_FAN */ - { 34657, 0x00008615 }, /* GL_TRIANGLE_MESH_SUN */ - { 34678, 0x00000005 }, /* GL_TRIANGLE_STRIP */ - { 34696, 0x00000001 }, /* GL_TRUE */ - { 34704, 0x00000CF5 }, /* GL_UNPACK_ALIGNMENT */ - { 34724, 0x0000806E }, /* GL_UNPACK_IMAGE_HEIGHT */ - { 34747, 0x00000CF1 }, /* GL_UNPACK_LSB_FIRST */ - { 34767, 0x00000CF2 }, /* GL_UNPACK_ROW_LENGTH */ - { 34788, 0x0000806D }, /* GL_UNPACK_SKIP_IMAGES */ - { 34810, 0x00000CF4 }, /* GL_UNPACK_SKIP_PIXELS */ - { 34832, 0x00000CF3 }, /* GL_UNPACK_SKIP_ROWS */ - { 34852, 0x00000CF0 }, /* GL_UNPACK_SWAP_BYTES */ - { 34873, 0x00001401 }, /* GL_UNSIGNED_BYTE */ - { 34890, 0x00008362 }, /* GL_UNSIGNED_BYTE_2_3_3_REV */ - { 34917, 0x00008032 }, /* GL_UNSIGNED_BYTE_3_3_2 */ - { 34940, 0x00001405 }, /* GL_UNSIGNED_INT */ - { 34956, 0x00008036 }, /* GL_UNSIGNED_INT_10_10_10_2 */ - { 34983, 0x000084FA }, /* GL_UNSIGNED_INT_24_8_NV */ - { 35007, 0x00008368 }, /* GL_UNSIGNED_INT_2_10_10_10_REV */ - { 35038, 0x00008035 }, /* GL_UNSIGNED_INT_8_8_8_8 */ - { 35062, 0x00008367 }, /* GL_UNSIGNED_INT_8_8_8_8_REV */ - { 35090, 0x00001403 }, /* GL_UNSIGNED_SHORT */ - { 35108, 0x00008366 }, /* GL_UNSIGNED_SHORT_1_5_5_5_REV */ - { 35138, 0x00008033 }, /* GL_UNSIGNED_SHORT_4_4_4_4 */ - { 35164, 0x00008365 }, /* GL_UNSIGNED_SHORT_4_4_4_4_REV */ - { 35194, 0x00008034 }, /* GL_UNSIGNED_SHORT_5_5_5_1 */ - { 35220, 0x00008363 }, /* GL_UNSIGNED_SHORT_5_6_5 */ - { 35244, 0x00008364 }, /* GL_UNSIGNED_SHORT_5_6_5_REV */ - { 35272, 0x000085BA }, /* GL_UNSIGNED_SHORT_8_8_APPLE */ - { 35300, 0x000085BA }, /* GL_UNSIGNED_SHORT_8_8_MESA */ - { 35327, 0x000085BB }, /* GL_UNSIGNED_SHORT_8_8_REV_APPLE */ - { 35359, 0x000085BB }, /* GL_UNSIGNED_SHORT_8_8_REV_MESA */ - { 35390, 0x00008CA2 }, /* GL_UPPER_LEFT */ - { 35404, 0x00002A20 }, /* GL_V2F */ - { 35411, 0x00002A21 }, /* GL_V3F */ - { 35418, 0x00008B83 }, /* GL_VALIDATE_STATUS */ - { 35437, 0x00001F00 }, /* GL_VENDOR */ - { 35447, 0x00001F02 }, /* GL_VERSION */ - { 35458, 0x00008074 }, /* GL_VERTEX_ARRAY */ - { 35474, 0x000085B5 }, /* GL_VERTEX_ARRAY_BINDING_APPLE */ - { 35504, 0x00008896 }, /* GL_VERTEX_ARRAY_BUFFER_BINDING */ - { 35535, 0x00008896 }, /* GL_VERTEX_ARRAY_BUFFER_BINDING_ARB */ - { 35570, 0x0000808E }, /* GL_VERTEX_ARRAY_POINTER */ - { 35594, 0x0000807A }, /* GL_VERTEX_ARRAY_SIZE */ - { 35615, 0x0000807C }, /* GL_VERTEX_ARRAY_STRIDE */ - { 35638, 0x0000807B }, /* GL_VERTEX_ARRAY_TYPE */ - { 35659, 0x00008650 }, /* GL_VERTEX_ATTRIB_ARRAY0_NV */ - { 35686, 0x0000865A }, /* GL_VERTEX_ATTRIB_ARRAY10_NV */ - { 35714, 0x0000865B }, /* GL_VERTEX_ATTRIB_ARRAY11_NV */ - { 35742, 0x0000865C }, /* GL_VERTEX_ATTRIB_ARRAY12_NV */ - { 35770, 0x0000865D }, /* GL_VERTEX_ATTRIB_ARRAY13_NV */ - { 35798, 0x0000865E }, /* GL_VERTEX_ATTRIB_ARRAY14_NV */ - { 35826, 0x0000865F }, /* GL_VERTEX_ATTRIB_ARRAY15_NV */ - { 35854, 0x00008651 }, /* GL_VERTEX_ATTRIB_ARRAY1_NV */ - { 35881, 0x00008652 }, /* GL_VERTEX_ATTRIB_ARRAY2_NV */ - { 35908, 0x00008653 }, /* GL_VERTEX_ATTRIB_ARRAY3_NV */ - { 35935, 0x00008654 }, /* GL_VERTEX_ATTRIB_ARRAY4_NV */ - { 35962, 0x00008655 }, /* GL_VERTEX_ATTRIB_ARRAY5_NV */ - { 35989, 0x00008656 }, /* GL_VERTEX_ATTRIB_ARRAY6_NV */ - { 36016, 0x00008657 }, /* GL_VERTEX_ATTRIB_ARRAY7_NV */ - { 36043, 0x00008658 }, /* GL_VERTEX_ATTRIB_ARRAY8_NV */ - { 36070, 0x00008659 }, /* GL_VERTEX_ATTRIB_ARRAY9_NV */ - { 36097, 0x0000889F }, /* GL_VERTEX_ATTRIB_ARRAY_BUFFER_BINDING */ - { 36135, 0x0000889F }, /* GL_VERTEX_ATTRIB_ARRAY_BUFFER_BINDING_ARB */ - { 36177, 0x00008622 }, /* GL_VERTEX_ATTRIB_ARRAY_ENABLED */ - { 36208, 0x00008622 }, /* GL_VERTEX_ATTRIB_ARRAY_ENABLED_ARB */ - { 36243, 0x0000886A }, /* GL_VERTEX_ATTRIB_ARRAY_NORMALIZED */ - { 36277, 0x0000886A }, /* GL_VERTEX_ATTRIB_ARRAY_NORMALIZED_ARB */ - { 36315, 0x00008645 }, /* GL_VERTEX_ATTRIB_ARRAY_POINTER */ - { 36346, 0x00008645 }, /* GL_VERTEX_ATTRIB_ARRAY_POINTER_ARB */ - { 36381, 0x00008623 }, /* GL_VERTEX_ATTRIB_ARRAY_SIZE */ - { 36409, 0x00008623 }, /* GL_VERTEX_ATTRIB_ARRAY_SIZE_ARB */ - { 36441, 0x00008624 }, /* GL_VERTEX_ATTRIB_ARRAY_STRIDE */ - { 36471, 0x00008624 }, /* GL_VERTEX_ATTRIB_ARRAY_STRIDE_ARB */ - { 36505, 0x00008625 }, /* GL_VERTEX_ATTRIB_ARRAY_TYPE */ - { 36533, 0x00008625 }, /* GL_VERTEX_ATTRIB_ARRAY_TYPE_ARB */ - { 36565, 0x000086A7 }, /* GL_VERTEX_BLEND_ARB */ - { 36585, 0x00008620 }, /* GL_VERTEX_PROGRAM_ARB */ - { 36607, 0x0000864A }, /* GL_VERTEX_PROGRAM_BINDING_NV */ - { 36636, 0x00008620 }, /* GL_VERTEX_PROGRAM_NV */ - { 36657, 0x00008642 }, /* GL_VERTEX_PROGRAM_POINT_SIZE */ - { 36686, 0x00008642 }, /* GL_VERTEX_PROGRAM_POINT_SIZE_ARB */ - { 36719, 0x00008642 }, /* GL_VERTEX_PROGRAM_POINT_SIZE_NV */ - { 36751, 0x00008643 }, /* GL_VERTEX_PROGRAM_TWO_SIDE */ - { 36778, 0x00008643 }, /* GL_VERTEX_PROGRAM_TWO_SIDE_ARB */ - { 36809, 0x00008643 }, /* GL_VERTEX_PROGRAM_TWO_SIDE_NV */ - { 36839, 0x00008B31 }, /* GL_VERTEX_SHADER */ - { 36856, 0x00008B31 }, /* GL_VERTEX_SHADER_ARB */ - { 36877, 0x00008621 }, /* GL_VERTEX_STATE_PROGRAM_NV */ - { 36904, 0x00000BA2 }, /* GL_VIEWPORT */ - { 36916, 0x00000800 }, /* GL_VIEWPORT_BIT */ - { 36932, 0x000086AD }, /* GL_WEIGHT_ARRAY_ARB */ - { 36952, 0x0000889E }, /* GL_WEIGHT_ARRAY_BUFFER_BINDING */ - { 36983, 0x0000889E }, /* GL_WEIGHT_ARRAY_BUFFER_BINDING_ARB */ - { 37018, 0x000086AC }, /* GL_WEIGHT_ARRAY_POINTER_ARB */ - { 37046, 0x000086AB }, /* GL_WEIGHT_ARRAY_SIZE_ARB */ - { 37071, 0x000086AA }, /* GL_WEIGHT_ARRAY_STRIDE_ARB */ - { 37098, 0x000086A9 }, /* GL_WEIGHT_ARRAY_TYPE_ARB */ - { 37123, 0x000086A6 }, /* GL_WEIGHT_SUM_UNITY_ARB */ - { 37147, 0x000081D4 }, /* GL_WRAP_BORDER_SUN */ - { 37166, 0x000088B9 }, /* GL_WRITE_ONLY */ - { 37180, 0x000088B9 }, /* GL_WRITE_ONLY_ARB */ - { 37198, 0x00001506 }, /* GL_XOR */ - { 37205, 0x000085B9 }, /* GL_YCBCR_422_APPLE */ - { 37224, 0x00008757 }, /* GL_YCBCR_MESA */ - { 37238, 0x00000000 }, /* GL_ZERO */ - { 37246, 0x00000D16 }, /* GL_ZOOM_X */ - { 37256, 0x00000D17 }, /* GL_ZOOM_Y */ + { 29561, 0x00008801 }, /* GL_STENCIL_BACK_FAIL_ATI */ + { 29586, 0x00008800 }, /* GL_STENCIL_BACK_FUNC */ + { 29607, 0x00008800 }, /* GL_STENCIL_BACK_FUNC_ATI */ + { 29632, 0x00008802 }, /* GL_STENCIL_BACK_PASS_DEPTH_FAIL */ + { 29664, 0x00008802 }, /* GL_STENCIL_BACK_PASS_DEPTH_FAIL_ATI */ + { 29700, 0x00008803 }, /* GL_STENCIL_BACK_PASS_DEPTH_PASS */ + { 29732, 0x00008803 }, /* GL_STENCIL_BACK_PASS_DEPTH_PASS_ATI */ + { 29768, 0x00008CA3 }, /* GL_STENCIL_BACK_REF */ + { 29788, 0x00008CA4 }, /* GL_STENCIL_BACK_VALUE_MASK */ + { 29815, 0x00008CA5 }, /* GL_STENCIL_BACK_WRITEMASK */ + { 29841, 0x00000D57 }, /* GL_STENCIL_BITS */ + { 29857, 0x00000400 }, /* GL_STENCIL_BUFFER_BIT */ + { 29879, 0x00000B91 }, /* GL_STENCIL_CLEAR_VALUE */ + { 29902, 0x00000B94 }, /* GL_STENCIL_FAIL */ + { 29918, 0x00000B92 }, /* GL_STENCIL_FUNC */ + { 29934, 0x00001901 }, /* GL_STENCIL_INDEX */ + { 29951, 0x00008D49 }, /* GL_STENCIL_INDEX16_EXT */ + { 29974, 0x00008D46 }, /* GL_STENCIL_INDEX1_EXT */ + { 29996, 0x00008D47 }, /* GL_STENCIL_INDEX4_EXT */ + { 30018, 0x00008D48 }, /* GL_STENCIL_INDEX8_EXT */ + { 30040, 0x00008D45 }, /* GL_STENCIL_INDEX_EXT */ + { 30061, 0x00000B95 }, /* GL_STENCIL_PASS_DEPTH_FAIL */ + { 30088, 0x00000B96 }, /* GL_STENCIL_PASS_DEPTH_PASS */ + { 30115, 0x00000B97 }, /* GL_STENCIL_REF */ + { 30130, 0x00000B90 }, /* GL_STENCIL_TEST */ + { 30146, 0x00008910 }, /* GL_STENCIL_TEST_TWO_SIDE_EXT */ + { 30175, 0x00000B93 }, /* GL_STENCIL_VALUE_MASK */ + { 30197, 0x00000B98 }, /* GL_STENCIL_WRITEMASK */ + { 30218, 0x00000C33 }, /* GL_STEREO */ + { 30228, 0x000088E2 }, /* GL_STREAM_COPY */ + { 30243, 0x000088E2 }, /* GL_STREAM_COPY_ARB */ + { 30262, 0x000088E0 }, /* GL_STREAM_DRAW */ + { 30277, 0x000088E0 }, /* GL_STREAM_DRAW_ARB */ + { 30296, 0x000088E1 }, /* GL_STREAM_READ */ + { 30311, 0x000088E1 }, /* GL_STREAM_READ_ARB */ + { 30330, 0x00000D50 }, /* GL_SUBPIXEL_BITS */ + { 30347, 0x000084E7 }, /* GL_SUBTRACT */ + { 30359, 0x000084E7 }, /* GL_SUBTRACT_ARB */ + { 30375, 0x00002001 }, /* GL_T */ + { 30380, 0x00002A2A }, /* GL_T2F_C3F_V3F */ + { 30395, 0x00002A2C }, /* GL_T2F_C4F_N3F_V3F */ + { 30414, 0x00002A29 }, /* GL_T2F_C4UB_V3F */ + { 30430, 0x00002A2B }, /* GL_T2F_N3F_V3F */ + { 30445, 0x00002A27 }, /* GL_T2F_V3F */ + { 30456, 0x00002A2D }, /* GL_T4F_C4F_N3F_V4F */ + { 30475, 0x00002A28 }, /* GL_T4F_V4F */ + { 30486, 0x00008031 }, /* GL_TABLE_TOO_LARGE_EXT */ + { 30509, 0x00001702 }, /* GL_TEXTURE */ + { 30520, 0x000084C0 }, /* GL_TEXTURE0 */ + { 30532, 0x000084C0 }, /* GL_TEXTURE0_ARB */ + { 30548, 0x000084C1 }, /* GL_TEXTURE1 */ + { 30560, 0x000084CA }, /* GL_TEXTURE10 */ + { 30573, 0x000084CA }, /* GL_TEXTURE10_ARB */ + { 30590, 0x000084CB }, /* GL_TEXTURE11 */ + { 30603, 0x000084CB }, /* GL_TEXTURE11_ARB */ + { 30620, 0x000084CC }, /* GL_TEXTURE12 */ + { 30633, 0x000084CC }, /* GL_TEXTURE12_ARB */ + { 30650, 0x000084CD }, /* GL_TEXTURE13 */ + { 30663, 0x000084CD }, /* GL_TEXTURE13_ARB */ + { 30680, 0x000084CE }, /* GL_TEXTURE14 */ + { 30693, 0x000084CE }, /* GL_TEXTURE14_ARB */ + { 30710, 0x000084CF }, /* GL_TEXTURE15 */ + { 30723, 0x000084CF }, /* GL_TEXTURE15_ARB */ + { 30740, 0x000084D0 }, /* GL_TEXTURE16 */ + { 30753, 0x000084D0 }, /* GL_TEXTURE16_ARB */ + { 30770, 0x000084D1 }, /* GL_TEXTURE17 */ + { 30783, 0x000084D1 }, /* GL_TEXTURE17_ARB */ + { 30800, 0x000084D2 }, /* GL_TEXTURE18 */ + { 30813, 0x000084D2 }, /* GL_TEXTURE18_ARB */ + { 30830, 0x000084D3 }, /* GL_TEXTURE19 */ + { 30843, 0x000084D3 }, /* GL_TEXTURE19_ARB */ + { 30860, 0x000084C1 }, /* GL_TEXTURE1_ARB */ + { 30876, 0x000084C2 }, /* GL_TEXTURE2 */ + { 30888, 0x000084D4 }, /* GL_TEXTURE20 */ + { 30901, 0x000084D4 }, /* GL_TEXTURE20_ARB */ + { 30918, 0x000084D5 }, /* GL_TEXTURE21 */ + { 30931, 0x000084D5 }, /* GL_TEXTURE21_ARB */ + { 30948, 0x000084D6 }, /* GL_TEXTURE22 */ + { 30961, 0x000084D6 }, /* GL_TEXTURE22_ARB */ + { 30978, 0x000084D7 }, /* GL_TEXTURE23 */ + { 30991, 0x000084D7 }, /* GL_TEXTURE23_ARB */ + { 31008, 0x000084D8 }, /* GL_TEXTURE24 */ + { 31021, 0x000084D8 }, /* GL_TEXTURE24_ARB */ + { 31038, 0x000084D9 }, /* GL_TEXTURE25 */ + { 31051, 0x000084D9 }, /* GL_TEXTURE25_ARB */ + { 31068, 0x000084DA }, /* GL_TEXTURE26 */ + { 31081, 0x000084DA }, /* GL_TEXTURE26_ARB */ + { 31098, 0x000084DB }, /* GL_TEXTURE27 */ + { 31111, 0x000084DB }, /* GL_TEXTURE27_ARB */ + { 31128, 0x000084DC }, /* GL_TEXTURE28 */ + { 31141, 0x000084DC }, /* GL_TEXTURE28_ARB */ + { 31158, 0x000084DD }, /* GL_TEXTURE29 */ + { 31171, 0x000084DD }, /* GL_TEXTURE29_ARB */ + { 31188, 0x000084C2 }, /* GL_TEXTURE2_ARB */ + { 31204, 0x000084C3 }, /* GL_TEXTURE3 */ + { 31216, 0x000084DE }, /* GL_TEXTURE30 */ + { 31229, 0x000084DE }, /* GL_TEXTURE30_ARB */ + { 31246, 0x000084DF }, /* GL_TEXTURE31 */ + { 31259, 0x000084DF }, /* GL_TEXTURE31_ARB */ + { 31276, 0x000084C3 }, /* GL_TEXTURE3_ARB */ + { 31292, 0x000084C4 }, /* GL_TEXTURE4 */ + { 31304, 0x000084C4 }, /* GL_TEXTURE4_ARB */ + { 31320, 0x000084C5 }, /* GL_TEXTURE5 */ + { 31332, 0x000084C5 }, /* GL_TEXTURE5_ARB */ + { 31348, 0x000084C6 }, /* GL_TEXTURE6 */ + { 31360, 0x000084C6 }, /* GL_TEXTURE6_ARB */ + { 31376, 0x000084C7 }, /* GL_TEXTURE7 */ + { 31388, 0x000084C7 }, /* GL_TEXTURE7_ARB */ + { 31404, 0x000084C8 }, /* GL_TEXTURE8 */ + { 31416, 0x000084C8 }, /* GL_TEXTURE8_ARB */ + { 31432, 0x000084C9 }, /* GL_TEXTURE9 */ + { 31444, 0x000084C9 }, /* GL_TEXTURE9_ARB */ + { 31460, 0x00000DE0 }, /* GL_TEXTURE_1D */ + { 31474, 0x00000DE1 }, /* GL_TEXTURE_2D */ + { 31488, 0x0000806F }, /* GL_TEXTURE_3D */ + { 31502, 0x0000805F }, /* GL_TEXTURE_ALPHA_SIZE */ + { 31524, 0x0000805F }, /* GL_TEXTURE_ALPHA_SIZE_EXT */ + { 31550, 0x0000813C }, /* GL_TEXTURE_BASE_LEVEL */ + { 31572, 0x00008068 }, /* GL_TEXTURE_BINDING_1D */ + { 31594, 0x00008069 }, /* GL_TEXTURE_BINDING_2D */ + { 31616, 0x0000806A }, /* GL_TEXTURE_BINDING_3D */ + { 31638, 0x00008514 }, /* GL_TEXTURE_BINDING_CUBE_MAP */ + { 31666, 0x00008514 }, /* GL_TEXTURE_BINDING_CUBE_MAP_ARB */ + { 31698, 0x000084F6 }, /* GL_TEXTURE_BINDING_RECTANGLE_ARB */ + { 31731, 0x000084F6 }, /* GL_TEXTURE_BINDING_RECTANGLE_NV */ + { 31763, 0x00040000 }, /* GL_TEXTURE_BIT */ + { 31778, 0x0000805E }, /* GL_TEXTURE_BLUE_SIZE */ + { 31799, 0x0000805E }, /* GL_TEXTURE_BLUE_SIZE_EXT */ + { 31824, 0x00001005 }, /* GL_TEXTURE_BORDER */ + { 31842, 0x00001004 }, /* GL_TEXTURE_BORDER_COLOR */ + { 31866, 0x00008171 }, /* GL_TEXTURE_CLIPMAP_CENTER_SGIX */ + { 31897, 0x00008176 }, /* GL_TEXTURE_CLIPMAP_DEPTH_SGIX */ + { 31927, 0x00008172 }, /* GL_TEXTURE_CLIPMAP_FRAME_SGIX */ + { 31957, 0x00008175 }, /* GL_TEXTURE_CLIPMAP_LOD_OFFSET_SGIX */ + { 31992, 0x00008173 }, /* GL_TEXTURE_CLIPMAP_OFFSET_SGIX */ + { 32023, 0x00008174 }, /* GL_TEXTURE_CLIPMAP_VIRTUAL_DEPTH_SGIX */ + { 32061, 0x000080BC }, /* GL_TEXTURE_COLOR_TABLE_SGI */ + { 32088, 0x000081EF }, /* GL_TEXTURE_COLOR_WRITEMASK_SGIS */ + { 32120, 0x000080BF }, /* GL_TEXTURE_COMPARE_FAIL_VALUE_ARB */ + { 32154, 0x0000884D }, /* GL_TEXTURE_COMPARE_FUNC */ + { 32178, 0x0000884D }, /* GL_TEXTURE_COMPARE_FUNC_ARB */ + { 32206, 0x0000884C }, /* GL_TEXTURE_COMPARE_MODE */ + { 32230, 0x0000884C }, /* GL_TEXTURE_COMPARE_MODE_ARB */ + { 32258, 0x0000819B }, /* GL_TEXTURE_COMPARE_OPERATOR_SGIX */ + { 32291, 0x0000819A }, /* GL_TEXTURE_COMPARE_SGIX */ + { 32315, 0x00001003 }, /* GL_TEXTURE_COMPONENTS */ + { 32337, 0x000086A1 }, /* GL_TEXTURE_COMPRESSED */ + { 32359, 0x000086A1 }, /* GL_TEXTURE_COMPRESSED_ARB */ + { 32385, 0x000086A3 }, /* GL_TEXTURE_COMPRESSED_FORMATS_ARB */ + { 32419, 0x000086A0 }, /* GL_TEXTURE_COMPRESSED_IMAGE_SIZE */ + { 32452, 0x000086A0 }, /* GL_TEXTURE_COMPRESSED_IMAGE_SIZE_ARB */ + { 32489, 0x000084EF }, /* GL_TEXTURE_COMPRESSION_HINT */ + { 32517, 0x000084EF }, /* GL_TEXTURE_COMPRESSION_HINT_ARB */ + { 32549, 0x00008078 }, /* GL_TEXTURE_COORD_ARRAY */ + { 32572, 0x0000889A }, /* GL_TEXTURE_COORD_ARRAY_BUFFER_BINDING */ + { 32610, 0x0000889A }, /* GL_TEXTURE_COORD_ARRAY_BUFFER_BINDING_ARB */ + { 32652, 0x00008092 }, /* GL_TEXTURE_COORD_ARRAY_POINTER */ + { 32683, 0x00008088 }, /* GL_TEXTURE_COORD_ARRAY_SIZE */ + { 32711, 0x0000808A }, /* GL_TEXTURE_COORD_ARRAY_STRIDE */ + { 32741, 0x00008089 }, /* GL_TEXTURE_COORD_ARRAY_TYPE */ + { 32769, 0x00008513 }, /* GL_TEXTURE_CUBE_MAP */ + { 32789, 0x00008513 }, /* GL_TEXTURE_CUBE_MAP_ARB */ + { 32813, 0x00008516 }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_X */ + { 32844, 0x00008516 }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB */ + { 32879, 0x00008518 }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Y */ + { 32910, 0x00008518 }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB */ + { 32945, 0x0000851A }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Z */ + { 32976, 0x0000851A }, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB */ + { 33011, 0x00008515 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_X */ + { 33042, 0x00008515 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB */ + { 33077, 0x00008517 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Y */ + { 33108, 0x00008517 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB */ + { 33143, 0x00008519 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Z */ + { 33174, 0x00008519 }, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB */ + { 33209, 0x00008071 }, /* GL_TEXTURE_DEPTH */ + { 33226, 0x0000884A }, /* GL_TEXTURE_DEPTH_SIZE */ + { 33248, 0x0000884A }, /* GL_TEXTURE_DEPTH_SIZE_ARB */ + { 33274, 0x00002300 }, /* GL_TEXTURE_ENV */ + { 33289, 0x00002201 }, /* GL_TEXTURE_ENV_COLOR */ + { 33310, 0x00002200 }, /* GL_TEXTURE_ENV_MODE */ + { 33330, 0x00008500 }, /* GL_TEXTURE_FILTER_CONTROL */ + { 33356, 0x00002500 }, /* GL_TEXTURE_GEN_MODE */ + { 33376, 0x00000C63 }, /* GL_TEXTURE_GEN_Q */ + { 33393, 0x00000C62 }, /* GL_TEXTURE_GEN_R */ + { 33410, 0x00000C60 }, /* GL_TEXTURE_GEN_S */ + { 33427, 0x00000C61 }, /* GL_TEXTURE_GEN_T */ + { 33444, 0x0000819D }, /* GL_TEXTURE_GEQUAL_R_SGIX */ + { 33469, 0x0000805D }, /* GL_TEXTURE_GREEN_SIZE */ + { 33491, 0x0000805D }, /* GL_TEXTURE_GREEN_SIZE_EXT */ + { 33517, 0x00001001 }, /* GL_TEXTURE_HEIGHT */ + { 33535, 0x000080ED }, /* GL_TEXTURE_INDEX_SIZE_EXT */ + { 33561, 0x00008061 }, /* GL_TEXTURE_INTENSITY_SIZE */ + { 33587, 0x00008061 }, /* GL_TEXTURE_INTENSITY_SIZE_EXT */ + { 33617, 0x00001003 }, /* GL_TEXTURE_INTERNAL_FORMAT */ + { 33644, 0x0000819C }, /* GL_TEXTURE_LEQUAL_R_SGIX */ + { 33669, 0x00008501 }, /* GL_TEXTURE_LOD_BIAS */ + { 33689, 0x00008501 }, /* GL_TEXTURE_LOD_BIAS_EXT */ + { 33713, 0x00008190 }, /* GL_TEXTURE_LOD_BIAS_R_SGIX */ + { 33740, 0x0000818E }, /* GL_TEXTURE_LOD_BIAS_S_SGIX */ + { 33767, 0x0000818F }, /* GL_TEXTURE_LOD_BIAS_T_SGIX */ + { 33794, 0x00008060 }, /* GL_TEXTURE_LUMINANCE_SIZE */ + { 33820, 0x00008060 }, /* GL_TEXTURE_LUMINANCE_SIZE_EXT */ + { 33850, 0x00002800 }, /* GL_TEXTURE_MAG_FILTER */ + { 33872, 0x00000BA8 }, /* GL_TEXTURE_MATRIX */ + { 33890, 0x000084FE }, /* GL_TEXTURE_MAX_ANISOTROPY_EXT */ + { 33920, 0x0000836B }, /* GL_TEXTURE_MAX_CLAMP_R_SGIX */ + { 33948, 0x00008369 }, /* GL_TEXTURE_MAX_CLAMP_S_SGIX */ + { 33976, 0x0000836A }, /* GL_TEXTURE_MAX_CLAMP_T_SGIX */ + { 34004, 0x0000813D }, /* GL_TEXTURE_MAX_LEVEL */ + { 34025, 0x0000813B }, /* GL_TEXTURE_MAX_LOD */ + { 34044, 0x00002801 }, /* GL_TEXTURE_MIN_FILTER */ + { 34066, 0x0000813A }, /* GL_TEXTURE_MIN_LOD */ + { 34085, 0x00008066 }, /* GL_TEXTURE_PRIORITY */ + { 34105, 0x000084F5 }, /* GL_TEXTURE_RECTANGLE_ARB */ + { 34130, 0x000084F5 }, /* GL_TEXTURE_RECTANGLE_NV */ + { 34154, 0x0000805C }, /* GL_TEXTURE_RED_SIZE */ + { 34174, 0x0000805C }, /* GL_TEXTURE_RED_SIZE_EXT */ + { 34198, 0x00008067 }, /* GL_TEXTURE_RESIDENT */ + { 34218, 0x00000BA5 }, /* GL_TEXTURE_STACK_DEPTH */ + { 34241, 0x00008065 }, /* GL_TEXTURE_TOO_LARGE_EXT */ + { 34266, 0x0000888F }, /* GL_TEXTURE_UNSIGNED_REMAP_MODE_NV */ + { 34300, 0x00001000 }, /* GL_TEXTURE_WIDTH */ + { 34317, 0x00008072 }, /* GL_TEXTURE_WRAP_R */ + { 34335, 0x00002802 }, /* GL_TEXTURE_WRAP_S */ + { 34353, 0x00002803 }, /* GL_TEXTURE_WRAP_T */ + { 34371, 0x000088BF }, /* GL_TIME_ELAPSED_EXT */ + { 34391, 0x00008648 }, /* GL_TRACK_MATRIX_NV */ + { 34410, 0x00008649 }, /* GL_TRACK_MATRIX_TRANSFORM_NV */ + { 34439, 0x00001000 }, /* GL_TRANSFORM_BIT */ + { 34456, 0x000084E6 }, /* GL_TRANSPOSE_COLOR_MATRIX */ + { 34482, 0x000084E6 }, /* GL_TRANSPOSE_COLOR_MATRIX_ARB */ + { 34512, 0x000088B7 }, /* GL_TRANSPOSE_CURRENT_MATRIX_ARB */ + { 34544, 0x000084E3 }, /* GL_TRANSPOSE_MODELVIEW_MATRIX */ + { 34574, 0x000084E3 }, /* GL_TRANSPOSE_MODELVIEW_MATRIX_ARB */ + { 34608, 0x0000862C }, /* GL_TRANSPOSE_NV */ + { 34624, 0x000084E4 }, /* GL_TRANSPOSE_PROJECTION_MATRIX */ + { 34655, 0x000084E4 }, /* GL_TRANSPOSE_PROJECTION_MATRIX_ARB */ + { 34690, 0x000084E5 }, /* GL_TRANSPOSE_TEXTURE_MATRIX */ + { 34718, 0x000084E5 }, /* GL_TRANSPOSE_TEXTURE_MATRIX_ARB */ + { 34750, 0x00000004 }, /* GL_TRIANGLES */ + { 34763, 0x00000006 }, /* GL_TRIANGLE_FAN */ + { 34779, 0x00008615 }, /* GL_TRIANGLE_MESH_SUN */ + { 34800, 0x00000005 }, /* GL_TRIANGLE_STRIP */ + { 34818, 0x00000001 }, /* GL_TRUE */ + { 34826, 0x00000CF5 }, /* GL_UNPACK_ALIGNMENT */ + { 34846, 0x0000806E }, /* GL_UNPACK_IMAGE_HEIGHT */ + { 34869, 0x00000CF1 }, /* GL_UNPACK_LSB_FIRST */ + { 34889, 0x00000CF2 }, /* GL_UNPACK_ROW_LENGTH */ + { 34910, 0x0000806D }, /* GL_UNPACK_SKIP_IMAGES */ + { 34932, 0x00000CF4 }, /* GL_UNPACK_SKIP_PIXELS */ + { 34954, 0x00000CF3 }, /* GL_UNPACK_SKIP_ROWS */ + { 34974, 0x00000CF0 }, /* GL_UNPACK_SWAP_BYTES */ + { 34995, 0x00001401 }, /* GL_UNSIGNED_BYTE */ + { 35012, 0x00008362 }, /* GL_UNSIGNED_BYTE_2_3_3_REV */ + { 35039, 0x00008032 }, /* GL_UNSIGNED_BYTE_3_3_2 */ + { 35062, 0x00001405 }, /* GL_UNSIGNED_INT */ + { 35078, 0x00008036 }, /* GL_UNSIGNED_INT_10_10_10_2 */ + { 35105, 0x000084FA }, /* GL_UNSIGNED_INT_24_8_NV */ + { 35129, 0x00008368 }, /* GL_UNSIGNED_INT_2_10_10_10_REV */ + { 35160, 0x00008035 }, /* GL_UNSIGNED_INT_8_8_8_8 */ + { 35184, 0x00008367 }, /* GL_UNSIGNED_INT_8_8_8_8_REV */ + { 35212, 0x00001403 }, /* GL_UNSIGNED_SHORT */ + { 35230, 0x00008366 }, /* GL_UNSIGNED_SHORT_1_5_5_5_REV */ + { 35260, 0x00008033 }, /* GL_UNSIGNED_SHORT_4_4_4_4 */ + { 35286, 0x00008365 }, /* GL_UNSIGNED_SHORT_4_4_4_4_REV */ + { 35316, 0x00008034 }, /* GL_UNSIGNED_SHORT_5_5_5_1 */ + { 35342, 0x00008363 }, /* GL_UNSIGNED_SHORT_5_6_5 */ + { 35366, 0x00008364 }, /* GL_UNSIGNED_SHORT_5_6_5_REV */ + { 35394, 0x000085BA }, /* GL_UNSIGNED_SHORT_8_8_APPLE */ + { 35422, 0x000085BA }, /* GL_UNSIGNED_SHORT_8_8_MESA */ + { 35449, 0x000085BB }, /* GL_UNSIGNED_SHORT_8_8_REV_APPLE */ + { 35481, 0x000085BB }, /* GL_UNSIGNED_SHORT_8_8_REV_MESA */ + { 35512, 0x00008CA2 }, /* GL_UPPER_LEFT */ + { 35526, 0x00002A20 }, /* GL_V2F */ + { 35533, 0x00002A21 }, /* GL_V3F */ + { 35540, 0x00008B83 }, /* GL_VALIDATE_STATUS */ + { 35559, 0x00001F00 }, /* GL_VENDOR */ + { 35569, 0x00001F02 }, /* GL_VERSION */ + { 35580, 0x00008074 }, /* GL_VERTEX_ARRAY */ + { 35596, 0x000085B5 }, /* GL_VERTEX_ARRAY_BINDING_APPLE */ + { 35626, 0x00008896 }, /* GL_VERTEX_ARRAY_BUFFER_BINDING */ + { 35657, 0x00008896 }, /* GL_VERTEX_ARRAY_BUFFER_BINDING_ARB */ + { 35692, 0x0000808E }, /* GL_VERTEX_ARRAY_POINTER */ + { 35716, 0x0000807A }, /* GL_VERTEX_ARRAY_SIZE */ + { 35737, 0x0000807C }, /* GL_VERTEX_ARRAY_STRIDE */ + { 35760, 0x0000807B }, /* GL_VERTEX_ARRAY_TYPE */ + { 35781, 0x00008650 }, /* GL_VERTEX_ATTRIB_ARRAY0_NV */ + { 35808, 0x0000865A }, /* GL_VERTEX_ATTRIB_ARRAY10_NV */ + { 35836, 0x0000865B }, /* GL_VERTEX_ATTRIB_ARRAY11_NV */ + { 35864, 0x0000865C }, /* GL_VERTEX_ATTRIB_ARRAY12_NV */ + { 35892, 0x0000865D }, /* GL_VERTEX_ATTRIB_ARRAY13_NV */ + { 35920, 0x0000865E }, /* GL_VERTEX_ATTRIB_ARRAY14_NV */ + { 35948, 0x0000865F }, /* GL_VERTEX_ATTRIB_ARRAY15_NV */ + { 35976, 0x00008651 }, /* GL_VERTEX_ATTRIB_ARRAY1_NV */ + { 36003, 0x00008652 }, /* GL_VERTEX_ATTRIB_ARRAY2_NV */ + { 36030, 0x00008653 }, /* GL_VERTEX_ATTRIB_ARRAY3_NV */ + { 36057, 0x00008654 }, /* GL_VERTEX_ATTRIB_ARRAY4_NV */ + { 36084, 0x00008655 }, /* GL_VERTEX_ATTRIB_ARRAY5_NV */ + { 36111, 0x00008656 }, /* GL_VERTEX_ATTRIB_ARRAY6_NV */ + { 36138, 0x00008657 }, /* GL_VERTEX_ATTRIB_ARRAY7_NV */ + { 36165, 0x00008658 }, /* GL_VERTEX_ATTRIB_ARRAY8_NV */ + { 36192, 0x00008659 }, /* GL_VERTEX_ATTRIB_ARRAY9_NV */ + { 36219, 0x0000889F }, /* GL_VERTEX_ATTRIB_ARRAY_BUFFER_BINDING */ + { 36257, 0x0000889F }, /* GL_VERTEX_ATTRIB_ARRAY_BUFFER_BINDING_ARB */ + { 36299, 0x00008622 }, /* GL_VERTEX_ATTRIB_ARRAY_ENABLED */ + { 36330, 0x00008622 }, /* GL_VERTEX_ATTRIB_ARRAY_ENABLED_ARB */ + { 36365, 0x0000886A }, /* GL_VERTEX_ATTRIB_ARRAY_NORMALIZED */ + { 36399, 0x0000886A }, /* GL_VERTEX_ATTRIB_ARRAY_NORMALIZED_ARB */ + { 36437, 0x00008645 }, /* GL_VERTEX_ATTRIB_ARRAY_POINTER */ + { 36468, 0x00008645 }, /* GL_VERTEX_ATTRIB_ARRAY_POINTER_ARB */ + { 36503, 0x00008623 }, /* GL_VERTEX_ATTRIB_ARRAY_SIZE */ + { 36531, 0x00008623 }, /* GL_VERTEX_ATTRIB_ARRAY_SIZE_ARB */ + { 36563, 0x00008624 }, /* GL_VERTEX_ATTRIB_ARRAY_STRIDE */ + { 36593, 0x00008624 }, /* GL_VERTEX_ATTRIB_ARRAY_STRIDE_ARB */ + { 36627, 0x00008625 }, /* GL_VERTEX_ATTRIB_ARRAY_TYPE */ + { 36655, 0x00008625 }, /* GL_VERTEX_ATTRIB_ARRAY_TYPE_ARB */ + { 36687, 0x000086A7 }, /* GL_VERTEX_BLEND_ARB */ + { 36707, 0x00008620 }, /* GL_VERTEX_PROGRAM_ARB */ + { 36729, 0x0000864A }, /* GL_VERTEX_PROGRAM_BINDING_NV */ + { 36758, 0x00008620 }, /* GL_VERTEX_PROGRAM_NV */ + { 36779, 0x00008642 }, /* GL_VERTEX_PROGRAM_POINT_SIZE */ + { 36808, 0x00008642 }, /* GL_VERTEX_PROGRAM_POINT_SIZE_ARB */ + { 36841, 0x00008642 }, /* GL_VERTEX_PROGRAM_POINT_SIZE_NV */ + { 36873, 0x00008643 }, /* GL_VERTEX_PROGRAM_TWO_SIDE */ + { 36900, 0x00008643 }, /* GL_VERTEX_PROGRAM_TWO_SIDE_ARB */ + { 36931, 0x00008643 }, /* GL_VERTEX_PROGRAM_TWO_SIDE_NV */ + { 36961, 0x00008B31 }, /* GL_VERTEX_SHADER */ + { 36978, 0x00008B31 }, /* GL_VERTEX_SHADER_ARB */ + { 36999, 0x00008621 }, /* GL_VERTEX_STATE_PROGRAM_NV */ + { 37026, 0x00000BA2 }, /* GL_VIEWPORT */ + { 37038, 0x00000800 }, /* GL_VIEWPORT_BIT */ + { 37054, 0x000086AD }, /* GL_WEIGHT_ARRAY_ARB */ + { 37074, 0x0000889E }, /* GL_WEIGHT_ARRAY_BUFFER_BINDING */ + { 37105, 0x0000889E }, /* GL_WEIGHT_ARRAY_BUFFER_BINDING_ARB */ + { 37140, 0x000086AC }, /* GL_WEIGHT_ARRAY_POINTER_ARB */ + { 37168, 0x000086AB }, /* GL_WEIGHT_ARRAY_SIZE_ARB */ + { 37193, 0x000086AA }, /* GL_WEIGHT_ARRAY_STRIDE_ARB */ + { 37220, 0x000086A9 }, /* GL_WEIGHT_ARRAY_TYPE_ARB */ + { 37245, 0x000086A6 }, /* GL_WEIGHT_SUM_UNITY_ARB */ + { 37269, 0x000081D4 }, /* GL_WRAP_BORDER_SUN */ + { 37288, 0x000088B9 }, /* GL_WRITE_ONLY */ + { 37302, 0x000088B9 }, /* GL_WRITE_ONLY_ARB */ + { 37320, 0x00001506 }, /* GL_XOR */ + { 37327, 0x000085B9 }, /* GL_YCBCR_422_APPLE */ + { 37346, 0x00008757 }, /* GL_YCBCR_MESA */ + { 37360, 0x00000000 }, /* GL_ZERO */ + { 37368, 0x00000D16 }, /* GL_ZOOM_X */ + { 37378, 0x00000D17 }, /* GL_ZOOM_Y */ }; static const unsigned reduced_enums[1277] = @@ -3521,9 +3529,9 @@ static const unsigned reduced_enums[1277] = 643, /* GL_LINES */ 645, /* GL_LINE_LOOP */ 652, /* GL_LINE_STRIP */ - 1628, /* GL_TRIANGLES */ - 1631, /* GL_TRIANGLE_STRIP */ - 1629, /* GL_TRIANGLE_FAN */ + 1632, /* GL_TRIANGLES */ + 1635, /* GL_TRIANGLE_STRIP */ + 1633, /* GL_TRIANGLE_FAN */ 1206, /* GL_QUADS */ 1208, /* GL_QUAD_STRIP */ 1096, /* GL_POLYGON */ @@ -3646,24 +3654,24 @@ static const unsigned reduced_enums[1277] = 320, /* GL_DEPTH_CLEAR_VALUE */ 331, /* GL_DEPTH_FUNC */ 12, /* GL_ACCUM_CLEAR_VALUE */ - 1413, /* GL_STENCIL_TEST */ - 1401, /* GL_STENCIL_CLEAR_VALUE */ - 1403, /* GL_STENCIL_FUNC */ - 1415, /* GL_STENCIL_VALUE_MASK */ - 1402, /* GL_STENCIL_FAIL */ - 1410, /* GL_STENCIL_PASS_DEPTH_FAIL */ - 1411, /* GL_STENCIL_PASS_DEPTH_PASS */ - 1412, /* GL_STENCIL_REF */ - 1416, /* GL_STENCIL_WRITEMASK */ + 1417, /* GL_STENCIL_TEST */ + 1405, /* GL_STENCIL_CLEAR_VALUE */ + 1407, /* GL_STENCIL_FUNC */ + 1419, /* GL_STENCIL_VALUE_MASK */ + 1406, /* GL_STENCIL_FAIL */ + 1414, /* GL_STENCIL_PASS_DEPTH_FAIL */ + 1415, /* GL_STENCIL_PASS_DEPTH_PASS */ + 1416, /* GL_STENCIL_REF */ + 1420, /* GL_STENCIL_WRITEMASK */ 789, /* GL_MATRIX_MODE */ 955, /* GL_NORMALIZE */ - 1718, /* GL_VIEWPORT */ + 1722, /* GL_VIEWPORT */ 929, /* GL_MODELVIEW_STACK_DEPTH */ 1188, /* GL_PROJECTION_STACK_DEPTH */ - 1607, /* GL_TEXTURE_STACK_DEPTH */ + 1611, /* GL_TEXTURE_STACK_DEPTH */ 927, /* GL_MODELVIEW_MATRIX */ 1187, /* GL_PROJECTION_MATRIX */ - 1592, /* GL_TEXTURE_MATRIX */ + 1596, /* GL_TEXTURE_MATRIX */ 61, /* GL_ATTRIB_STACK_DEPTH */ 127, /* GL_CLIENT_ATTRIB_STACK_DEPTH */ 43, /* GL_ALPHA_TEST */ @@ -3688,17 +3696,17 @@ static const unsigned reduced_enums[1277] = 585, /* GL_INDEX_MODE */ 1282, /* GL_RGBA_MODE */ 352, /* GL_DOUBLEBUFFER */ - 1417, /* GL_STEREO */ + 1421, /* GL_STEREO */ 1241, /* GL_RENDER_MODE */ 1040, /* GL_PERSPECTIVE_CORRECTION_HINT */ 1089, /* GL_POINT_SMOOTH_HINT */ 648, /* GL_LINE_SMOOTH_HINT */ 1106, /* GL_POLYGON_SMOOTH_HINT */ 477, /* GL_FOG_HINT */ - 1573, /* GL_TEXTURE_GEN_S */ - 1574, /* GL_TEXTURE_GEN_T */ - 1572, /* GL_TEXTURE_GEN_R */ - 1571, /* GL_TEXTURE_GEN_Q */ + 1577, /* GL_TEXTURE_GEN_S */ + 1578, /* GL_TEXTURE_GEN_T */ + 1576, /* GL_TEXTURE_GEN_R */ + 1575, /* GL_TEXTURE_GEN_Q */ 1053, /* GL_PIXEL_MAP_I_TO_I */ 1059, /* GL_PIXEL_MAP_S_TO_S */ 1055, /* GL_PIXEL_MAP_I_TO_R */ @@ -3719,12 +3727,12 @@ static const unsigned reduced_enums[1277] = 1046, /* GL_PIXEL_MAP_G_TO_G_SIZE */ 1044, /* GL_PIXEL_MAP_B_TO_B_SIZE */ 1042, /* GL_PIXEL_MAP_A_TO_A_SIZE */ - 1640, /* GL_UNPACK_SWAP_BYTES */ - 1635, /* GL_UNPACK_LSB_FIRST */ - 1636, /* GL_UNPACK_ROW_LENGTH */ - 1639, /* GL_UNPACK_SKIP_ROWS */ - 1638, /* GL_UNPACK_SKIP_PIXELS */ - 1633, /* GL_UNPACK_ALIGNMENT */ + 1644, /* GL_UNPACK_SWAP_BYTES */ + 1639, /* GL_UNPACK_LSB_FIRST */ + 1640, /* GL_UNPACK_ROW_LENGTH */ + 1643, /* GL_UNPACK_SKIP_ROWS */ + 1642, /* GL_UNPACK_SKIP_PIXELS */ + 1637, /* GL_UNPACK_ALIGNMENT */ 1028, /* GL_PACK_SWAP_BYTES */ 1023, /* GL_PACK_LSB_FIRST */ 1024, /* GL_PACK_ROW_LENGTH */ @@ -3737,8 +3745,8 @@ static const unsigned reduced_enums[1277] = 586, /* GL_INDEX_OFFSET */ 1230, /* GL_RED_SCALE */ 1228, /* GL_RED_BIAS */ - 1735, /* GL_ZOOM_X */ - 1736, /* GL_ZOOM_Y */ + 1739, /* GL_ZOOM_X */ + 1740, /* GL_ZOOM_Y */ 549, /* GL_GREEN_SCALE */ 547, /* GL_GREEN_BIAS */ 92, /* GL_BLUE_SCALE */ @@ -3759,14 +3767,14 @@ static const unsigned reduced_enums[1277] = 863, /* GL_MAX_TEXTURE_STACK_DEPTH */ 877, /* GL_MAX_VIEWPORT_DIMS */ 794, /* GL_MAX_CLIENT_ATTRIB_STACK_DEPTH */ - 1424, /* GL_SUBPIXEL_BITS */ + 1428, /* GL_SUBPIXEL_BITS */ 582, /* GL_INDEX_BITS */ 1229, /* GL_RED_BITS */ 548, /* GL_GREEN_BITS */ 91, /* GL_BLUE_BITS */ 41, /* GL_ALPHA_BITS */ 315, /* GL_DEPTH_BITS */ - 1399, /* GL_STENCIL_BITS */ + 1403, /* GL_STENCIL_BITS */ 14, /* GL_ACCUM_RED_BITS */ 13, /* GL_ACCUM_GREEN_BITS */ 10, /* GL_ACCUM_BLUE_BITS */ @@ -3795,18 +3803,18 @@ static const unsigned reduced_enums[1277] = 690, /* GL_MAP1_GRID_SEGMENTS */ 716, /* GL_MAP2_GRID_DOMAIN */ 717, /* GL_MAP2_GRID_SEGMENTS */ - 1501, /* GL_TEXTURE_1D */ - 1502, /* GL_TEXTURE_2D */ + 1505, /* GL_TEXTURE_1D */ + 1506, /* GL_TEXTURE_2D */ 438, /* GL_FEEDBACK_BUFFER_POINTER */ 439, /* GL_FEEDBACK_BUFFER_SIZE */ 440, /* GL_FEEDBACK_BUFFER_TYPE */ 1325, /* GL_SELECTION_BUFFER_POINTER */ 1326, /* GL_SELECTION_BUFFER_SIZE */ - 1610, /* GL_TEXTURE_WIDTH */ - 1578, /* GL_TEXTURE_HEIGHT */ - 1534, /* GL_TEXTURE_COMPONENTS */ - 1518, /* GL_TEXTURE_BORDER_COLOR */ - 1517, /* GL_TEXTURE_BORDER */ + 1614, /* GL_TEXTURE_WIDTH */ + 1582, /* GL_TEXTURE_HEIGHT */ + 1538, /* GL_TEXTURE_COMPONENTS */ + 1522, /* GL_TEXTURE_BORDER_COLOR */ + 1521, /* GL_TEXTURE_BORDER */ 344, /* GL_DONT_CARE */ 436, /* GL_FASTEST */ 951, /* GL_NICEST */ @@ -3823,11 +3831,11 @@ static const unsigned reduced_enums[1277] = 218, /* GL_COMPILE */ 219, /* GL_COMPILE_AND_EXECUTE */ 111, /* GL_BYTE */ - 1641, /* GL_UNSIGNED_BYTE */ + 1645, /* GL_UNSIGNED_BYTE */ 1339, /* GL_SHORT */ - 1650, /* GL_UNSIGNED_SHORT */ + 1654, /* GL_UNSIGNED_SHORT */ 590, /* GL_INT */ - 1644, /* GL_UNSIGNED_INT */ + 1648, /* GL_UNSIGNED_INT */ 443, /* GL_FLOAT */ 1, /* GL_2_BYTES */ 5, /* GL_3_BYTES */ @@ -3839,7 +3847,7 @@ static const unsigned reduced_enums[1277] = 268, /* GL_COPY */ 50, /* GL_AND_INVERTED */ 953, /* GL_NOOP */ - 1731, /* GL_XOR */ + 1735, /* GL_XOR */ 1015, /* GL_OR */ 954, /* GL_NOR */ 426, /* GL_EQUIV */ @@ -3855,12 +3863,12 @@ static const unsigned reduced_enums[1277] = 165, /* GL_COLOR_INDEXES */ 894, /* GL_MODELVIEW */ 1186, /* GL_PROJECTION */ - 1436, /* GL_TEXTURE */ + 1440, /* GL_TEXTURE */ 138, /* GL_COLOR */ 312, /* GL_DEPTH */ 1390, /* GL_STENCIL */ 164, /* GL_COLOR_INDEX */ - 1404, /* GL_STENCIL_INDEX */ + 1408, /* GL_STENCIL_INDEX */ 321, /* GL_DEPTH_COMPONENT */ 1225, /* GL_RED */ 546, /* GL_GREEN */ @@ -3883,23 +3891,23 @@ static const unsigned reduced_enums[1277] = 1243, /* GL_REPLACE */ 573, /* GL_INCR */ 308, /* GL_DECR */ - 1665, /* GL_VENDOR */ + 1669, /* GL_VENDOR */ 1240, /* GL_RENDERER */ - 1666, /* GL_VERSION */ + 1670, /* GL_VERSION */ 430, /* GL_EXTENSIONS */ 1289, /* GL_S */ - 1427, /* GL_T */ + 1431, /* GL_T */ 1215, /* GL_R */ 1204, /* GL_Q */ 930, /* GL_MODULATE */ 307, /* GL_DECAL */ - 1568, /* GL_TEXTURE_ENV_MODE */ - 1567, /* GL_TEXTURE_ENV_COLOR */ - 1566, /* GL_TEXTURE_ENV */ + 1572, /* GL_TEXTURE_ENV_MODE */ + 1571, /* GL_TEXTURE_ENV_COLOR */ + 1570, /* GL_TEXTURE_ENV */ 431, /* GL_EYE_LINEAR */ 977, /* GL_OBJECT_LINEAR */ 1369, /* GL_SPHERE_MAP */ - 1570, /* GL_TEXTURE_GEN_MODE */ + 1574, /* GL_TEXTURE_GEN_MODE */ 979, /* GL_OBJECT_PLANE */ 432, /* GL_EYE_PLANE */ 945, /* GL_NEAREST */ @@ -3908,30 +3916,30 @@ static const unsigned reduced_enums[1277] = 642, /* GL_LINEAR_MIPMAP_NEAREST */ 948, /* GL_NEAREST_MIPMAP_LINEAR */ 641, /* GL_LINEAR_MIPMAP_LINEAR */ - 1591, /* GL_TEXTURE_MAG_FILTER */ - 1599, /* GL_TEXTURE_MIN_FILTER */ - 1612, /* GL_TEXTURE_WRAP_S */ - 1613, /* GL_TEXTURE_WRAP_T */ + 1595, /* GL_TEXTURE_MAG_FILTER */ + 1603, /* GL_TEXTURE_MIN_FILTER */ + 1616, /* GL_TEXTURE_WRAP_S */ + 1617, /* GL_TEXTURE_WRAP_T */ 117, /* GL_CLAMP */ 1242, /* GL_REPEAT */ 1104, /* GL_POLYGON_OFFSET_UNITS */ 1103, /* GL_POLYGON_OFFSET_POINT */ 1102, /* GL_POLYGON_OFFSET_LINE */ 1216, /* GL_R3_G3_B2 */ - 1662, /* GL_V2F */ - 1663, /* GL_V3F */ + 1666, /* GL_V2F */ + 1667, /* GL_V3F */ 114, /* GL_C4UB_V2F */ 115, /* GL_C4UB_V3F */ 112, /* GL_C3F_V3F */ 942, /* GL_N3F_V3F */ 113, /* GL_C4F_N3F_V3F */ - 1432, /* GL_T2F_V3F */ - 1434, /* GL_T4F_V4F */ - 1430, /* GL_T2F_C4UB_V3F */ - 1428, /* GL_T2F_C3F_V3F */ - 1431, /* GL_T2F_N3F_V3F */ - 1429, /* GL_T2F_C4F_N3F_V3F */ - 1433, /* GL_T4F_C4F_N3F_V4F */ + 1436, /* GL_T2F_V3F */ + 1438, /* GL_T4F_V4F */ + 1434, /* GL_T2F_C4UB_V3F */ + 1432, /* GL_T2F_C3F_V3F */ + 1435, /* GL_T2F_N3F_V3F */ + 1433, /* GL_T2F_C4F_N3F_V3F */ + 1437, /* GL_T4F_C4F_N3F_V4F */ 130, /* GL_CLIP_PLANE0 */ 131, /* GL_CLIP_PLANE1 */ 132, /* GL_CLIP_PLANE2 */ @@ -3991,12 +3999,12 @@ static const unsigned reduced_enums[1277] = 879, /* GL_MINMAX */ 881, /* GL_MINMAX_FORMAT */ 883, /* GL_MINMAX_SINK */ - 1435, /* GL_TABLE_TOO_LARGE_EXT */ - 1643, /* GL_UNSIGNED_BYTE_3_3_2 */ - 1652, /* GL_UNSIGNED_SHORT_4_4_4_4 */ - 1654, /* GL_UNSIGNED_SHORT_5_5_5_1 */ - 1648, /* GL_UNSIGNED_INT_8_8_8_8 */ - 1645, /* GL_UNSIGNED_INT_10_10_10_2 */ + 1439, /* GL_TABLE_TOO_LARGE_EXT */ + 1647, /* GL_UNSIGNED_BYTE_3_3_2 */ + 1656, /* GL_UNSIGNED_SHORT_4_4_4_4 */ + 1658, /* GL_UNSIGNED_SHORT_5_5_5_1 */ + 1652, /* GL_UNSIGNED_INT_8_8_8_8 */ + 1649, /* GL_UNSIGNED_INT_10_10_10_2 */ 1101, /* GL_POLYGON_OFFSET_FILL */ 1100, /* GL_POLYGON_OFFSET_FACTOR */ 1099, /* GL_POLYGON_OFFSET_BIAS */ @@ -4034,39 +4042,39 @@ static const unsigned reduced_enums[1277] = 1251, /* GL_RGB10_A2 */ 1269, /* GL_RGBA12 */ 1271, /* GL_RGBA16 */ - 1604, /* GL_TEXTURE_RED_SIZE */ - 1576, /* GL_TEXTURE_GREEN_SIZE */ - 1515, /* GL_TEXTURE_BLUE_SIZE */ - 1504, /* GL_TEXTURE_ALPHA_SIZE */ - 1589, /* GL_TEXTURE_LUMINANCE_SIZE */ - 1580, /* GL_TEXTURE_INTENSITY_SIZE */ + 1608, /* GL_TEXTURE_RED_SIZE */ + 1580, /* GL_TEXTURE_GREEN_SIZE */ + 1519, /* GL_TEXTURE_BLUE_SIZE */ + 1508, /* GL_TEXTURE_ALPHA_SIZE */ + 1593, /* GL_TEXTURE_LUMINANCE_SIZE */ + 1584, /* GL_TEXTURE_INTENSITY_SIZE */ 1244, /* GL_REPLACE_EXT */ 1194, /* GL_PROXY_TEXTURE_1D */ 1196, /* GL_PROXY_TEXTURE_2D */ - 1608, /* GL_TEXTURE_TOO_LARGE_EXT */ - 1601, /* GL_TEXTURE_PRIORITY */ - 1606, /* GL_TEXTURE_RESIDENT */ - 1507, /* GL_TEXTURE_BINDING_1D */ - 1508, /* GL_TEXTURE_BINDING_2D */ - 1509, /* GL_TEXTURE_BINDING_3D */ + 1612, /* GL_TEXTURE_TOO_LARGE_EXT */ + 1605, /* GL_TEXTURE_PRIORITY */ + 1610, /* GL_TEXTURE_RESIDENT */ + 1511, /* GL_TEXTURE_BINDING_1D */ + 1512, /* GL_TEXTURE_BINDING_2D */ + 1513, /* GL_TEXTURE_BINDING_3D */ 1025, /* GL_PACK_SKIP_IMAGES */ 1021, /* GL_PACK_IMAGE_HEIGHT */ - 1637, /* GL_UNPACK_SKIP_IMAGES */ - 1634, /* GL_UNPACK_IMAGE_HEIGHT */ - 1503, /* GL_TEXTURE_3D */ + 1641, /* GL_UNPACK_SKIP_IMAGES */ + 1638, /* GL_UNPACK_IMAGE_HEIGHT */ + 1507, /* GL_TEXTURE_3D */ 1198, /* GL_PROXY_TEXTURE_3D */ - 1563, /* GL_TEXTURE_DEPTH */ - 1611, /* GL_TEXTURE_WRAP_R */ + 1567, /* GL_TEXTURE_DEPTH */ + 1615, /* GL_TEXTURE_WRAP_R */ 792, /* GL_MAX_3D_TEXTURE_SIZE */ - 1667, /* GL_VERTEX_ARRAY */ + 1671, /* GL_VERTEX_ARRAY */ 956, /* GL_NORMAL_ARRAY */ 139, /* GL_COLOR_ARRAY */ 576, /* GL_INDEX_ARRAY */ - 1542, /* GL_TEXTURE_COORD_ARRAY */ + 1546, /* GL_TEXTURE_COORD_ARRAY */ 414, /* GL_EDGE_FLAG_ARRAY */ - 1672, /* GL_VERTEX_ARRAY_SIZE */ - 1674, /* GL_VERTEX_ARRAY_TYPE */ - 1673, /* GL_VERTEX_ARRAY_STRIDE */ + 1676, /* GL_VERTEX_ARRAY_SIZE */ + 1678, /* GL_VERTEX_ARRAY_TYPE */ + 1677, /* GL_VERTEX_ARRAY_STRIDE */ 961, /* GL_NORMAL_ARRAY_TYPE */ 960, /* GL_NORMAL_ARRAY_STRIDE */ 143, /* GL_COLOR_ARRAY_SIZE */ @@ -4074,15 +4082,15 @@ static const unsigned reduced_enums[1277] = 144, /* GL_COLOR_ARRAY_STRIDE */ 581, /* GL_INDEX_ARRAY_TYPE */ 580, /* GL_INDEX_ARRAY_STRIDE */ - 1546, /* GL_TEXTURE_COORD_ARRAY_SIZE */ - 1548, /* GL_TEXTURE_COORD_ARRAY_TYPE */ - 1547, /* GL_TEXTURE_COORD_ARRAY_STRIDE */ + 1550, /* GL_TEXTURE_COORD_ARRAY_SIZE */ + 1552, /* GL_TEXTURE_COORD_ARRAY_TYPE */ + 1551, /* GL_TEXTURE_COORD_ARRAY_STRIDE */ 418, /* GL_EDGE_FLAG_ARRAY_STRIDE */ - 1671, /* GL_VERTEX_ARRAY_POINTER */ + 1675, /* GL_VERTEX_ARRAY_POINTER */ 959, /* GL_NORMAL_ARRAY_POINTER */ 142, /* GL_COLOR_ARRAY_POINTER */ 579, /* GL_INDEX_ARRAY_POINTER */ - 1545, /* GL_TEXTURE_COORD_ARRAY_POINTER */ + 1549, /* GL_TEXTURE_COORD_ARRAY_POINTER */ 417, /* GL_EDGE_FLAG_ARRAY_POINTER */ 935, /* GL_MULTISAMPLE */ 1301, /* GL_SAMPLE_ALPHA_TO_COVERAGE */ @@ -4103,9 +4111,9 @@ static const unsigned reduced_enums[1277] = 1120, /* GL_POST_COLOR_MATRIX_GREEN_BIAS */ 1115, /* GL_POST_COLOR_MATRIX_BLUE_BIAS */ 1111, /* GL_POST_COLOR_MATRIX_ALPHA_BIAS */ - 1525, /* GL_TEXTURE_COLOR_TABLE_SGI */ + 1529, /* GL_TEXTURE_COLOR_TABLE_SGI */ 1199, /* GL_PROXY_TEXTURE_COLOR_TABLE_SGI */ - 1527, /* GL_TEXTURE_COMPARE_FAIL_VALUE_ARB */ + 1531, /* GL_TEXTURE_COMPARE_FAIL_VALUE_ARB */ 80, /* GL_BLEND_DST_RGB */ 88, /* GL_BLEND_SRC_RGB */ 79, /* GL_BLEND_DST_ALPHA */ @@ -4130,7 +4138,7 @@ static const unsigned reduced_enums[1277] = 72, /* GL_BGRA */ 813, /* GL_MAX_ELEMENTS_VERTICES */ 812, /* GL_MAX_ELEMENTS_INDICES */ - 1579, /* GL_TEXTURE_INDEX_SIZE_EXT */ + 1583, /* GL_TEXTURE_INDEX_SIZE_EXT */ 136, /* GL_CLIP_VOLUME_CLIPPING_HINT_EXT */ 1083, /* GL_POINT_SIZE_MIN */ 1079, /* GL_POINT_SIZE_MAX */ @@ -4138,10 +4146,10 @@ static const unsigned reduced_enums[1277] = 1069, /* GL_POINT_DISTANCE_ATTENUATION */ 118, /* GL_CLAMP_TO_BORDER */ 121, /* GL_CLAMP_TO_EDGE */ - 1600, /* GL_TEXTURE_MIN_LOD */ - 1598, /* GL_TEXTURE_MAX_LOD */ - 1506, /* GL_TEXTURE_BASE_LEVEL */ - 1597, /* GL_TEXTURE_MAX_LEVEL */ + 1604, /* GL_TEXTURE_MIN_LOD */ + 1602, /* GL_TEXTURE_MAX_LOD */ + 1510, /* GL_TEXTURE_BASE_LEVEL */ + 1601, /* GL_TEXTURE_MAX_LEVEL */ 570, /* GL_IGNORE_BORDER_HP */ 245, /* GL_CONSTANT_BORDER_HP */ 1245, /* GL_REPLICATE_BORDER_HP */ @@ -4149,51 +4157,51 @@ static const unsigned reduced_enums[1277] = 984, /* GL_OCCLUSION_TEST_HP */ 985, /* GL_OCCLUSION_TEST_RESULT_HP */ 639, /* GL_LINEAR_CLIPMAP_LINEAR_SGIX */ - 1519, /* GL_TEXTURE_CLIPMAP_CENTER_SGIX */ - 1521, /* GL_TEXTURE_CLIPMAP_FRAME_SGIX */ - 1523, /* GL_TEXTURE_CLIPMAP_OFFSET_SGIX */ - 1524, /* GL_TEXTURE_CLIPMAP_VIRTUAL_DEPTH_SGIX */ - 1522, /* GL_TEXTURE_CLIPMAP_LOD_OFFSET_SGIX */ - 1520, /* GL_TEXTURE_CLIPMAP_DEPTH_SGIX */ + 1523, /* GL_TEXTURE_CLIPMAP_CENTER_SGIX */ + 1525, /* GL_TEXTURE_CLIPMAP_FRAME_SGIX */ + 1527, /* GL_TEXTURE_CLIPMAP_OFFSET_SGIX */ + 1528, /* GL_TEXTURE_CLIPMAP_VIRTUAL_DEPTH_SGIX */ + 1526, /* GL_TEXTURE_CLIPMAP_LOD_OFFSET_SGIX */ + 1524, /* GL_TEXTURE_CLIPMAP_DEPTH_SGIX */ 795, /* GL_MAX_CLIPMAP_DEPTH_SGIX */ 796, /* GL_MAX_CLIPMAP_VIRTUAL_DEPTH_SGIX */ 1146, /* GL_POST_TEXTURE_FILTER_BIAS_SGIX */ 1148, /* GL_POST_TEXTURE_FILTER_SCALE_SGIX */ 1145, /* GL_POST_TEXTURE_FILTER_BIAS_RANGE_SGIX */ 1147, /* GL_POST_TEXTURE_FILTER_SCALE_RANGE_SGIX */ - 1587, /* GL_TEXTURE_LOD_BIAS_S_SGIX */ - 1588, /* GL_TEXTURE_LOD_BIAS_T_SGIX */ - 1586, /* GL_TEXTURE_LOD_BIAS_R_SGIX */ + 1591, /* GL_TEXTURE_LOD_BIAS_S_SGIX */ + 1592, /* GL_TEXTURE_LOD_BIAS_T_SGIX */ + 1590, /* GL_TEXTURE_LOD_BIAS_R_SGIX */ 516, /* GL_GENERATE_MIPMAP */ 517, /* GL_GENERATE_MIPMAP_HINT */ 480, /* GL_FOG_OFFSET_SGIX */ 481, /* GL_FOG_OFFSET_VALUE_SGIX */ - 1533, /* GL_TEXTURE_COMPARE_SGIX */ - 1532, /* GL_TEXTURE_COMPARE_OPERATOR_SGIX */ - 1583, /* GL_TEXTURE_LEQUAL_R_SGIX */ - 1575, /* GL_TEXTURE_GEQUAL_R_SGIX */ + 1537, /* GL_TEXTURE_COMPARE_SGIX */ + 1536, /* GL_TEXTURE_COMPARE_OPERATOR_SGIX */ + 1587, /* GL_TEXTURE_LEQUAL_R_SGIX */ + 1579, /* GL_TEXTURE_GEQUAL_R_SGIX */ 322, /* GL_DEPTH_COMPONENT16 */ 325, /* GL_DEPTH_COMPONENT24 */ 328, /* GL_DEPTH_COMPONENT32 */ 273, /* GL_CULL_VERTEX_EXT */ 275, /* GL_CULL_VERTEX_OBJECT_POSITION_EXT */ 274, /* GL_CULL_VERTEX_EYE_POSITION_EXT */ - 1728, /* GL_WRAP_BORDER_SUN */ - 1526, /* GL_TEXTURE_COLOR_WRITEMASK_SGIS */ + 1732, /* GL_WRAP_BORDER_SUN */ + 1530, /* GL_TEXTURE_COLOR_WRITEMASK_SGIS */ 632, /* GL_LIGHT_MODEL_COLOR_CONTROL */ 1340, /* GL_SINGLE_COLOR */ 1328, /* GL_SEPARATE_SPECULAR_COLOR */ 1337, /* GL_SHARED_TEXTURE_PALETTE_EXT */ - 1642, /* GL_UNSIGNED_BYTE_2_3_3_REV */ - 1655, /* GL_UNSIGNED_SHORT_5_6_5 */ - 1656, /* GL_UNSIGNED_SHORT_5_6_5_REV */ - 1653, /* GL_UNSIGNED_SHORT_4_4_4_4_REV */ - 1651, /* GL_UNSIGNED_SHORT_1_5_5_5_REV */ - 1649, /* GL_UNSIGNED_INT_8_8_8_8_REV */ - 1647, /* GL_UNSIGNED_INT_2_10_10_10_REV */ - 1595, /* GL_TEXTURE_MAX_CLAMP_S_SGIX */ - 1596, /* GL_TEXTURE_MAX_CLAMP_T_SGIX */ - 1594, /* GL_TEXTURE_MAX_CLAMP_R_SGIX */ + 1646, /* GL_UNSIGNED_BYTE_2_3_3_REV */ + 1659, /* GL_UNSIGNED_SHORT_5_6_5 */ + 1660, /* GL_UNSIGNED_SHORT_5_6_5_REV */ + 1657, /* GL_UNSIGNED_SHORT_4_4_4_4_REV */ + 1655, /* GL_UNSIGNED_SHORT_1_5_5_5_REV */ + 1653, /* GL_UNSIGNED_INT_8_8_8_8_REV */ + 1651, /* GL_UNSIGNED_INT_2_10_10_10_REV */ + 1599, /* GL_TEXTURE_MAX_CLAMP_S_SGIX */ + 1600, /* GL_TEXTURE_MAX_CLAMP_T_SGIX */ + 1598, /* GL_TEXTURE_MAX_CLAMP_R_SGIX */ 886, /* GL_MIRRORED_REPEAT */ 1284, /* GL_RGB_S3TC */ 1261, /* GL_RGB4_S3TC */ @@ -4226,46 +4234,46 @@ static const unsigned reduced_enums[1277] = 526, /* GL_GL_CURRENT_RASTER_SECONDARY_COLOR */ 28, /* GL_ALIASED_POINT_SIZE_RANGE */ 27, /* GL_ALIASED_LINE_WIDTH_RANGE */ - 1437, /* GL_TEXTURE0 */ - 1439, /* GL_TEXTURE1 */ - 1461, /* GL_TEXTURE2 */ - 1483, /* GL_TEXTURE3 */ - 1489, /* GL_TEXTURE4 */ - 1491, /* GL_TEXTURE5 */ - 1493, /* GL_TEXTURE6 */ - 1495, /* GL_TEXTURE7 */ - 1497, /* GL_TEXTURE8 */ - 1499, /* GL_TEXTURE9 */ - 1440, /* GL_TEXTURE10 */ - 1442, /* GL_TEXTURE11 */ - 1444, /* GL_TEXTURE12 */ - 1446, /* GL_TEXTURE13 */ - 1448, /* GL_TEXTURE14 */ - 1450, /* GL_TEXTURE15 */ - 1452, /* GL_TEXTURE16 */ - 1454, /* GL_TEXTURE17 */ - 1456, /* GL_TEXTURE18 */ - 1458, /* GL_TEXTURE19 */ - 1462, /* GL_TEXTURE20 */ - 1464, /* GL_TEXTURE21 */ - 1466, /* GL_TEXTURE22 */ - 1468, /* GL_TEXTURE23 */ - 1470, /* GL_TEXTURE24 */ - 1472, /* GL_TEXTURE25 */ - 1474, /* GL_TEXTURE26 */ - 1476, /* GL_TEXTURE27 */ - 1478, /* GL_TEXTURE28 */ - 1480, /* GL_TEXTURE29 */ - 1484, /* GL_TEXTURE30 */ - 1486, /* GL_TEXTURE31 */ + 1441, /* GL_TEXTURE0 */ + 1443, /* GL_TEXTURE1 */ + 1465, /* GL_TEXTURE2 */ + 1487, /* GL_TEXTURE3 */ + 1493, /* GL_TEXTURE4 */ + 1495, /* GL_TEXTURE5 */ + 1497, /* GL_TEXTURE6 */ + 1499, /* GL_TEXTURE7 */ + 1501, /* GL_TEXTURE8 */ + 1503, /* GL_TEXTURE9 */ + 1444, /* GL_TEXTURE10 */ + 1446, /* GL_TEXTURE11 */ + 1448, /* GL_TEXTURE12 */ + 1450, /* GL_TEXTURE13 */ + 1452, /* GL_TEXTURE14 */ + 1454, /* GL_TEXTURE15 */ + 1456, /* GL_TEXTURE16 */ + 1458, /* GL_TEXTURE17 */ + 1460, /* GL_TEXTURE18 */ + 1462, /* GL_TEXTURE19 */ + 1466, /* GL_TEXTURE20 */ + 1468, /* GL_TEXTURE21 */ + 1470, /* GL_TEXTURE22 */ + 1472, /* GL_TEXTURE23 */ + 1474, /* GL_TEXTURE24 */ + 1476, /* GL_TEXTURE25 */ + 1478, /* GL_TEXTURE26 */ + 1480, /* GL_TEXTURE27 */ + 1482, /* GL_TEXTURE28 */ + 1484, /* GL_TEXTURE29 */ + 1488, /* GL_TEXTURE30 */ + 1490, /* GL_TEXTURE31 */ 18, /* GL_ACTIVE_TEXTURE */ 124, /* GL_CLIENT_ACTIVE_TEXTURE */ 864, /* GL_MAX_TEXTURE_UNITS */ - 1621, /* GL_TRANSPOSE_MODELVIEW_MATRIX */ - 1624, /* GL_TRANSPOSE_PROJECTION_MATRIX */ - 1626, /* GL_TRANSPOSE_TEXTURE_MATRIX */ - 1618, /* GL_TRANSPOSE_COLOR_MATRIX */ - 1425, /* GL_SUBTRACT */ + 1625, /* GL_TRANSPOSE_MODELVIEW_MATRIX */ + 1628, /* GL_TRANSPOSE_PROJECTION_MATRIX */ + 1630, /* GL_TRANSPOSE_TEXTURE_MATRIX */ + 1622, /* GL_TRANSPOSE_COLOR_MATRIX */ + 1429, /* GL_SUBTRACT */ 853, /* GL_MAX_RENDERBUFFER_SIZE_EXT */ 221, /* GL_COMPRESSED_ALPHA */ 225, /* GL_COMPRESSED_LUMINANCE */ @@ -4273,18 +4281,18 @@ static const unsigned reduced_enums[1277] = 223, /* GL_COMPRESSED_INTENSITY */ 229, /* GL_COMPRESSED_RGB */ 230, /* GL_COMPRESSED_RGBA */ - 1540, /* GL_TEXTURE_COMPRESSION_HINT */ - 1602, /* GL_TEXTURE_RECTANGLE_ARB */ - 1512, /* GL_TEXTURE_BINDING_RECTANGLE_ARB */ + 1544, /* GL_TEXTURE_COMPRESSION_HINT */ + 1606, /* GL_TEXTURE_RECTANGLE_ARB */ + 1516, /* GL_TEXTURE_BINDING_RECTANGLE_ARB */ 1202, /* GL_PROXY_TEXTURE_RECTANGLE_ARB */ 851, /* GL_MAX_RECTANGLE_TEXTURE_SIZE_ARB */ 334, /* GL_DEPTH_STENCIL_NV */ - 1646, /* GL_UNSIGNED_INT_24_8_NV */ + 1650, /* GL_UNSIGNED_INT_24_8_NV */ 860, /* GL_MAX_TEXTURE_LOD_BIAS */ - 1593, /* GL_TEXTURE_MAX_ANISOTROPY_EXT */ + 1597, /* GL_TEXTURE_MAX_ANISOTROPY_EXT */ 861, /* GL_MAX_TEXTURE_MAX_ANISOTROPY_EXT */ - 1569, /* GL_TEXTURE_FILTER_CONTROL */ - 1584, /* GL_TEXTURE_LOD_BIAS */ + 1573, /* GL_TEXTURE_FILTER_CONTROL */ + 1588, /* GL_TEXTURE_LOD_BIAS */ 207, /* GL_COMBINE4 */ 854, /* GL_MAX_SHININESS_NV */ 855, /* GL_MAX_SPOT_EXPONENT_NV */ @@ -4293,14 +4301,14 @@ static const unsigned reduced_enums[1277] = 906, /* GL_MODELVIEW1_ARB */ 962, /* GL_NORMAL_MAP */ 1231, /* GL_REFLECTION_MAP */ - 1549, /* GL_TEXTURE_CUBE_MAP */ - 1510, /* GL_TEXTURE_BINDING_CUBE_MAP */ - 1557, /* GL_TEXTURE_CUBE_MAP_POSITIVE_X */ - 1551, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_X */ - 1559, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Y */ - 1553, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Y */ - 1561, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Z */ - 1555, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Z */ + 1553, /* GL_TEXTURE_CUBE_MAP */ + 1514, /* GL_TEXTURE_BINDING_CUBE_MAP */ + 1561, /* GL_TEXTURE_CUBE_MAP_POSITIVE_X */ + 1555, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_X */ + 1563, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Y */ + 1557, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Y */ + 1565, /* GL_TEXTURE_CUBE_MAP_POSITIVE_Z */ + 1559, /* GL_TEXTURE_CUBE_MAP_NEGATIVE_Z */ 1200, /* GL_PROXY_TEXTURE_CUBE_MAP */ 807, /* GL_MAX_CUBE_MAP_TEXTURE_SIZE */ 941, /* GL_MULTISAMPLE_FILTER_HINT_NV */ @@ -4332,26 +4340,26 @@ static const unsigned reduced_enums[1277] = 1001, /* GL_OPERAND1_ALPHA */ 1007, /* GL_OPERAND2_ALPHA */ 1013, /* GL_OPERAND3_ALPHA_NV */ - 1668, /* GL_VERTEX_ARRAY_BINDING_APPLE */ - 1732, /* GL_YCBCR_422_APPLE */ - 1657, /* GL_UNSIGNED_SHORT_8_8_APPLE */ - 1659, /* GL_UNSIGNED_SHORT_8_8_REV_APPLE */ + 1672, /* GL_VERTEX_ARRAY_BINDING_APPLE */ + 1736, /* GL_YCBCR_422_APPLE */ + 1661, /* GL_UNSIGNED_SHORT_8_8_APPLE */ + 1663, /* GL_UNSIGNED_SHORT_8_8_REV_APPLE */ 1342, /* GL_SLICE_ACCUM_SUN */ 1207, /* GL_QUAD_MESH_SUN */ - 1630, /* GL_TRIANGLE_MESH_SUN */ - 1706, /* GL_VERTEX_PROGRAM_ARB */ - 1717, /* GL_VERTEX_STATE_PROGRAM_NV */ - 1693, /* GL_VERTEX_ATTRIB_ARRAY_ENABLED */ - 1699, /* GL_VERTEX_ATTRIB_ARRAY_SIZE */ - 1701, /* GL_VERTEX_ATTRIB_ARRAY_STRIDE */ - 1703, /* GL_VERTEX_ATTRIB_ARRAY_TYPE */ + 1634, /* GL_TRIANGLE_MESH_SUN */ + 1710, /* GL_VERTEX_PROGRAM_ARB */ + 1721, /* GL_VERTEX_STATE_PROGRAM_NV */ + 1697, /* GL_VERTEX_ATTRIB_ARRAY_ENABLED */ + 1703, /* GL_VERTEX_ATTRIB_ARRAY_SIZE */ + 1705, /* GL_VERTEX_ATTRIB_ARRAY_STRIDE */ + 1707, /* GL_VERTEX_ATTRIB_ARRAY_TYPE */ 300, /* GL_CURRENT_VERTEX_ATTRIB */ 1165, /* GL_PROGRAM_LENGTH_ARB */ 1179, /* GL_PROGRAM_STRING_ARB */ 928, /* GL_MODELVIEW_PROJECTION_NV */ 569, /* GL_IDENTITY_NV */ 614, /* GL_INVERSE_NV */ - 1623, /* GL_TRANSPOSE_NV */ + 1627, /* GL_TRANSPOSE_NV */ 615, /* GL_INVERSE_TRANSPOSE_NV */ 837, /* GL_MAX_PROGRAM_MATRIX_STACK_DEPTH_ARB */ 836, /* GL_MAX_PROGRAM_MATRICES_ARB */ @@ -4365,33 +4373,33 @@ static const unsigned reduced_enums[1277] = 781, /* GL_MATRIX7_NV */ 285, /* GL_CURRENT_MATRIX_STACK_DEPTH_ARB */ 282, /* GL_CURRENT_MATRIX_ARB */ - 1709, /* GL_VERTEX_PROGRAM_POINT_SIZE */ - 1712, /* GL_VERTEX_PROGRAM_TWO_SIDE */ + 1713, /* GL_VERTEX_PROGRAM_POINT_SIZE */ + 1716, /* GL_VERTEX_PROGRAM_TWO_SIDE */ 1177, /* GL_PROGRAM_PARAMETER_NV */ - 1697, /* GL_VERTEX_ATTRIB_ARRAY_POINTER */ + 1701, /* GL_VERTEX_ATTRIB_ARRAY_POINTER */ 1181, /* GL_PROGRAM_TARGET_NV */ 1178, /* GL_PROGRAM_RESIDENT_NV */ - 1615, /* GL_TRACK_MATRIX_NV */ - 1616, /* GL_TRACK_MATRIX_TRANSFORM_NV */ - 1707, /* GL_VERTEX_PROGRAM_BINDING_NV */ + 1619, /* GL_TRACK_MATRIX_NV */ + 1620, /* GL_TRACK_MATRIX_TRANSFORM_NV */ + 1711, /* GL_VERTEX_PROGRAM_BINDING_NV */ 1159, /* GL_PROGRAM_ERROR_POSITION_ARB */ 319, /* GL_DEPTH_CLAMP_NV */ - 1675, /* GL_VERTEX_ATTRIB_ARRAY0_NV */ - 1682, /* GL_VERTEX_ATTRIB_ARRAY1_NV */ - 1683, /* GL_VERTEX_ATTRIB_ARRAY2_NV */ - 1684, /* GL_VERTEX_ATTRIB_ARRAY3_NV */ - 1685, /* GL_VERTEX_ATTRIB_ARRAY4_NV */ - 1686, /* GL_VERTEX_ATTRIB_ARRAY5_NV */ - 1687, /* GL_VERTEX_ATTRIB_ARRAY6_NV */ - 1688, /* GL_VERTEX_ATTRIB_ARRAY7_NV */ - 1689, /* GL_VERTEX_ATTRIB_ARRAY8_NV */ - 1690, /* GL_VERTEX_ATTRIB_ARRAY9_NV */ - 1676, /* GL_VERTEX_ATTRIB_ARRAY10_NV */ - 1677, /* GL_VERTEX_ATTRIB_ARRAY11_NV */ - 1678, /* GL_VERTEX_ATTRIB_ARRAY12_NV */ - 1679, /* GL_VERTEX_ATTRIB_ARRAY13_NV */ - 1680, /* GL_VERTEX_ATTRIB_ARRAY14_NV */ - 1681, /* GL_VERTEX_ATTRIB_ARRAY15_NV */ + 1679, /* GL_VERTEX_ATTRIB_ARRAY0_NV */ + 1686, /* GL_VERTEX_ATTRIB_ARRAY1_NV */ + 1687, /* GL_VERTEX_ATTRIB_ARRAY2_NV */ + 1688, /* GL_VERTEX_ATTRIB_ARRAY3_NV */ + 1689, /* GL_VERTEX_ATTRIB_ARRAY4_NV */ + 1690, /* GL_VERTEX_ATTRIB_ARRAY5_NV */ + 1691, /* GL_VERTEX_ATTRIB_ARRAY6_NV */ + 1692, /* GL_VERTEX_ATTRIB_ARRAY7_NV */ + 1693, /* GL_VERTEX_ATTRIB_ARRAY8_NV */ + 1694, /* GL_VERTEX_ATTRIB_ARRAY9_NV */ + 1680, /* GL_VERTEX_ATTRIB_ARRAY10_NV */ + 1681, /* GL_VERTEX_ATTRIB_ARRAY11_NV */ + 1682, /* GL_VERTEX_ATTRIB_ARRAY12_NV */ + 1683, /* GL_VERTEX_ATTRIB_ARRAY13_NV */ + 1684, /* GL_VERTEX_ATTRIB_ARRAY14_NV */ + 1685, /* GL_VERTEX_ATTRIB_ARRAY15_NV */ 699, /* GL_MAP1_VERTEX_ATTRIB0_4_NV */ 706, /* GL_MAP1_VERTEX_ATTRIB1_4_NV */ 707, /* GL_MAP1_VERTEX_ATTRIB2_4_NV */ @@ -4424,20 +4432,20 @@ static const unsigned reduced_enums[1277] = 730, /* GL_MAP2_VERTEX_ATTRIB13_4_NV */ 731, /* GL_MAP2_VERTEX_ATTRIB14_4_NV */ 732, /* GL_MAP2_VERTEX_ATTRIB15_4_NV */ - 1538, /* GL_TEXTURE_COMPRESSED_IMAGE_SIZE */ - 1535, /* GL_TEXTURE_COMPRESSED */ + 1542, /* GL_TEXTURE_COMPRESSED_IMAGE_SIZE */ + 1539, /* GL_TEXTURE_COMPRESSED */ 967, /* GL_NUM_COMPRESSED_TEXTURE_FORMATS */ 239, /* GL_COMPRESSED_TEXTURE_FORMATS */ 876, /* GL_MAX_VERTEX_UNITS_ARB */ 22, /* GL_ACTIVE_VERTEX_UNITS_ARB */ - 1727, /* GL_WEIGHT_SUM_UNITY_ARB */ - 1705, /* GL_VERTEX_BLEND_ARB */ + 1731, /* GL_WEIGHT_SUM_UNITY_ARB */ + 1709, /* GL_VERTEX_BLEND_ARB */ 302, /* GL_CURRENT_WEIGHT_ARB */ - 1726, /* GL_WEIGHT_ARRAY_TYPE_ARB */ - 1725, /* GL_WEIGHT_ARRAY_STRIDE_ARB */ - 1724, /* GL_WEIGHT_ARRAY_SIZE_ARB */ - 1723, /* GL_WEIGHT_ARRAY_POINTER_ARB */ - 1720, /* GL_WEIGHT_ARRAY_ARB */ + 1730, /* GL_WEIGHT_ARRAY_TYPE_ARB */ + 1729, /* GL_WEIGHT_ARRAY_STRIDE_ARB */ + 1728, /* GL_WEIGHT_ARRAY_SIZE_ARB */ + 1727, /* GL_WEIGHT_ARRAY_POINTER_ARB */ + 1724, /* GL_WEIGHT_ARRAY_ARB */ 345, /* GL_DOT3_RGB */ 346, /* GL_DOT3_RGBA */ 237, /* GL_COMPRESSED_RGB_FXT1_3DFX */ @@ -4482,17 +4490,17 @@ static const unsigned reduced_enums[1277] = 931, /* GL_MODULATE_ADD_ATI */ 932, /* GL_MODULATE_SIGNED_ADD_ATI */ 933, /* GL_MODULATE_SUBTRACT_ATI */ - 1733, /* GL_YCBCR_MESA */ + 1737, /* GL_YCBCR_MESA */ 1022, /* GL_PACK_INVERT_MESA */ 305, /* GL_DEBUG_OBJECT_MESA */ 306, /* GL_DEBUG_PRINT_MESA */ 304, /* GL_DEBUG_ASSERT_MESA */ 107, /* GL_BUFFER_SIZE */ 109, /* GL_BUFFER_USAGE */ - 1393, /* GL_STENCIL_BACK_FUNC */ + 1394, /* GL_STENCIL_BACK_FUNC */ 1392, /* GL_STENCIL_BACK_FAIL */ - 1394, /* GL_STENCIL_BACK_PASS_DEPTH_FAIL */ - 1395, /* GL_STENCIL_BACK_PASS_DEPTH_PASS */ + 1396, /* GL_STENCIL_BACK_PASS_DEPTH_FAIL */ + 1398, /* GL_STENCIL_BACK_PASS_DEPTH_PASS */ 484, /* GL_FRAGMENT_PROGRAM_ARB */ 1156, /* GL_PROGRAM_ALU_INSTRUCTIONS_ARB */ 1184, /* GL_PROGRAM_TEX_INSTRUCTIONS_ARB */ @@ -4534,10 +4542,10 @@ static const unsigned reduced_enums[1277] = 788, /* GL_MATRIX_INDEX_ARRAY_TYPE_ARB */ 787, /* GL_MATRIX_INDEX_ARRAY_STRIDE_ARB */ 785, /* GL_MATRIX_INDEX_ARRAY_POINTER_ARB */ - 1564, /* GL_TEXTURE_DEPTH_SIZE */ + 1568, /* GL_TEXTURE_DEPTH_SIZE */ 338, /* GL_DEPTH_TEXTURE_MODE */ - 1530, /* GL_TEXTURE_COMPARE_MODE */ - 1528, /* GL_TEXTURE_COMPARE_FUNC */ + 1534, /* GL_TEXTURE_COMPARE_MODE */ + 1532, /* GL_TEXTURE_COMPARE_FUNC */ 216, /* GL_COMPARE_R_TO_TEXTURE */ 1090, /* GL_POINT_SPRITE */ 265, /* GL_COORD_REPLACE */ @@ -4547,7 +4555,7 @@ static const unsigned reduced_enums[1277] = 1211, /* GL_QUERY_RESULT */ 1213, /* GL_QUERY_RESULT_AVAILABLE */ 870, /* GL_MAX_VERTEX_ATTRIBS */ - 1695, /* GL_VERTEX_ATTRIB_ARRAY_NORMALIZED */ + 1699, /* GL_VERTEX_ATTRIB_ARRAY_NORMALIZED */ 336, /* GL_DEPTH_STENCIL_TO_RGBA_NV */ 335, /* GL_DEPTH_STENCIL_TO_BGRA_NV */ 856, /* GL_MAX_TEXTURE_COORDS */ @@ -4555,23 +4563,23 @@ static const unsigned reduced_enums[1277] = 1161, /* GL_PROGRAM_ERROR_STRING_ARB */ 1163, /* GL_PROGRAM_FORMAT_ASCII_ARB */ 1162, /* GL_PROGRAM_FORMAT_ARB */ - 1609, /* GL_TEXTURE_UNSIGNED_REMAP_MODE_NV */ + 1613, /* GL_TEXTURE_UNSIGNED_REMAP_MODE_NV */ 317, /* GL_DEPTH_BOUNDS_TEST_EXT */ 316, /* GL_DEPTH_BOUNDS_EXT */ 52, /* GL_ARRAY_BUFFER */ 419, /* GL_ELEMENT_ARRAY_BUFFER */ 54, /* GL_ARRAY_BUFFER_BINDING */ 421, /* GL_ELEMENT_ARRAY_BUFFER_BINDING */ - 1669, /* GL_VERTEX_ARRAY_BUFFER_BINDING */ + 1673, /* GL_VERTEX_ARRAY_BUFFER_BINDING */ 957, /* GL_NORMAL_ARRAY_BUFFER_BINDING */ 140, /* GL_COLOR_ARRAY_BUFFER_BINDING */ 577, /* GL_INDEX_ARRAY_BUFFER_BINDING */ - 1543, /* GL_TEXTURE_COORD_ARRAY_BUFFER_BINDING */ + 1547, /* GL_TEXTURE_COORD_ARRAY_BUFFER_BINDING */ 415, /* GL_EDGE_FLAG_ARRAY_BUFFER_BINDING */ 1318, /* GL_SECONDARY_COLOR_ARRAY_BUFFER_BINDING */ 462, /* GL_FOG_COORDINATE_ARRAY_BUFFER_BINDING */ - 1721, /* GL_WEIGHT_ARRAY_BUFFER_BINDING */ - 1691, /* GL_VERTEX_ATTRIB_ARRAY_BUFFER_BINDING */ + 1725, /* GL_WEIGHT_ARRAY_BUFFER_BINDING */ + 1695, /* GL_VERTEX_ATTRIB_ARRAY_BUFFER_BINDING */ 1164, /* GL_PROGRAM_INSTRUCTIONS_ARB */ 832, /* GL_MAX_PROGRAM_INSTRUCTIONS_ARB */ 1170, /* GL_PROGRAM_NATIVE_INSTRUCTIONS_ARB */ @@ -4595,14 +4603,14 @@ static const unsigned reduced_enums[1277] = 833, /* GL_MAX_PROGRAM_LOCAL_PARAMETERS_ARB */ 829, /* GL_MAX_PROGRAM_ENV_PARAMETERS_ARB */ 1185, /* GL_PROGRAM_UNDER_NATIVE_LIMITS_ARB */ - 1620, /* GL_TRANSPOSE_CURRENT_MATRIX_ARB */ + 1624, /* GL_TRANSPOSE_CURRENT_MATRIX_ARB */ 1221, /* GL_READ_ONLY */ - 1729, /* GL_WRITE_ONLY */ + 1733, /* GL_WRITE_ONLY */ 1223, /* GL_READ_WRITE */ 101, /* GL_BUFFER_ACCESS */ 103, /* GL_BUFFER_MAPPED */ 105, /* GL_BUFFER_MAP_POINTER */ - 1614, /* GL_TIME_ELAPSED_EXT */ + 1618, /* GL_TIME_ELAPSED_EXT */ 744, /* GL_MATRIX0_ARB */ 756, /* GL_MATRIX1_ARB */ 768, /* GL_MATRIX2_ARB */ @@ -4635,9 +4643,9 @@ static const unsigned reduced_enums[1277] = 767, /* GL_MATRIX29_ARB */ 770, /* GL_MATRIX30_ARB */ 771, /* GL_MATRIX31_ARB */ - 1420, /* GL_STREAM_DRAW */ - 1422, /* GL_STREAM_READ */ - 1418, /* GL_STREAM_COPY */ + 1424, /* GL_STREAM_DRAW */ + 1426, /* GL_STREAM_READ */ + 1422, /* GL_STREAM_COPY */ 1386, /* GL_STATIC_DRAW */ 1388, /* GL_STATIC_READ */ 1384, /* GL_STATIC_COPY */ @@ -4653,12 +4661,12 @@ static const unsigned reduced_enums[1277] = 831, /* GL_MAX_PROGRAM_IF_DEPTH_NV */ 835, /* GL_MAX_PROGRAM_LOOP_DEPTH_NV */ 834, /* GL_MAX_PROGRAM_LOOP_COUNT_NV */ - 1414, /* GL_STENCIL_TEST_TWO_SIDE_EXT */ + 1418, /* GL_STENCIL_TEST_TWO_SIDE_EXT */ 17, /* GL_ACTIVE_STENCIL_FACE_EXT */ 891, /* GL_MIRROR_CLAMP_TO_BORDER_EXT */ 1299, /* GL_SAMPLES_PASSED */ 485, /* GL_FRAGMENT_SHADER */ - 1715, /* GL_VERTEX_SHADER */ + 1719, /* GL_VERTEX_SHADER */ 1175, /* GL_PROGRAM_OBJECT_ARB */ 1331, /* GL_SHADER_OBJECT_ARB */ 816, /* GL_MAX_FRAGMENT_UNIFORM_COMPONENTS */ @@ -4696,7 +4704,7 @@ static const unsigned reduced_enums[1277] = 311, /* GL_DELETE_STATUS */ 220, /* GL_COMPILE_STATUS */ 657, /* GL_LINK_STATUS */ - 1664, /* GL_VALIDATE_STATUS */ + 1668, /* GL_VALIDATE_STATUS */ 589, /* GL_INFO_LOG_LENGTH */ 56, /* GL_ATTACHED_SHADERS */ 20, /* GL_ACTIVE_UNIFORMS */ @@ -4733,10 +4741,10 @@ static const unsigned reduced_enums[1277] = 523, /* GL_GL_COMPRESSED_SLUMINANCE_ALPHA */ 1092, /* GL_POINT_SPRITE_COORD_ORIGIN */ 665, /* GL_LOWER_LEFT */ - 1661, /* GL_UPPER_LEFT */ - 1396, /* GL_STENCIL_BACK_REF */ - 1397, /* GL_STENCIL_BACK_VALUE_MASK */ - 1398, /* GL_STENCIL_BACK_WRITEMASK */ + 1665, /* GL_UPPER_LEFT */ + 1400, /* GL_STENCIL_BACK_REF */ + 1401, /* GL_STENCIL_BACK_VALUE_MASK */ + 1402, /* GL_STENCIL_BACK_WRITEMASK */ 402, /* GL_DRAW_FRAMEBUFFER_BINDING_EXT */ 1235, /* GL_RENDERBUFFER_BINDING_EXT */ 1220, /* GL_READ_FRAMEBUFFER_EXT */ @@ -4781,15 +4789,15 @@ static const unsigned reduced_enums[1277] = 1239, /* GL_RENDERBUFFER_WIDTH_EXT */ 1237, /* GL_RENDERBUFFER_HEIGHT_EXT */ 1238, /* GL_RENDERBUFFER_INTERNAL_FORMAT_EXT */ - 1409, /* GL_STENCIL_INDEX_EXT */ - 1406, /* GL_STENCIL_INDEX1_EXT */ - 1407, /* GL_STENCIL_INDEX4_EXT */ - 1408, /* GL_STENCIL_INDEX8_EXT */ - 1405, /* GL_STENCIL_INDEX16_EXT */ + 1413, /* GL_STENCIL_INDEX_EXT */ + 1410, /* GL_STENCIL_INDEX1_EXT */ + 1411, /* GL_STENCIL_INDEX4_EXT */ + 1412, /* GL_STENCIL_INDEX8_EXT */ + 1409, /* GL_STENCIL_INDEX16_EXT */ 427, /* GL_EVAL_BIT */ 1217, /* GL_RASTER_POSITION_UNCLIPPED_IBM */ 659, /* GL_LIST_BIT */ - 1514, /* GL_TEXTURE_BIT */ + 1518, /* GL_TEXTURE_BIT */ 1314, /* GL_SCISSOR_BIT */ 29, /* GL_ALL_ATTRIB_BITS */ 938, /* GL_MULTISAMPLE_BIT */ diff --git a/reactos/dll/3rdparty/mesa32/src/main/fbobject.c b/reactos/dll/3rdparty/mesa32/src/main/fbobject.c index eac2f787171..8e7d66cb9c9 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/fbobject.c +++ b/reactos/dll/3rdparty/mesa32/src/main/fbobject.c @@ -150,22 +150,18 @@ _mesa_remove_attachment(GLcontext *ctx, struct gl_renderbuffer_attachment *att) { if (att->Type == GL_TEXTURE) { ASSERT(att->Texture); - att->Texture->RefCount--; - if (att->Texture->RefCount == 0) { - ctx->Driver.DeleteTexture(ctx, att->Texture); + if (ctx->Driver.FinishRenderTexture) { + /* tell driver we're done rendering to this texobj */ + ctx->Driver.FinishRenderTexture(ctx, att); } - else { - /* tell driver that we're done rendering to this texture. */ - if (ctx->Driver.FinishRenderTexture) { - ctx->Driver.FinishRenderTexture(ctx, att); - } - } - att->Texture = NULL; + _mesa_reference_texobj(&att->Texture, NULL); /* unbind */ + ASSERT(!att->Texture); } if (att->Type == GL_TEXTURE || att->Type == GL_RENDERBUFFER_EXT) { ASSERT(att->Renderbuffer); ASSERT(!att->Texture); - _mesa_reference_renderbuffer(&att->Renderbuffer, NULL); + _mesa_reference_renderbuffer(&att->Renderbuffer, NULL); /* unbind */ + ASSERT(!att->Renderbuffer); } att->Type = GL_NONE; att->Complete = GL_TRUE; @@ -191,8 +187,8 @@ _mesa_set_texture_attachment(GLcontext *ctx, /* new attachment */ _mesa_remove_attachment(ctx, att); att->Type = GL_TEXTURE; - att->Texture = texObj; - texObj->RefCount++; + assert(!att->Texture); + _mesa_reference_texobj(&att->Texture, texObj); } /* always update these fields */ @@ -983,6 +979,7 @@ _mesa_BindFramebufferEXT(GLenum target, GLuint framebuffer) return; } _mesa_HashInsert(ctx->Shared->FrameBuffers, framebuffer, newFb); + ASSERT(newFb->RefCount == 1); } } else { @@ -1006,8 +1003,10 @@ _mesa_BindFramebufferEXT(GLenum target, GLuint framebuffer) if (bindDrawBuf) { /* check if old FB had any texture attachments */ check_end_texture_render(ctx, ctx->DrawBuffer); - /* check if time to delete this framebuffer */ + + /* bind new drawing buffer */ _mesa_reference_framebuffer(&ctx->DrawBuffer, newFb); + if (newFb->Name != 0) { /* check if newly bound framebuffer has any texture attachments */ check_begin_texture_render(ctx, newFb); diff --git a/reactos/dll/3rdparty/mesa32/src/main/framebuffer.c b/reactos/dll/3rdparty/mesa32/src/main/framebuffer.c index 1fd31a53211..8aeb3695088 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/framebuffer.c +++ b/reactos/dll/3rdparty/mesa32/src/main/framebuffer.c @@ -38,6 +38,7 @@ #include "fbobject.h" #include "framebuffer.h" #include "renderbuffer.h" +#include "texobj.h" @@ -190,17 +191,11 @@ _mesa_free_framebuffer_data(struct gl_framebuffer *fb) _mesa_reference_renderbuffer(&att->Renderbuffer, NULL); } if (att->Texture) { - /* render to texture */ - att->Texture->RefCount--; - if (att->Texture->RefCount == 0) { - GET_CURRENT_CONTEXT(ctx); - if (ctx) { - ctx->Driver.DeleteTexture(ctx, att->Texture); - } - } + _mesa_reference_texobj(&att->Texture, NULL); } + ASSERT(!att->Renderbuffer); + ASSERT(!att->Texture); att->Type = GL_NONE; - att->Texture = NULL; } /* unbind _Depth/_StencilBuffer to decr ref counts */ diff --git a/reactos/dll/3rdparty/mesa32/src/main/glheader.h b/reactos/dll/3rdparty/mesa32/src/main/glheader.h index fd4127558a8..2d2da49fe5b 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/glheader.h +++ b/reactos/dll/3rdparty/mesa32/src/main/glheader.h @@ -237,7 +237,7 @@ #endif -#if !defined __GNUC__ || __GNUC__ < 3 +#if (!defined(__GNUC__) || __GNUC__ < 3) && !defined(__IBMC__) # define __builtin_expect(x, y) x #endif diff --git a/reactos/dll/3rdparty/mesa32/src/main/image.c b/reactos/dll/3rdparty/mesa32/src/main/image.c index 803f4785c0a..d7a96f70d9a 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/image.c +++ b/reactos/dll/3rdparty/mesa32/src/main/image.c @@ -3794,7 +3794,7 @@ _mesa_pack_stencil_span( const GLcontext *ctx, GLuint n, GLint *dst = (GLint *) dest; GLuint i; for (i=0;iSwapBytes) { _mesa_swap4( (GLuint *) dst, n ); diff --git a/reactos/dll/3rdparty/mesa32/src/main/light.c b/reactos/dll/3rdparty/mesa32/src/main/light.c index 6e057614bad..6dd334e16dc 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/light.c +++ b/reactos/dll/3rdparty/mesa32/src/main/light.c @@ -53,6 +53,11 @@ _mesa_ShadeModel( GLenum mode ) FLUSH_VERTICES(ctx, _NEW_LIGHT); ctx->Light.ShadeModel = mode; + if (mode == GL_FLAT) + ctx->_TriangleCaps |= DD_FLATSHADE; + else + ctx->_TriangleCaps &= ~DD_FLATSHADE; + if (ctx->Driver.ShadeModel) ctx->Driver.ShadeModel( ctx, mode ); } @@ -441,6 +446,10 @@ _mesa_LightModelfv( GLenum pname, const GLfloat *params ) return; FLUSH_VERTICES(ctx, _NEW_LIGHT); ctx->Light.Model.TwoSide = newbool; + if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) + ctx->_TriangleCaps |= DD_TRI_LIGHT_TWOSIDE; + else + ctx->_TriangleCaps &= ~DD_TRI_LIGHT_TWOSIDE; break; case GL_LIGHT_MODEL_COLOR_CONTROL: if (params[0] == (GLfloat) GL_SINGLE_COLOR) diff --git a/reactos/dll/3rdparty/mesa32/src/main/lines.c b/reactos/dll/3rdparty/mesa32/src/main/lines.c index dc7195d4ebf..b464c4f59ed 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/lines.c +++ b/reactos/dll/3rdparty/mesa32/src/main/lines.c @@ -59,6 +59,11 @@ _mesa_LineWidth( GLfloat width ) ctx->Const.MinLineWidth, ctx->Const.MaxLineWidth); + if (width != 1.0F) + ctx->_TriangleCaps |= DD_LINE_WIDTH; + else + ctx->_TriangleCaps &= ~DD_LINE_WIDTH; + if (ctx->Driver.LineWidth) ctx->Driver.LineWidth(ctx, width); } diff --git a/reactos/dll/3rdparty/mesa32/src/main/mtypes.h b/reactos/dll/3rdparty/mesa32/src/main/mtypes.h index 71215d54709..d00f2efc716 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/mtypes.h +++ b/reactos/dll/3rdparty/mesa32/src/main/mtypes.h @@ -1523,12 +1523,6 @@ struct gl_texture_unit struct gl_texture_object *_Current; /**< Points to really enabled tex obj */ - struct gl_texture_object Saved1D; /**< only used by glPush/PopAttrib */ - struct gl_texture_object Saved2D; - struct gl_texture_object Saved3D; - struct gl_texture_object SavedCubeMap; - struct gl_texture_object SavedRect; - /* GL_SGI_texture_color_table */ struct gl_color_table ColorTable; struct gl_color_table ProxyColorTable; @@ -2848,7 +2842,6 @@ struct mesa_display_list */ struct gl_dlist_state { - struct mesa_display_list *CallStack[MAX_LIST_NESTING]; GLuint CallDepth; /**< Current recursion calling depth */ struct mesa_display_list *CurrentList; diff --git a/reactos/dll/3rdparty/mesa32/src/main/points.c b/reactos/dll/3rdparty/mesa32/src/main/points.c index 408b68a7430..8825bb18192 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/points.c +++ b/reactos/dll/3rdparty/mesa32/src/main/points.c @@ -123,9 +123,15 @@ _mesa_PointParameterfvEXT( GLenum pname, const GLfloat *params) return; FLUSH_VERTICES(ctx, _NEW_POINT); COPY_3V(ctx->Point.Params, params); + ctx->Point._Attenuated = (ctx->Point.Params[0] != 1.0 || ctx->Point.Params[1] != 0.0 || ctx->Point.Params[2] != 0.0); + + if (ctx->Point._Attenuated) + ctx->_TriangleCaps |= DD_POINT_ATTEN; + else + ctx->_TriangleCaps &= ~DD_POINT_ATTEN; } else { _mesa_error(ctx, GL_INVALID_ENUM, diff --git a/reactos/dll/3rdparty/mesa32/src/main/polygon.c b/reactos/dll/3rdparty/mesa32/src/main/polygon.c index fd02e5a652d..564250b881c 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/polygon.c +++ b/reactos/dll/3rdparty/mesa32/src/main/polygon.c @@ -167,6 +167,11 @@ _mesa_PolygonMode( GLenum face, GLenum mode ) return; } + if (ctx->Polygon.FrontMode == GL_FILL && ctx->Polygon.BackMode == GL_FILL) + ctx->_TriangleCaps &= ~DD_TRI_UNFILLED; + else + ctx->_TriangleCaps |= DD_TRI_UNFILLED; + if (ctx->Driver.PolygonMode) ctx->Driver.PolygonMode(ctx, face, mode); } diff --git a/reactos/dll/3rdparty/mesa32/src/main/state.c b/reactos/dll/3rdparty/mesa32/src/main/state.c index 96ee5127e11..99b3f48b453 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/state.c +++ b/reactos/dll/3rdparty/mesa32/src/main/state.c @@ -812,6 +812,9 @@ _mesa_init_exec_table(struct _glapi_table *exec) SET_ProgramEnvParameters4fvEXT(exec, _mesa_ProgramEnvParameters4fvEXT); SET_ProgramLocalParameters4fvEXT(exec, _mesa_ProgramLocalParameters4fvEXT); #endif + + /* GL_ATI_separate_stencil */ + SET_StencilFuncSeparateATI(exec, _mesa_StencilFuncSeparateATI); } @@ -821,6 +824,16 @@ _mesa_init_exec_table(struct _glapi_table *exec) /*@{*/ +static void +update_separate_specular( GLcontext *ctx ) +{ + if (NEED_SECONDARY_COLOR(ctx)) + ctx->_TriangleCaps |= DD_SEPARATE_SPECULAR; + else + ctx->_TriangleCaps &= ~DD_SEPARATE_SPECULAR; +} + + /** * Update state dependent on vertex arrays. */ @@ -1045,6 +1058,26 @@ update_color(GLcontext *ctx) } +/* + * Check polygon state and set DD_TRI_CULL_FRONT_BACK and/or DD_TRI_OFFSET + * in ctx->_TriangleCaps if needed. + */ +static void +update_polygon( GLcontext *ctx ) +{ + ctx->_TriangleCaps &= ~(DD_TRI_CULL_FRONT_BACK | DD_TRI_OFFSET); + + if (ctx->Polygon.CullFlag && ctx->Polygon.CullFaceMode == GL_FRONT_AND_BACK) + ctx->_TriangleCaps |= DD_TRI_CULL_FRONT_BACK; + + /* Any Polygon offsets enabled? */ + if (ctx->Polygon.OffsetPoint || + ctx->Polygon.OffsetLine || + ctx->Polygon.OffsetFill) { + ctx->_TriangleCaps |= DD_TRI_OFFSET; + } +} + /** * Update the ctx->_TriangleCaps bitfield. @@ -1052,6 +1085,7 @@ update_color(GLcontext *ctx) * This function must be called after other update_*() functions since * there are dependencies on some other derived values. */ +#if 0 static void update_tricaps(GLcontext *ctx, GLbitfield new_state) { @@ -1117,6 +1151,7 @@ update_tricaps(GLcontext *ctx, GLbitfield new_state) if (ctx->Stencil._TestTwoSide) ctx->_TriangleCaps |= DD_TRI_TWOSTENCIL; } +#endif /** @@ -1154,6 +1189,9 @@ _mesa_update_state_locked( GLcontext *ctx ) if (new_state & (_NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT)) _mesa_update_draw_buffer_bounds( ctx ); + if (new_state & _NEW_POLYGON) + update_polygon( ctx ); + if (new_state & _NEW_LIGHT) _mesa_update_lighting( ctx ); @@ -1163,6 +1201,9 @@ _mesa_update_state_locked( GLcontext *ctx ) if (new_state & _IMAGE_NEW_TRANSFER_STATE) _mesa_update_pixel( ctx, new_state ); + if (new_state & _DD_NEW_SEPARATE_SPECULAR) + update_separate_specular( ctx ); + if (new_state & (_NEW_ARRAY | _NEW_PROGRAM)) update_arrays( ctx ); @@ -1172,9 +1213,11 @@ _mesa_update_state_locked( GLcontext *ctx ) if (new_state & _NEW_COLOR) update_color( ctx ); +#if 0 if (new_state & (_NEW_POINT | _NEW_LINE | _NEW_POLYGON | _NEW_LIGHT | _NEW_STENCIL | _DD_NEW_SEPARATE_SPECULAR)) update_tricaps( ctx, new_state ); +#endif if (ctx->FragmentProgram._MaintainTexEnvProgram) { if (new_state & (_NEW_TEXTURE | _DD_NEW_SEPARATE_SPECULAR | _NEW_FOG)) diff --git a/reactos/dll/3rdparty/mesa32/src/main/stencil.c b/reactos/dll/3rdparty/mesa32/src/main/stencil.c index e61eb0030c0..c1906197de1 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/stencil.c +++ b/reactos/dll/3rdparty/mesa32/src/main/stencil.c @@ -1,8 +1,8 @@ /* * Mesa 3-D graphics library - * Version: 6.5.2 + * Version: 7.1 * - * Copyright (C) 1999-2006 Brian Paul All Rights Reserved. + * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -53,6 +53,48 @@ #include "mtypes.h" +static GLboolean +validate_stencil_op(GLcontext *ctx, GLenum op) +{ + switch (op) { + case GL_KEEP: + case GL_ZERO: + case GL_REPLACE: + case GL_INCR: + case GL_DECR: + case GL_INVERT: + return GL_TRUE; + case GL_INCR_WRAP_EXT: + case GL_DECR_WRAP_EXT: + if (ctx->Extensions.EXT_stencil_wrap) { + return GL_TRUE; + } + /* FALL-THROUGH */ + default: + return GL_FALSE; + } +} + + +static GLboolean +validate_stencil_func(GLcontext *ctx, GLenum func) +{ + switch (func) { + case GL_NEVER: + case GL_LESS: + case GL_LEQUAL: + case GL_GREATER: + case GL_GEQUAL: + case GL_EQUAL: + case GL_NOTEQUAL: + case GL_ALWAYS: + return GL_TRUE; + default: + return GL_FALSE; + } +} + + /** * Set the clear value for the stencil buffer. * @@ -82,6 +124,62 @@ _mesa_ClearStencil( GLint s ) } +/** + * Set the function and reference value for stencil testing. + * + * \param frontfunc front test function. + * \param backfunc back test function. + * \param ref front and back reference value. + * \param mask front and back bitmask. + * + * \sa glStencilFunc(). + * + * Verifies the parameters and updates the respective values in + * __GLcontextRec::Stencil. On change flushes the vertices and notifies the + * driver via the dd_function_table::StencilFunc callback. + */ +void GLAPIENTRY +_mesa_StencilFuncSeparateATI( GLenum frontfunc, GLenum backfunc, GLint ref, GLuint mask ) +{ + GET_CURRENT_CONTEXT(ctx); + const GLint stencilMax = (1 << ctx->DrawBuffer->Visual.stencilBits) - 1; + ASSERT_OUTSIDE_BEGIN_END(ctx); + + if (!validate_stencil_func(ctx, frontfunc)) { + _mesa_error(ctx, GL_INVALID_ENUM, + "glStencilFuncSeparateATI(frontfunc)"); + return; + } + if (!validate_stencil_func(ctx, backfunc)) { + _mesa_error(ctx, GL_INVALID_ENUM, + "glStencilFuncSeparateATI(backfunc)"); + return; + } + + ref = CLAMP( ref, 0, stencilMax ); + + /* set both front and back state */ + if (ctx->Stencil.Function[0] == frontfunc && + ctx->Stencil.Function[1] == backfunc && + ctx->Stencil.ValueMask[0] == mask && + ctx->Stencil.ValueMask[1] == mask && + ctx->Stencil.Ref[0] == ref && + ctx->Stencil.Ref[1] == ref) + return; + FLUSH_VERTICES(ctx, _NEW_STENCIL); + ctx->Stencil.Function[0] = frontfunc; + ctx->Stencil.Function[1] = backfunc; + ctx->Stencil.Ref[0] = ctx->Stencil.Ref[1] = ref; + ctx->Stencil.ValueMask[0] = ctx->Stencil.ValueMask[1] = mask; + if (ctx->Driver.StencilFuncSeparate) { + ctx->Driver.StencilFuncSeparate(ctx, GL_FRONT, + frontfunc, ref, mask); + ctx->Driver.StencilFuncSeparate(ctx, GL_BACK, + backfunc, ref, mask); + } +} + + /** * Set the function and reference value for stencil testing. * @@ -102,19 +200,9 @@ _mesa_StencilFunc( GLenum func, GLint ref, GLuint mask ) const GLint stencilMax = (1 << ctx->DrawBuffer->Visual.stencilBits) - 1; ASSERT_OUTSIDE_BEGIN_END(ctx); - switch (func) { - case GL_NEVER: - case GL_LESS: - case GL_LEQUAL: - case GL_GREATER: - case GL_GEQUAL: - case GL_EQUAL: - case GL_NOTEQUAL: - case GL_ALWAYS: - break; - default: - _mesa_error( ctx, GL_INVALID_ENUM, "glStencilFunc (0x%04x)", func ); - return; + if (!validate_stencil_func(ctx, func)) { + _mesa_error(ctx, GL_INVALID_ENUM, "glStencilFunc(func)"); + return; } ref = CLAMP( ref, 0, stencilMax ); @@ -218,59 +306,17 @@ _mesa_StencilOp(GLenum fail, GLenum zfail, GLenum zpass) GET_CURRENT_CONTEXT(ctx); ASSERT_OUTSIDE_BEGIN_END(ctx); - switch (fail) { - case GL_KEEP: - case GL_ZERO: - case GL_REPLACE: - case GL_INCR: - case GL_DECR: - case GL_INVERT: - break; - case GL_INCR_WRAP_EXT: - case GL_DECR_WRAP_EXT: - if (ctx->Extensions.EXT_stencil_wrap) { - break; - } - /* FALL-THROUGH */ - default: - _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOp"); - return; + if (!validate_stencil_op(ctx, fail)) { + _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOp(sfail)"); + return; } - switch (zfail) { - case GL_KEEP: - case GL_ZERO: - case GL_REPLACE: - case GL_INCR: - case GL_DECR: - case GL_INVERT: - break; - case GL_INCR_WRAP_EXT: - case GL_DECR_WRAP_EXT: - if (ctx->Extensions.EXT_stencil_wrap) { - break; - } - /* FALL-THROUGH */ - default: - _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOp"); - return; + if (!validate_stencil_op(ctx, zfail)) { + _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOp(zfail)"); + return; } - switch (zpass) { - case GL_KEEP: - case GL_ZERO: - case GL_REPLACE: - case GL_INCR: - case GL_DECR: - case GL_INVERT: - break; - case GL_INCR_WRAP_EXT: - case GL_DECR_WRAP_EXT: - if (ctx->Extensions.EXT_stencil_wrap) { - break; - } - /* FALL-THROUGH */ - default: - _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOp"); - return; + if (!validate_stencil_op(ctx, zpass)) { + _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOp(zpass)"); + return; } if (ctx->Extensions.ATI_separate_stencil) { @@ -343,85 +389,55 @@ _mesa_ActiveStencilFaceEXT(GLenum face) * instead. */ void GLAPIENTRY -_mesa_StencilOpSeparate(GLenum face, GLenum fail, GLenum zfail, GLenum zpass) +_mesa_StencilOpSeparate(GLenum face, GLenum sfail, GLenum zfail, GLenum zpass) { + GLboolean set = GL_FALSE; GET_CURRENT_CONTEXT(ctx); ASSERT_OUTSIDE_BEGIN_END(ctx); + if (!validate_stencil_op(ctx, sfail)) { + _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOpSeparate(sfail)"); + return; + } + if (!validate_stencil_op(ctx, zfail)) { + _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOpSeparate(zfail)"); + return; + } + if (!validate_stencil_op(ctx, zpass)) { + _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOpSeparate(zpass)"); + return; + } if (face != GL_FRONT && face != GL_BACK && face != GL_FRONT_AND_BACK) { _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOpSeparate(face)"); return; } - switch (fail) { - case GL_KEEP: - case GL_ZERO: - case GL_REPLACE: - case GL_INCR: - case GL_DECR: - case GL_INVERT: - break; - case GL_INCR_WRAP_EXT: - case GL_DECR_WRAP_EXT: - if (ctx->Extensions.EXT_stencil_wrap) { - break; - } - /* FALL-THROUGH */ - default: - _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOpSeparate(fail)"); - return; - } - switch (zfail) { - case GL_KEEP: - case GL_ZERO: - case GL_REPLACE: - case GL_INCR: - case GL_DECR: - case GL_INVERT: - break; - case GL_INCR_WRAP_EXT: - case GL_DECR_WRAP_EXT: - if (ctx->Extensions.EXT_stencil_wrap) { - break; - } - /* FALL-THROUGH */ - default: - _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOpSeparate(zfail)"); - return; - } - switch (zpass) { - case GL_KEEP: - case GL_ZERO: - case GL_REPLACE: - case GL_INCR: - case GL_DECR: - case GL_INVERT: - break; - case GL_INCR_WRAP_EXT: - case GL_DECR_WRAP_EXT: - if (ctx->Extensions.EXT_stencil_wrap) { - break; - } - /* FALL-THROUGH */ - default: - _mesa_error(ctx, GL_INVALID_ENUM, "glStencilOpSeparate(zpass)"); - return; - } - - FLUSH_VERTICES(ctx, _NEW_STENCIL); - if (face != GL_BACK) { - ctx->Stencil.FailFunc[0] = fail; - ctx->Stencil.ZFailFunc[0] = zfail; - ctx->Stencil.ZPassFunc[0] = zpass; + /* set front */ + if (ctx->Stencil.ZFailFunc[0] != zfail || + ctx->Stencil.ZPassFunc[0] != zpass || + ctx->Stencil.FailFunc[0] != sfail){ + FLUSH_VERTICES(ctx, _NEW_STENCIL); + ctx->Stencil.ZFailFunc[0] = zfail; + ctx->Stencil.ZPassFunc[0] = zpass; + ctx->Stencil.FailFunc[0] = sfail; + set = GL_TRUE; + } } if (face != GL_FRONT) { - ctx->Stencil.FailFunc[1] = fail; - ctx->Stencil.ZFailFunc[1] = zfail; - ctx->Stencil.ZPassFunc[1] = zpass; + /* set back */ + if (ctx->Stencil.ZFailFunc[1] != zfail || + ctx->Stencil.ZPassFunc[1] != zpass || + ctx->Stencil.FailFunc[1] != sfail) { + FLUSH_VERTICES(ctx, _NEW_STENCIL); + ctx->Stencil.ZFailFunc[1] = zfail; + ctx->Stencil.ZPassFunc[1] = zpass; + ctx->Stencil.FailFunc[1] = sfail; + set = GL_TRUE; + } } - if (ctx->Driver.StencilOpSeparate) { - ctx->Driver.StencilOpSeparate(ctx, face, fail, zfail, zpass); + if (set && ctx->Driver.StencilOpSeparate) { + ctx->Driver.StencilOpSeparate(ctx, face, sfail, zfail, zpass); } } @@ -438,20 +454,9 @@ _mesa_StencilFuncSeparate(GLenum face, GLenum func, GLint ref, GLuint mask) _mesa_error(ctx, GL_INVALID_ENUM, "glStencilFuncSeparate(face)"); return; } - - switch (func) { - case GL_NEVER: - case GL_LESS: - case GL_LEQUAL: - case GL_GREATER: - case GL_GEQUAL: - case GL_EQUAL: - case GL_NOTEQUAL: - case GL_ALWAYS: - break; - default: - _mesa_error(ctx, GL_INVALID_ENUM, "glStencilFuncSeparate(func)"); - return; + if (!validate_stencil_func(ctx, func)) { + _mesa_error(ctx, GL_INVALID_ENUM, "glStencilFuncSeparate(func)"); + return; } ref = CLAMP(ref, 0, stencilMax); diff --git a/reactos/dll/3rdparty/mesa32/src/main/stencil.h b/reactos/dll/3rdparty/mesa32/src/main/stencil.h index 27c6362023c..252ac932acd 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/stencil.h +++ b/reactos/dll/3rdparty/mesa32/src/main/stencil.h @@ -5,9 +5,9 @@ /* * Mesa 3-D graphics library - * Version: 6.5 + * Version: 7.1 * - * Copyright (C) 1999-2005 Brian Paul All Rights Reserved. + * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -63,6 +63,9 @@ extern void GLAPIENTRY _mesa_StencilFuncSeparate(GLenum face, GLenum func, GLint ref, GLuint mask); +extern void GLAPIENTRY +_mesa_StencilFuncSeparateATI(GLenum frontfunc, GLenum backfunc, GLint ref, GLuint mask); + extern void GLAPIENTRY _mesa_StencilMaskSeparate(GLenum face, GLuint mask); diff --git a/reactos/dll/3rdparty/mesa32/src/main/texenvprogram.c b/reactos/dll/3rdparty/mesa32/src/main/texenvprogram.c index 1a46c10ffa3..47f3adbd0d8 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/texenvprogram.c +++ b/reactos/dll/3rdparty/mesa32/src/main/texenvprogram.c @@ -35,10 +35,11 @@ #include "texenvprogram.h" /** - * According to Glean's texCombine test, no more than 21 instructions - * are needed. Allow a few extra just in case. + * This MAX is probably a bit generous, but that's OK. There can be + * up to four instructions per texture unit (TEX + 3 for combine), + * then there's fog and specular add. */ -#define MAX_INSTRUCTIONS 24 +#define MAX_INSTRUCTIONS ((MAX_TEXTURE_UNITS * 4) + 12) #define DISASSEM (MESA_VERBOSE & VERBOSE_DISASSEM) @@ -460,8 +461,8 @@ static void emit_dst( struct prog_dst_register *dst, dst->File = ureg.file; dst->Index = ureg.idx; dst->WriteMask = mask; - dst->CondMask = 0; - dst->CondSwizzle = 0; + dst->CondMask = COND_TR; /* always pass cond test */ + dst->CondSwizzle = SWIZZLE_NOOP; } static struct prog_instruction * @@ -476,7 +477,9 @@ emit_op(struct texenv_fragment_program *p, { GLuint nr = p->program->Base.NumInstructions++; struct prog_instruction *inst = &p->program->Base.Instructions[nr]; - + + assert(nr < MAX_INSTRUCTIONS); + _mesa_init_instructions(inst, 1); inst->Opcode = op; diff --git a/reactos/dll/3rdparty/mesa32/src/main/texobj.c b/reactos/dll/3rdparty/mesa32/src/main/texobj.c index 56d816e45f7..7b36154a5e5 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/texobj.c +++ b/reactos/dll/3rdparty/mesa32/src/main/texobj.c @@ -156,6 +156,11 @@ _mesa_delete_texture_object( GLcontext *ctx, struct gl_texture_object *texObj ) (void) ctx; + /* Set Target to an invalid value. With some assertions elsewhere + * we can try to detect possible use of deleted textures. + */ + texObj->Target = 0x99; + _mesa_free_colortable_data(&texObj->Palette); /* free the texture images */ @@ -188,6 +193,7 @@ void _mesa_copy_texture_object( struct gl_texture_object *dest, const struct gl_texture_object *src ) { + dest->Target = src->Target; dest->Name = src->Name; dest->Priority = src->Priority; dest->BorderColor[0] = src->BorderColor[0]; @@ -219,6 +225,92 @@ _mesa_copy_texture_object( struct gl_texture_object *dest, } +/** + * Check if the given texture object is valid by examining its Target field. + * For debugging only. + */ +static GLboolean +valid_texture_object(const struct gl_texture_object *tex) +{ + switch (tex->Target) { + case 0: + case GL_TEXTURE_1D: + case GL_TEXTURE_2D: + case GL_TEXTURE_3D: + case GL_TEXTURE_CUBE_MAP_ARB: + case GL_TEXTURE_RECTANGLE_NV: + return GL_TRUE; + case 0x99: + _mesa_problem(NULL, "invalid reference to a deleted texture object"); + return GL_FALSE; + default: + _mesa_problem(NULL, "invalid texture object Target value"); + return GL_FALSE; + } +} + + +/** + * Reference (or unreference) a texture object. + * If '*ptr', decrement *ptr's refcount (and delete if it becomes zero). + * If 'tex' is non-null, increment its refcount. + */ +void +_mesa_reference_texobj(struct gl_texture_object **ptr, + struct gl_texture_object *tex) +{ + assert(ptr); + if (*ptr == tex) { + /* no change */ + return; + } + + if (*ptr) { + /* Unreference the old texture */ + GLboolean deleteFlag = GL_FALSE; + struct gl_texture_object *oldTex = *ptr; + + assert(valid_texture_object(oldTex)); + + _glthread_LOCK_MUTEX(oldTex->Mutex); + ASSERT(oldTex->RefCount > 0); + oldTex->RefCount--; + + deleteFlag = (oldTex->RefCount == 0); + _glthread_UNLOCK_MUTEX(oldTex->Mutex); + + if (deleteFlag) { + GET_CURRENT_CONTEXT(ctx); + if (ctx) + ctx->Driver.DeleteTexture(ctx, oldTex); + else + _mesa_problem(NULL, "Unable to delete texture, no context"); + } + + *ptr = NULL; + } + assert(!*ptr); + + if (tex) { + /* reference new texture */ + assert(valid_texture_object(tex)); + _glthread_LOCK_MUTEX(tex->Mutex); + if (tex->RefCount == 0) { + /* this texture's being deleted (look just above) */ + /* Not sure this can every really happen. Warn if it does. */ + _mesa_problem(NULL, "referencing deleted texture object"); + *ptr = NULL; + } + else { + tex->RefCount++; + *ptr = tex; + } + _glthread_UNLOCK_MUTEX(tex->Mutex); + } +} + + + /** * Report why a texture object is incomplete. * @@ -620,8 +712,7 @@ unbind_texobj_from_fbo(GLcontext *ctx, struct gl_texture_object *texObj) /** * Check if the given texture object is bound to any texture image units and - * unbind it if so. - * XXX all RefCount accesses should be protected by a mutex. + * unbind it if so (revert to default textures). */ static void unbind_texobj_from_texunits(GLcontext *ctx, struct gl_texture_object *texObj) @@ -630,34 +721,20 @@ unbind_texobj_from_texunits(GLcontext *ctx, struct gl_texture_object *texObj) for (u = 0; u < MAX_TEXTURE_IMAGE_UNITS; u++) { struct gl_texture_unit *unit = &ctx->Texture.Unit[u]; - struct gl_texture_object **curr = NULL; - if (texObj == unit->Current1D) { - curr = &unit->Current1D; - unit->Current1D = ctx->Shared->Default1D; + _mesa_reference_texobj(&unit->Current1D, ctx->Shared->Default1D); } else if (texObj == unit->Current2D) { - curr = &unit->Current2D; - unit->Current2D = ctx->Shared->Default2D; + _mesa_reference_texobj(&unit->Current2D, ctx->Shared->Default2D); } else if (texObj == unit->Current3D) { - curr = &unit->Current3D; - unit->Current3D = ctx->Shared->Default3D; + _mesa_reference_texobj(&unit->Current3D, ctx->Shared->Default3D); } else if (texObj == unit->CurrentCubeMap) { - curr = &unit->CurrentCubeMap; - unit->CurrentCubeMap = ctx->Shared->DefaultCubeMap; + _mesa_reference_texobj(&unit->CurrentCubeMap, ctx->Shared->DefaultCubeMap); } else if (texObj == unit->CurrentRect) { - curr = &unit->CurrentRect; - unit->CurrentRect = ctx->Shared->DefaultRect; - } - - if (curr) { - (*curr)->RefCount++; - texObj->RefCount--; - if (texObj == unit->_Current) - unit->_Current = *curr; + _mesa_reference_texobj(&unit->CurrentRect, ctx->Shared->DefaultRect); } } } @@ -693,8 +770,6 @@ _mesa_DeleteTextures( GLsizei n, const GLuint *textures) = _mesa_lookup_texture(ctx, textures[i]); if (delObj) { - GLboolean deleted; - _mesa_lock_texture(ctx, delObj); /* Check if texture is bound to any framebuffer objects. @@ -704,10 +779,12 @@ _mesa_DeleteTextures( GLsizei n, const GLuint *textures) unbind_texobj_from_fbo(ctx, delObj); /* Check if this texture is currently bound to any texture units. - * If so, unbind it and decrement the reference count. + * If so, unbind it. */ unbind_texobj_from_texunits(ctx, delObj); + _mesa_unlock_texture(ctx, delObj); + ctx->NewState |= _NEW_TEXTURE; /* The texture _name_ is now free for re-use. @@ -717,23 +794,10 @@ _mesa_DeleteTextures( GLsizei n, const GLuint *textures) _mesa_HashRemove(ctx->Shared->TexObjects, delObj->Name); _glthread_UNLOCK_MUTEX(ctx->Shared->Mutex); - /* The actual texture object will not be freed until it's no - * longer bound in any context. - * XXX all RefCount accesses should be protected by a mutex. + /* Unreference the texobj. If refcount hits zero, the texture + * will be deleted. */ - delObj->RefCount--; - deleted = (delObj->RefCount == 0); - _mesa_unlock_texture(ctx, delObj); - - /* We know that refcount went to zero above, so this is - * the only pointer left to delObj, so we don't have to - * worry about locking any more: - */ - if (deleted) { - ASSERT(delObj->Name != 0); /* Never delete default tex objs */ - ASSERT(ctx->Driver.DeleteTexture); - (*ctx->Driver.DeleteTexture)(ctx, delObj); - } + _mesa_reference_texobj(&delObj, NULL); } } } @@ -761,7 +825,6 @@ _mesa_BindTexture( GLenum target, GLuint texName ) GET_CURRENT_CONTEXT(ctx); const GLuint unit = ctx->Texture.CurrentUnit; struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit]; - struct gl_texture_object *oldTexObj; struct gl_texture_object *newTexObj = NULL; ASSERT_OUTSIDE_BEGIN_END(ctx); @@ -769,48 +832,6 @@ _mesa_BindTexture( GLenum target, GLuint texName ) _mesa_debug(ctx, "glBindTexture %s %d\n", _mesa_lookup_enum_by_nr(target), (GLint) texName); - /* - * Get pointer to currently bound texture object (oldTexObj) - */ - switch (target) { - case GL_TEXTURE_1D: - oldTexObj = texUnit->Current1D; - break; - case GL_TEXTURE_2D: - oldTexObj = texUnit->Current2D; - break; - case GL_TEXTURE_3D: - oldTexObj = texUnit->Current3D; - break; - case GL_TEXTURE_CUBE_MAP_ARB: - if (!ctx->Extensions.ARB_texture_cube_map) { - _mesa_error( ctx, GL_INVALID_ENUM, "glBindTexture(target)" ); - return; - } - oldTexObj = texUnit->CurrentCubeMap; - break; - case GL_TEXTURE_RECTANGLE_NV: - if (!ctx->Extensions.NV_texture_rectangle) { - _mesa_error( ctx, GL_INVALID_ENUM, "glBindTexture(target)" ); - return; - } - oldTexObj = texUnit->CurrentRect; - break; - default: - _mesa_error( ctx, GL_INVALID_ENUM, "glBindTexture(target)" ); - return; - } - - if (oldTexObj->Name == texName) { - /* XXX this might be wrong. If the texobj is in use by another - * context and a texobj parameter was changed, this might be our - * only chance to update this context's hardware state. - * Note that some applications re-bind the same texture a lot so we - * want to handle that case quickly. - */ - return; /* rebinding the same texture- no change */ - } - /* * Get pointer to new texture object (newTexObj) */ @@ -879,28 +900,30 @@ _mesa_BindTexture( GLenum target, GLuint texName ) newTexObj->Target = target; } - /* XXX all RefCount accesses should be protected by a mutex. */ - newTexObj->RefCount++; + assert(valid_texture_object(newTexObj)); - /* do the actual binding, but first flush outstanding vertices: - */ + /* flush before changing binding */ FLUSH_VERTICES(ctx, _NEW_TEXTURE); + /* Do the actual binding. The refcount on the previously bound + * texture object will be decremented. It'll be deleted if the + * count hits zero. + */ switch (target) { case GL_TEXTURE_1D: - texUnit->Current1D = newTexObj; + _mesa_reference_texobj(&texUnit->Current1D, newTexObj); break; case GL_TEXTURE_2D: - texUnit->Current2D = newTexObj; + _mesa_reference_texobj(&texUnit->Current2D, newTexObj); break; case GL_TEXTURE_3D: - texUnit->Current3D = newTexObj; + _mesa_reference_texobj(&texUnit->Current3D, newTexObj); break; case GL_TEXTURE_CUBE_MAP_ARB: - texUnit->CurrentCubeMap = newTexObj; + _mesa_reference_texobj(&texUnit->CurrentCubeMap, newTexObj); break; case GL_TEXTURE_RECTANGLE_NV: - texUnit->CurrentRect = newTexObj; + _mesa_reference_texobj(&texUnit->CurrentRect, newTexObj); break; default: _mesa_problem(ctx, "bad target in BindTexture"); @@ -910,18 +933,6 @@ _mesa_BindTexture( GLenum target, GLuint texName ) /* Pass BindTexture call to device driver */ if (ctx->Driver.BindTexture) (*ctx->Driver.BindTexture)( ctx, target, newTexObj ); - - /* Decrement the reference count on the old texture and check if it's - * time to delete it. - */ - /* XXX all RefCount accesses should be protected by a mutex. */ - oldTexObj->RefCount--; - ASSERT(oldTexObj->RefCount >= 0); - if (oldTexObj->RefCount == 0) { - ASSERT(oldTexObj->Name != 0); - ASSERT(ctx->Driver.DeleteTexture); - (*ctx->Driver.DeleteTexture)( ctx, oldTexObj ); - } } diff --git a/reactos/dll/3rdparty/mesa32/src/main/texobj.h b/reactos/dll/3rdparty/mesa32/src/main/texobj.h index ec7cf8cd86e..9577e5e4dba 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/texobj.h +++ b/reactos/dll/3rdparty/mesa32/src/main/texobj.h @@ -57,6 +57,10 @@ extern void _mesa_copy_texture_object( struct gl_texture_object *dest, const struct gl_texture_object *src ); +extern void +_mesa_reference_texobj(struct gl_texture_object **ptr, + struct gl_texture_object *tex); + extern void _mesa_test_texobj_completeness( const GLcontext *ctx, struct gl_texture_object *obj ); diff --git a/reactos/dll/3rdparty/mesa32/src/main/texstate.c b/reactos/dll/3rdparty/mesa32/src/main/texstate.c index 1b45eae42c3..a5966e7ecda 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/texstate.c +++ b/reactos/dll/3rdparty/mesa32/src/main/texstate.c @@ -63,31 +63,6 @@ static const struct gl_tex_env_combine_state default_combine_state = { }; -/** - * Copy a texture binding. Helper used by _mesa_copy_texture_state(). - */ -static void -copy_texture_binding(const GLcontext *ctx, - struct gl_texture_object **dst, - struct gl_texture_object *src) -{ - /* only copy if names differ (per OpenGL SI) */ - if ((*dst)->Name != src->Name) { - /* unbind/delete dest binding which we're changing */ - (*dst)->RefCount--; - if ((*dst)->RefCount == 0) { - /* time to delete this texture object */ - ASSERT((*dst)->Name != 0); - ASSERT(ctx->Driver.DeleteTexture); - /* XXX cast-away const, unfortunately */ - (*ctx->Driver.DeleteTexture)((GLcontext *) ctx, *dst); - } - /* make new binding, incrementing ref count */ - *dst = src; - src->RefCount++; - } -} - /** * Used by glXCopyContext to copy texture state from one context to another. @@ -144,16 +119,16 @@ _mesa_copy_texture_state( const GLcontext *src, GLcontext *dst ) /* copy texture object bindings, not contents of texture objects */ _mesa_lock_context_textures(dst); - copy_texture_binding(src, &dst->Texture.Unit[i].Current1D, - src->Texture.Unit[i].Current1D); - copy_texture_binding(src, &dst->Texture.Unit[i].Current2D, - src->Texture.Unit[i].Current2D); - copy_texture_binding(src, &dst->Texture.Unit[i].Current3D, - src->Texture.Unit[i].Current3D); - copy_texture_binding(src, &dst->Texture.Unit[i].CurrentCubeMap, - src->Texture.Unit[i].CurrentCubeMap); - copy_texture_binding(src, &dst->Texture.Unit[i].CurrentRect, - src->Texture.Unit[i].CurrentRect); + _mesa_reference_texobj(&dst->Texture.Unit[i].Current1D, + src->Texture.Unit[i].Current1D); + _mesa_reference_texobj(&dst->Texture.Unit[i].Current2D, + src->Texture.Unit[i].Current2D); + _mesa_reference_texobj(&dst->Texture.Unit[i].Current3D, + src->Texture.Unit[i].Current3D); + _mesa_reference_texobj(&dst->Texture.Unit[i].CurrentCubeMap, + src->Texture.Unit[i].CurrentCubeMap); + _mesa_reference_texobj(&dst->Texture.Unit[i].CurrentRect, + src->Texture.Unit[i].CurrentRect); _mesa_unlock_context_textures(dst); } @@ -3032,6 +3007,8 @@ alloc_proxy_textures( GLcontext *ctx ) if (!ctx->Texture.ProxyRect) goto cleanup; + assert(ctx->Texture.Proxy1D->RefCount == 1); + return GL_TRUE; cleanup: @@ -3087,11 +3064,12 @@ init_texture_unit( GLcontext *ctx, GLuint unit ) ASSIGN_4V( texUnit->EyePlaneR, 0.0, 0.0, 0.0, 0.0 ); ASSIGN_4V( texUnit->EyePlaneQ, 0.0, 0.0, 0.0, 0.0 ); - texUnit->Current1D = ctx->Shared->Default1D; - texUnit->Current2D = ctx->Shared->Default2D; - texUnit->Current3D = ctx->Shared->Default3D; - texUnit->CurrentCubeMap = ctx->Shared->DefaultCubeMap; - texUnit->CurrentRect = ctx->Shared->DefaultRect; + /* initialize current texture object ptrs to the shared default objects */ + _mesa_reference_texobj(&texUnit->Current1D, ctx->Shared->Default1D); + _mesa_reference_texobj(&texUnit->Current2D, ctx->Shared->Default2D); + _mesa_reference_texobj(&texUnit->Current3D, ctx->Shared->Default3D); + _mesa_reference_texobj(&texUnit->CurrentCubeMap, ctx->Shared->DefaultCubeMap); + _mesa_reference_texobj(&texUnit->CurrentRect, ctx->Shared->DefaultRect); } @@ -3106,21 +3084,20 @@ _mesa_init_texture(GLcontext *ctx) assert(MAX_TEXTURE_LEVELS >= MAX_3D_TEXTURE_LEVELS); assert(MAX_TEXTURE_LEVELS >= MAX_CUBE_TEXTURE_LEVELS); - /* Effectively bind the default textures to all texture units */ - ctx->Shared->Default1D->RefCount += MAX_TEXTURE_UNITS; - ctx->Shared->Default2D->RefCount += MAX_TEXTURE_UNITS; - ctx->Shared->Default3D->RefCount += MAX_TEXTURE_UNITS; - ctx->Shared->DefaultCubeMap->RefCount += MAX_TEXTURE_UNITS; - ctx->Shared->DefaultRect->RefCount += MAX_TEXTURE_UNITS; - /* Texture group */ ctx->Texture.CurrentUnit = 0; /* multitexture */ ctx->Texture._EnabledUnits = 0; - for (i=0; iTexture.SharedPalette = GL_FALSE; _mesa_init_colortable(&ctx->Texture.Palette); + for (i = 0; i < MAX_TEXTURE_UNITS; i++) + init_texture_unit( ctx, i ); + + /* After we're done initializing the context's texture state the default + * texture objects' refcounts should be at least MAX_TEXTURE_UNITS + 1. + */ + assert(ctx->Shared->Default1D->RefCount >= MAX_TEXTURE_UNITS + 1); + _mesa_TexEnvProgramCacheInit( ctx ); /* Allocate proxy textures */ @@ -3132,12 +3109,22 @@ _mesa_init_texture(GLcontext *ctx) /** - * Free dynamically-allocted texture data attached to the given context. + * Free dynamically-allocated texture data attached to the given context. */ void _mesa_free_texture_data(GLcontext *ctx) { - GLuint i; + GLuint u; + + /* unreference current textures */ + for (u = 0; u < MAX_TEXTURE_IMAGE_UNITS; u++) { + struct gl_texture_unit *unit = ctx->Texture.Unit + u; + _mesa_reference_texobj(&unit->Current1D, NULL); + _mesa_reference_texobj(&unit->Current2D, NULL); + _mesa_reference_texobj(&unit->Current3D, NULL); + _mesa_reference_texobj(&unit->CurrentCubeMap, NULL); + _mesa_reference_texobj(&unit->CurrentRect, NULL); + } /* Free proxy texture objects */ (ctx->Driver.DeleteTexture)(ctx, ctx->Texture.Proxy1D ); @@ -3146,8 +3133,8 @@ _mesa_free_texture_data(GLcontext *ctx) (ctx->Driver.DeleteTexture)(ctx, ctx->Texture.ProxyCubeMap ); (ctx->Driver.DeleteTexture)(ctx, ctx->Texture.ProxyRect ); - for (i = 0; i < MAX_TEXTURE_IMAGE_UNITS; i++) - _mesa_free_colortable_data( &ctx->Texture.Unit[i].ColorTable ); + for (u = 0; u < MAX_TEXTURE_IMAGE_UNITS; u++) + _mesa_free_colortable_data( &ctx->Texture.Unit[u].ColorTable ); _mesa_TexEnvProgramCacheDestroy( ctx ); } diff --git a/reactos/dll/3rdparty/mesa32/src/main/version.h b/reactos/dll/3rdparty/mesa32/src/main/version.h index 2c84579918d..2d3c68bca99 100644 --- a/reactos/dll/3rdparty/mesa32/src/main/version.h +++ b/reactos/dll/3rdparty/mesa32/src/main/version.h @@ -1,6 +1,6 @@ /* * Mesa 3-D graphics library - * Version: 7.0.1 + * Version: 7.0.2 * * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. * @@ -30,8 +30,8 @@ /* Mesa version */ #define MESA_MAJOR 7 #define MESA_MINOR 0 -#define MESA_PATCH 1 -#define MESA_VERSION_STRING "7.0.1" +#define MESA_PATCH 2 +#define MESA_VERSION_STRING "7.0.2" /* To make version comparison easy */ #define MESA_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) diff --git a/reactos/dll/3rdparty/mesa32/src/shader/arbprogparse.c b/reactos/dll/3rdparty/mesa32/src/shader/arbprogparse.c index 5027264f031..6a87a1779e7 100644 --- a/reactos/dll/3rdparty/mesa32/src/shader/arbprogparse.c +++ b/reactos/dll/3rdparty/mesa32/src/shader/arbprogparse.c @@ -624,6 +624,41 @@ program_error(GLcontext *ctx, GLint position, const char *descrip) } +/** + * As above, but with an extra string parameter for more info. + */ +static void +program_error2(GLcontext *ctx, GLint position, const char *descrip, + const char *var) +{ + if (descrip) { + const char *prefix = "glProgramString(", *suffix = ")"; + char *str = (char *) _mesa_malloc(_mesa_strlen(descrip) + + _mesa_strlen(": ") + + _mesa_strlen(var) + + _mesa_strlen(prefix) + + _mesa_strlen(suffix) + 1); + if (str) { + _mesa_sprintf(str, "%s%s: %s%s", prefix, descrip, var, suffix); + _mesa_error(ctx, GL_INVALID_OPERATION, str); + _mesa_free(str); + } + } + { + char *str = (char *) _mesa_malloc(_mesa_strlen(descrip) + + _mesa_strlen(": ") + + _mesa_strlen(var) + 1); + if (str) { + _mesa_sprintf(str, "%s: %s", descrip, var); + } + _mesa_set_program_error(ctx, position, str); + if (str) { + _mesa_free(str); + } + } +} + + /** * constructs an integer from 4 GLubytes in LE format @@ -1217,10 +1252,10 @@ parse_state_single_item (GLcontext * ctx, const GLubyte ** inst, state_tokens[1] = coord; /* EYE or OBJECT */ - type = *(*inst++); + type = *(*inst)++; /* 0 - s, 1 - t, 2 - r, 3 - q */ - coord = *(*inst++); + coord = *(*inst)++; if (type == TEX_GEN_EYE) { switch (coord) { @@ -1236,6 +1271,9 @@ parse_state_single_item (GLcontext * ctx, const GLubyte ** inst, case COMPONENT_W: state_tokens[2] = STATE_TEXGEN_EYE_Q; break; + default: + _mesa_problem(ctx, "bad texgen component in " + "parse_state_single_item()"); } } else { @@ -1252,6 +1290,9 @@ parse_state_single_item (GLcontext * ctx, const GLubyte ** inst, case COMPONENT_W: state_tokens[2] = STATE_TEXGEN_OBJECT_Q; break; + default: + _mesa_problem(ctx, "bad texgen component in " + "parse_state_single_item()"); } } } @@ -1274,7 +1315,7 @@ parse_state_single_item (GLcontext * ctx, const GLubyte ** inst, break; case STATE_POINT: - switch (*(*inst++)) { + switch (*(*inst)++) { case POINT_SIZE: state_tokens[0] = STATE_POINT_SIZE; break; @@ -1678,18 +1719,14 @@ parse_attrib (GLcontext * ctx, const GLubyte ** inst, struct var_cache **vc_head struct arb_program *Program) { GLuint found; - char *error_msg; struct var_cache *attrib_var; attrib_var = parse_string (inst, vc_head, Program, &found); Program->Position = parse_position (inst); if (found) { - error_msg = (char *) - _mesa_malloc (_mesa_strlen ((char *) attrib_var->name) + 40); - _mesa_sprintf (error_msg, "Duplicate Varible Declaration: %s", - attrib_var->name); - program_error(ctx, Program->Position, error_msg); - _mesa_free (error_msg); + program_error2(ctx, Program->Position, + "Duplicate variable declaration", + (char *) attrib_var->name); return 1; } @@ -1867,12 +1904,9 @@ parse_param (GLcontext * ctx, const GLubyte ** inst, struct var_cache **vc_head, Program->Position = parse_position (inst); if (found) { - char *error_msg = (char *) - _mesa_malloc (_mesa_strlen ((char *) param_var->name) + 40); - _mesa_sprintf (error_msg, "Duplicate Varible Declaration: %s", - param_var->name); - program_error (ctx, Program->Position, error_msg); - _mesa_free (error_msg); + program_error2(ctx, Program->Position, + "Duplicate variable declaration", + (char *) param_var->name); return 1; } @@ -1967,12 +2001,9 @@ parse_temp (GLcontext * ctx, const GLubyte ** inst, struct var_cache **vc_head, temp_var = parse_string (inst, vc_head, Program, &found); Program->Position = parse_position (inst); if (found) { - char *error_msg = (char *) - _mesa_malloc (_mesa_strlen ((char *) temp_var->name) + 40); - _mesa_sprintf (error_msg, "Duplicate Varible Declaration: %s", - temp_var->name); - program_error(ctx, Program->Position, error_msg); - _mesa_free (error_msg); + program_error2(ctx, Program->Position, + "Duplicate variable declaration", + (char *) temp_var->name); return 1; } @@ -2013,12 +2044,9 @@ parse_output (GLcontext * ctx, const GLubyte ** inst, struct var_cache **vc_head output_var = parse_string (inst, vc_head, Program, &found); Program->Position = parse_position (inst); if (found) { - char *error_msg = (char *) - _mesa_malloc (_mesa_strlen ((char *) output_var->name) + 40); - _mesa_sprintf (error_msg, "Duplicate Varible Declaration: %s", - output_var->name); - program_error (ctx, Program->Position, error_msg); - _mesa_free (error_msg); + program_error2(ctx, Program->Position, + "Duplicate variable declaration", + (char *) output_var->name); return 1; } @@ -2044,12 +2072,9 @@ parse_alias (GLcontext * ctx, const GLubyte ** inst, struct var_cache **vc_head, Program->Position = parse_position (inst); if (found) { - char *error_msg = (char *) - _mesa_malloc (_mesa_strlen ((char *) temp_var->name) + 40); - _mesa_sprintf (error_msg, "Duplicate Varible Declaration: %s", - temp_var->name); - program_error(ctx, Program->Position, error_msg); - _mesa_free (error_msg); + program_error2(ctx, Program->Position, + "Duplicate variable declaration", + (char *) temp_var->name); return 1; } @@ -2059,12 +2084,9 @@ parse_alias (GLcontext * ctx, const GLubyte ** inst, struct var_cache **vc_head, if (!found) { - char *error_msg = (char *) - _mesa_malloc (_mesa_strlen ((char *) temp_var->name) + 40); - _mesa_sprintf (error_msg, "Alias value %s is not defined", - temp_var->alias_binding->name); - program_error (ctx, Program->Position, error_msg); - _mesa_free (error_msg); + program_error2(ctx, Program->Position, + "Undefined alias value", + (char *) temp_var->alias_binding->name); return 1; } @@ -2087,12 +2109,9 @@ parse_address (GLcontext * ctx, const GLubyte ** inst, struct var_cache **vc_hea temp_var = parse_string (inst, vc_head, Program, &found); Program->Position = parse_position (inst); if (found) { - char *error_msg = (char *) - _mesa_malloc (_mesa_strlen ((char *) temp_var->name) + 40); - _mesa_sprintf (error_msg, "Duplicate Varible Declaration: %s", - temp_var->name); - program_error (ctx, Program->Position, error_msg); - _mesa_free (error_msg); + program_error2(ctx, Program->Position, + "Duplicate variable declaration", + (char *) temp_var->name); return 1; } @@ -2445,8 +2464,9 @@ parse_src_reg (GLcontext * ctx, const GLubyte ** inst, Program->Position = parse_position (inst); if (!found) { - program_error(ctx, Program->Position, - "2: Undefined variable"); /* src->name */ + program_error2(ctx, Program->Position, + "Undefined variable", + (char *) src->name); return 1; } diff --git a/reactos/dll/3rdparty/mesa32/src/shader/atifragshader.c b/reactos/dll/3rdparty/mesa32/src/shader/atifragshader.c index 4727c1a4365..854c9118741 100644 --- a/reactos/dll/3rdparty/mesa32/src/shader/atifragshader.c +++ b/reactos/dll/3rdparty/mesa32/src/shader/atifragshader.c @@ -440,7 +440,7 @@ _mesa_PassTexCoordATI(GLuint dst, GLuint coord, GLenum swizzle) _mesa_error(ctx, GL_INVALID_OPERATION, "glPassTexCoordATI(coord)"); return; } - if ((swizzle < GL_SWIZZLE_STR_ATI) && (swizzle > GL_SWIZZLE_STQ_DQ_ATI)) { + if (!(swizzle >= GL_SWIZZLE_STR_ATI) && (swizzle <= GL_SWIZZLE_STQ_DQ_ATI)) { _mesa_error(ctx, GL_INVALID_ENUM, "glPassTexCoordATI(swizzle)"); return; } @@ -513,7 +513,7 @@ _mesa_SampleMapATI(GLuint dst, GLuint interp, GLenum swizzle) _mesa_error(ctx, GL_INVALID_OPERATION, "glSampleMapATI(interp)"); return; } - if ((swizzle < GL_SWIZZLE_STR_ATI) && (swizzle > GL_SWIZZLE_STQ_DQ_ATI)) { + if (!(swizzle >= GL_SWIZZLE_STR_ATI) && (swizzle <= GL_SWIZZLE_STQ_DQ_ATI)) { _mesa_error(ctx, GL_INVALID_ENUM, "glSampleMapATI(swizzle)"); return; } diff --git a/reactos/dll/3rdparty/mesa32/src/shader/prog_statevars.c b/reactos/dll/3rdparty/mesa32/src/shader/prog_statevars.c index 975a617ac89..d37d7fb9bf4 100644 --- a/reactos/dll/3rdparty/mesa32/src/shader/prog_statevars.c +++ b/reactos/dll/3rdparty/mesa32/src/shader/prog_statevars.c @@ -507,6 +507,8 @@ _mesa_program_state_flags(const gl_state_index state[STATE_LENGTH]) switch (state[1]) { case STATE_TEXRECT_SCALE: return _NEW_TEXTURE; + case STATE_FOG_PARAMS_OPTIMIZED: + return _NEW_FOG; default: /* unknown state indexes are silently ignored and * no flag set, since it is handled by the driver. diff --git a/reactos/dll/3rdparty/mesa32/src/shader/shader_api.c b/reactos/dll/3rdparty/mesa32/src/shader/shader_api.c index b794e30e970..06d24b4bf0f 100644 --- a/reactos/dll/3rdparty/mesa32/src/shader/shader_api.c +++ b/reactos/dll/3rdparty/mesa32/src/shader/shader_api.c @@ -378,7 +378,7 @@ _mesa_attach_shader(GLcontext *ctx, GLuint program, GLuint shader) struct gl_shader_program *shProg = _mesa_lookup_shader_program(ctx, program); struct gl_shader *sh = _mesa_lookup_shader(ctx, shader); - const GLuint n = shProg->NumShaders; + GLuint n; GLuint i; if (!shProg || !sh) { @@ -387,6 +387,8 @@ _mesa_attach_shader(GLcontext *ctx, GLuint program, GLuint shader) return; } + n = shProg->NumShaders; + for (i = 0; i < n; i++) { if (shProg->Shaders[i] == sh) { /* already attached */ @@ -548,7 +550,7 @@ _mesa_detach_shader(GLcontext *ctx, GLuint program, GLuint shader) { struct gl_shader_program *shProg = _mesa_lookup_shader_program(ctx, program); - const GLuint n = shProg->NumShaders; + GLuint n; GLuint i, j; if (!shProg) { @@ -557,6 +559,8 @@ _mesa_detach_shader(GLcontext *ctx, GLuint program, GLuint shader) return; } + n = shProg->NumShaders; + for (i = 0; i < n; i++) { if (shProg->Shaders[i]->Name == shader) { /* found it */ diff --git a/reactos/dll/3rdparty/mesa32/src/sparc/glapi_sparc.S b/reactos/dll/3rdparty/mesa32/src/sparc/glapi_sparc.S index 420391a2d00..9709b030929 100644 --- a/reactos/dll/3rdparty/mesa32/src/sparc/glapi_sparc.S +++ b/reactos/dll/3rdparty/mesa32/src/sparc/glapi_sparc.S @@ -837,6 +837,7 @@ __glapi_sparc_icache_flush: /* %o0 = insn_addr */ .globl gl_dispatch_stub_769 ; .type gl_dispatch_stub_769,#function .globl gl_dispatch_stub_770 ; .type gl_dispatch_stub_770,#function .globl gl_dispatch_stub_771 ; .type gl_dispatch_stub_771,#function + .globl gl_dispatch_stub_772 ; .type gl_dispatch_stub_772,#function .globl _mesa_sparc_glapi_begin ; .type _mesa_sparc_glapi_begin,#function _mesa_sparc_glapi_begin: @@ -1612,6 +1613,7 @@ _mesa_sparc_glapi_begin: GL_STUB(gl_dispatch_stub_769, _gloffset__dispatch_stub_769) GL_STUB(gl_dispatch_stub_770, _gloffset__dispatch_stub_770) GL_STUB(gl_dispatch_stub_771, _gloffset__dispatch_stub_771) + GL_STUB(gl_dispatch_stub_772, _gloffset__dispatch_stub_772) .globl _mesa_sparc_glapi_end ; .type _mesa_sparc_glapi_end,#function _mesa_sparc_glapi_end: diff --git a/reactos/dll/3rdparty/mesa32/src/swrast/s_copypix.c b/reactos/dll/3rdparty/mesa32/src/swrast/s_copypix.c index 012839cb88a..ac7fa21fe0c 100644 --- a/reactos/dll/3rdparty/mesa32/src/swrast/s_copypix.c +++ b/reactos/dll/3rdparty/mesa32/src/swrast/s_copypix.c @@ -1,6 +1,6 @@ /* * Mesa 3-D graphics library - * Version: 6.5.3 + * Version: 7.0.2 * * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. * @@ -71,13 +71,20 @@ regions_overlap(GLint srcx, GLint srcy, } else { /* add one pixel of slop when zooming, just to be safe */ - if ((srcx > dstx + (width * zoomX) + 1) || (srcx + width + 1 < dstx)) { + if (srcx > (dstx + ((zoomX > 0.0F) ? (width * zoomX + 1.0F) : 0.0F))) { + /* src is completely right of dest */ + return GL_FALSE; + } + else if (srcx + width + 1.0F < dstx + ((zoomX > 0.0F) ? 0.0F : (width * zoomX))) { + /* src is completely left of dest */ return GL_FALSE; } else if ((srcy < dsty) && (srcy + height < dsty + (height * zoomY))) { + /* src is completely below dest */ return GL_FALSE; } else if ((srcy > dsty) && (srcy + height > dsty + (height * zoomY))) { + /* src is completely above dest */ return GL_FALSE; } else { diff --git a/reactos/dll/3rdparty/mesa32/src/swrast/s_pointtemp.h b/reactos/dll/3rdparty/mesa32/src/swrast/s_pointtemp.h index dddc2f7f40c..94364643d4b 100644 --- a/reactos/dll/3rdparty/mesa32/src/swrast/s_pointtemp.h +++ b/reactos/dll/3rdparty/mesa32/src/swrast/s_pointtemp.h @@ -217,9 +217,9 @@ NAME ( GLcontext *ctx, const SWvertex *vert ) } else { /* even size */ - xmin = (GLint) vert->win[0] - iRadius + 1; + xmin = (GLint) vert->win[0] - iRadius; xmax = xmin + iSize - 1; - ymin = (GLint) vert->win[1] - iRadius + 1; + ymin = (GLint) vert->win[1] - iRadius; ymax = ymin + iSize - 1; } #endif /*SMOOTH*/ diff --git a/reactos/dll/3rdparty/mesa32/src/swrast/s_span.c b/reactos/dll/3rdparty/mesa32/src/swrast/s_span.c index 097d2c7b51c..5814400b0fe 100644 --- a/reactos/dll/3rdparty/mesa32/src/swrast/s_span.c +++ b/reactos/dll/3rdparty/mesa32/src/swrast/s_span.c @@ -61,8 +61,11 @@ _swrast_span_default_z( GLcontext *ctx, SWspan *span ) const GLfloat depthMax = ctx->DrawBuffer->_DepthMaxF; if (ctx->DrawBuffer->Visual.depthBits <= 16) span->z = FloatToFixed(ctx->Current.RasterPos[2] * depthMax + 0.5F); - else - span->z = (GLint) (ctx->Current.RasterPos[2] * depthMax + 0.5F); + else { + GLfloat tmpf = ctx->Current.RasterPos[2] * depthMax; + tmpf = MIN2(tmpf, depthMax); + span->z = (GLint) tmpf; + } span->zStep = 0; span->interpMask |= SPAN_Z; } diff --git a/reactos/dll/3rdparty/mesa32/src/swrast_setup/ss_tritmp.h b/reactos/dll/3rdparty/mesa32/src/swrast_setup/ss_tritmp.h index 1fdf0cb5999..59c534ee5ee 100644 --- a/reactos/dll/3rdparty/mesa32/src/swrast_setup/ss_tritmp.h +++ b/reactos/dll/3rdparty/mesa32/src/swrast_setup/ss_tritmp.h @@ -198,14 +198,16 @@ static void TAG(quadfunc)( GLcontext *ctx, GLuint v0, { if (IND & SS_UNFILLED_BIT) { struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb; - GLubyte ef1 = VB->EdgeFlag[v1]; - GLubyte ef3 = VB->EdgeFlag[v3]; - VB->EdgeFlag[v1] = 0; - TAG(triangle)( ctx, v0, v1, v3 ); - VB->EdgeFlag[v1] = ef1; - VB->EdgeFlag[v3] = 0; - TAG(triangle)( ctx, v1, v2, v3 ); - VB->EdgeFlag[v3] = ef3; + if (VB->EdgeFlag) { /* XXX this test shouldn't be needed (bug 12614) */ + GLubyte ef1 = VB->EdgeFlag[v1]; + GLubyte ef3 = VB->EdgeFlag[v3]; + VB->EdgeFlag[v1] = 0; + TAG(triangle)( ctx, v0, v1, v3 ); + VB->EdgeFlag[v1] = ef1; + VB->EdgeFlag[v3] = 0; + TAG(triangle)( ctx, v1, v2, v3 ); + VB->EdgeFlag[v3] = ef3; + } } else { TAG(triangle)( ctx, v0, v1, v3 ); TAG(triangle)( ctx, v1, v2, v3 ); diff --git a/reactos/dll/3rdparty/mesa32/src/tnl/t_draw.c b/reactos/dll/3rdparty/mesa32/src/tnl/t_draw.c index 5b2b2ae5495..ff50d91a165 100644 --- a/reactos/dll/3rdparty/mesa32/src/tnl/t_draw.c +++ b/reactos/dll/3rdparty/mesa32/src/tnl/t_draw.c @@ -1,9 +1,8 @@ - /* * Mesa 3-D graphics library - * Version: 6.5 + * Version: 7.0.2 * - * Copyright (C) 1999-2006 Brian Paul All Rights Reserved. + * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -368,7 +367,7 @@ void _tnl_draw_prims( GLcontext *ctx, _tnl_draw_prims ); return; } - else if (max_index >= max) { + else if (max_index > max) { /* The software TNL pipeline has a fixed amount of storage for * vertices and it is necessary to split incoming drawing commands * if they exceed that limit. diff --git a/reactos/dll/3rdparty/mesa32/src/tnl/t_vb_fog.c b/reactos/dll/3rdparty/mesa32/src/tnl/t_vb_fog.c index 5440ff7894d..d8bca3820bc 100644 --- a/reactos/dll/3rdparty/mesa32/src/tnl/t_vb_fog.c +++ b/reactos/dll/3rdparty/mesa32/src/tnl/t_vb_fog.c @@ -41,7 +41,6 @@ struct fog_stage_data { GLvector4f fogcoord; /* has actual storage allocated */ - GLvector4f input; /* points into VB->EyePtr Z values */ }; #define FOG_STAGE_DATA(stage) ((struct fog_stage_data *)stage->privatePtr) @@ -91,7 +90,8 @@ init_static_data( void ) * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function. * Fog coordinates are distances from the eye (typically between the * near and far clip plane distances). - * Note the fog (eye Z) coords may be negative so we use ABS(z) below. + * Note that fogcoords may be negative, if eye z is source absolute + * value must be taken earlier. * Fog blend factors are in the range [0,1]. */ static void @@ -114,7 +114,7 @@ compute_fog_blend_factors(GLcontext *ctx, GLvector4f *out, const GLvector4f *in) else d = 1.0F / (ctx->Fog.End - ctx->Fog.Start); for ( i = 0 ; i < n ; i++, STRIDE_F(v, stride)) { - const GLfloat z = FABSF(*v); + const GLfloat z = *v; GLfloat f = (end - z) * d; data[i][0] = CLAMP(f, 0.0F, 1.0F); } @@ -122,14 +122,14 @@ compute_fog_blend_factors(GLcontext *ctx, GLvector4f *out, const GLvector4f *in) case GL_EXP: d = ctx->Fog.Density; for ( i = 0 ; i < n ; i++, STRIDE_F(v,stride)) { - const GLfloat z = FABSF(*v); + const GLfloat z = *v; NEG_EXP( data[i][0], d * z ); } break; case GL_EXP2: d = ctx->Fog.Density*ctx->Fog.Density; for ( i = 0 ; i < n ; i++, STRIDE_F(v, stride)) { - const GLfloat z = FABSF(*v); + const GLfloat z = *v; NEG_EXP( data[i][0], d * z * z ); } break; @@ -153,6 +153,8 @@ run_fog_stage(GLcontext *ctx, struct tnl_pipeline_stage *stage) if (ctx->Fog.FogCoordinateSource == GL_FRAGMENT_DEPTH_EXT) { + GLuint i; + GLfloat *coord; /* Fog is computed from vertex or fragment Z values */ /* source = VB->ObjPtr or VB->EyePtr coords */ /* dest = VB->AttribPtr[_TNL_ATTRIB_FOG] = fog stage private storage */ @@ -167,11 +169,10 @@ run_fog_stage(GLcontext *ctx, struct tnl_pipeline_stage *stage) */ input = &store->fogcoord; - /* NOTE: negate plane here so we get positive fog coords! */ - plane[0] = -m[2]; - plane[1] = -m[6]; - plane[2] = -m[10]; - plane[3] = -m[14]; + plane[0] = m[2]; + plane[1] = m[6]; + plane[2] = m[10]; + plane[3] = m[14]; /* Full eye coords weren't required, just calculate the * eye Z values. */ @@ -180,18 +181,29 @@ run_fog_stage(GLcontext *ctx, struct tnl_pipeline_stage *stage) VB->ObjPtr, plane ); input->count = VB->ObjPtr->count; + + /* make sure coords are really positive + NOTE should avoid going through array twice */ + coord = input->start; + for (i = 0; i < input->count; i++) { + *coord = FABSF(*coord); + STRIDE_F(coord, input->stride); + } } else { - /* fog coordinates = eye Z coordinates (use ABS later) */ - input = &store->input; + /* fog coordinates = eye Z coordinates - need to copy for ABS */ + input = &store->fogcoord; if (VB->EyePtr->size < 2) _mesa_vector4f_clean_elem( VB->EyePtr, VB->Count, 2 ); - input->data = (GLfloat (*)[4]) &(VB->EyePtr->data[0][2]); - input->start = VB->EyePtr->start+2; - input->stride = VB->EyePtr->stride; + input->stride = 4 * sizeof(GLfloat); input->count = VB->EyePtr->count; + coord = VB->EyePtr->start; + for (i = 0 ; i < VB->EyePtr->count; i++) { + input->data[i][0] = FABSF(coord[2]); + STRIDE_F(coord, VB->EyePtr->stride); + } } } else { @@ -234,7 +246,6 @@ alloc_fog_data(GLcontext *ctx, struct tnl_pipeline_stage *stage) return GL_FALSE; _mesa_vector4f_alloc( &store->fogcoord, 0, tnl->vb.Size, 32 ); - _mesa_vector4f_init( &store->input, 0, NULL ); if (!inited) init_static_data(); diff --git a/reactos/dll/3rdparty/mesa32/src/tnl/t_vertex_sse.c b/reactos/dll/3rdparty/mesa32/src/tnl/t_vertex_sse.c index ad4cc62d5f7..9515d9f81f5 100644 --- a/reactos/dll/3rdparty/mesa32/src/tnl/t_vertex_sse.c +++ b/reactos/dll/3rdparty/mesa32/src/tnl/t_vertex_sse.c @@ -39,6 +39,12 @@ #include "x86/common_x86_asm.h" +/** + * Number of bytes to allocate for generated SSE functions + */ +#define MAX_SSE_CODE_SIZE 1024 + + #define X 0 #define Y 1 #define Z 2 @@ -348,8 +354,6 @@ static GLboolean build_vertex_emit( struct x86_program *p ) struct x86_reg vp1 = x86_make_reg(file_XMM, 2); GLubyte *fixup, *label; - x86_init_func(&p->func); - /* Push a few regs? */ x86_push(&p->func, countEBP); @@ -621,7 +625,10 @@ static GLboolean build_vertex_emit( struct x86_program *p ) x86_pop(&p->func, countEBP); x86_ret(&p->func); + assert(!vtx->emit); vtx->emit = (tnl_emit_func)x86_get_func(&p->func); + + assert( (char *) p->func.csr - (char *) p->func.store <= MAX_SSE_CODE_SIZE ); return GL_TRUE; } @@ -646,7 +653,10 @@ void _tnl_generate_sse_emit( GLcontext *ctx ) p.identity = x86_make_reg(file_XMM, 6); p.chan0 = x86_make_reg(file_XMM, 7); - x86_init_func(&p.func); + if (!x86_init_func(&p.func, MAX_SSE_CODE_SIZE)) { + vtx->emit = NULL; + return; + } if (build_vertex_emit(&p)) { _tnl_register_fastpath( vtx, GL_TRUE ); diff --git a/reactos/dll/3rdparty/mesa32/src/tnl/t_vp_build.c b/reactos/dll/3rdparty/mesa32/src/tnl/t_vp_build.c index dff062a417c..b7bc1977237 100644 --- a/reactos/dll/3rdparty/mesa32/src/tnl/t_vp_build.c +++ b/reactos/dll/3rdparty/mesa32/src/tnl/t_vp_build.c @@ -1,8 +1,8 @@ /* * Mesa 3-D graphics library - * Version: 6.5 + * Version: 7.1 * - * Copyright (C) 2006 Tungsten Graphics All Rights Reserved. + * Copyright (C) 2007 Tungsten Graphics All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,11 +33,11 @@ #include "glheader.h" #include "macros.h" #include "enums.h" -#include "program.h" -#include "prog_instruction.h" -#include "prog_parameter.h" -#include "prog_print.h" -#include "prog_statevars.h" +#include "shader/program.h" +#include "shader/prog_instruction.h" +#include "shader/prog_parameter.h" +#include "shader/prog_print.h" +#include "shader/prog_statevars.h" #include "t_context.h" /* NOTE: very light dependency on this */ #include "t_vp_build.h" @@ -457,9 +457,13 @@ static void register_matrix_param5( struct tnl_program *p, } +/** + * Convert a ureg source register to a prog_src_register. + */ static void emit_arg( struct prog_src_register *src, struct ureg reg ) { + assert(reg.file != PROGRAM_OUTPUT); src->File = reg.file; src->Index = reg.idx; src->Swizzle = reg.swz; @@ -469,15 +473,24 @@ static void emit_arg( struct prog_src_register *src, src->RelAddr = 0; } +/** + * Convert a ureg dest register to a prog_dst_register. + */ static void emit_dst( struct prog_dst_register *dst, struct ureg reg, GLuint mask ) { + /* Check for legal output register type. UNDEFINED will occur in + * instruction that don't produce a result (like END). + */ + assert(reg.file == PROGRAM_TEMPORARY || + reg.file == PROGRAM_OUTPUT || + reg.file == PROGRAM_UNDEFINED); dst->File = reg.file; dst->Index = reg.idx; /* allow zero as a shorthand for xyzw */ dst->WriteMask = mask ? mask : WRITEMASK_XYZW; - dst->CondMask = COND_TR; - dst->CondSwizzle = 0; + dst->CondMask = COND_TR; /* always pass cond test */ + dst->CondSwizzle = SWIZZLE_NOOP; dst->CondSrc = 0; dst->pad = 0; } @@ -500,7 +513,7 @@ static void debug_insn( struct prog_instruction *inst, const char *fn, static void emit_op3fn(struct tnl_program *p, - GLuint op, + enum prog_opcode op, struct ureg dest, GLuint mask, struct ureg src0, @@ -686,7 +699,7 @@ static struct ureg get_eye_normal( struct tnl_program *p ) struct ureg rescale = register_param2(p, STATE_INTERNAL, STATE_NORMAL_SCALE); - emit_op2( p, OPCODE_MUL, p->eye_normal, 0, normal, + emit_op2( p, OPCODE_MUL, p->eye_normal, 0, p->eye_normal, swizzle1(rescale, X)); } } @@ -956,13 +969,19 @@ static void build_lighting( struct tnl_program *p ) STATE_POSITION); struct ureg V = get_eye_position(p); struct ureg dist = get_temp(p); + struct ureg tmpPpli = get_temp(p); VPpli = get_temp(p); half = get_temp(p); - /* Calulate VPpli vector + /* In homogeneous object coordinates + */ + emit_op1(p, OPCODE_RCP, dist, 0, swizzle1(Ppli, W)); + emit_op2(p, OPCODE_MUL, tmpPpli, 0, Ppli, dist); + + /* Calculate VPpli vector */ - emit_op2(p, OPCODE_SUB, VPpli, 0, Ppli, V); + emit_op2(p, OPCODE_SUB, VPpli, 0, tmpPpli, V); /* Normalize VPpli. The dist value also used in * attenuation below. @@ -994,6 +1013,7 @@ static void build_lighting( struct tnl_program *p ) emit_normalize_vec3(p, half, half); release_temp(p, dist); + release_temp(p, tmpPpli); } /* Calculate dot products: @@ -1103,7 +1123,7 @@ static void build_fog( struct tnl_program *p ) { struct ureg fog = register_output(p, VERT_RESULT_FOGC); struct ureg input; - + if (p->state->fog_source_is_depth) { input = swizzle1(get_eye_position(p), Z); } @@ -1111,39 +1131,48 @@ static void build_fog( struct tnl_program *p ) input = swizzle1(register_input(p, VERT_ATTRIB_FOG), X); } - if (p->state->tnl_do_vertex_fog) { + if (p->state->fog_mode && p->state->tnl_do_vertex_fog) { struct ureg params = register_param2(p, STATE_INTERNAL, STATE_FOG_PARAMS_OPTIMIZED); struct ureg tmp = get_temp(p); + GLboolean useabs = (p->state->fog_mode != FOG_EXP2); + + if (useabs) { + emit_op1(p, OPCODE_ABS, tmp, 0, input); + } switch (p->state->fog_mode) { case FOG_LINEAR: { struct ureg id = get_identity_param(p); - emit_op3(p, OPCODE_MAD, tmp, 0, input, swizzle1(params,X), swizzle1(params,Y)); + emit_op3(p, OPCODE_MAD, tmp, 0, useabs ? tmp : input, + swizzle1(params,X), swizzle1(params,Y)); emit_op2(p, OPCODE_MAX, tmp, 0, tmp, swizzle1(id,X)); /* saturate */ emit_op2(p, OPCODE_MIN, fog, WRITEMASK_X, tmp, swizzle1(id,W)); break; } case FOG_EXP: - emit_op1(p, OPCODE_ABS, tmp, 0, input); - emit_op2(p, OPCODE_MUL, tmp, 0, tmp, swizzle1(params,Z)); + emit_op2(p, OPCODE_MUL, tmp, 0, useabs ? tmp : input, + swizzle1(params,Z)); emit_op1(p, OPCODE_EX2, fog, WRITEMASK_X, negate(tmp)); break; case FOG_EXP2: emit_op2(p, OPCODE_MUL, tmp, 0, input, swizzle1(params,W)); - emit_op2(p, OPCODE_MUL, tmp, 0, tmp, tmp); + emit_op2(p, OPCODE_MUL, tmp, 0, tmp, tmp); emit_op1(p, OPCODE_EX2, fog, WRITEMASK_X, negate(tmp)); break; } - + release_temp(p, tmp); } else { /* results = incoming fog coords (compute fog per-fragment later) * * KW: Is it really necessary to do anything in this case? + * BP: Yes, we always need to compute the absolute value, unless + * we want to push that down into the fragment program... */ - emit_op1(p, OPCODE_MOV, fog, WRITEMASK_X, input); + GLboolean useabs = GL_TRUE; + emit_op1(p, useabs ? OPCODE_ABS : OPCODE_MOV, fog, WRITEMASK_X, input); } } diff --git a/reactos/dll/3rdparty/mesa32/src/vbo/vbo_save_draw.c b/reactos/dll/3rdparty/mesa32/src/vbo/vbo_save_draw.c index 8940551d08b..697d00e9d11 100644 --- a/reactos/dll/3rdparty/mesa32/src/vbo/vbo_save_draw.c +++ b/reactos/dll/3rdparty/mesa32/src/vbo/vbo_save_draw.c @@ -132,9 +132,11 @@ static void vbo_bind_vertex_list( GLcontext *ctx, } for (attr = 0; attr < VBO_ATTRIB_MAX; attr++) { - if (node->attrsz[attr]) { + GLuint src = map[attr]; + + if (node->attrsz[src]) { arrays[attr].Ptr = (const GLubyte *)data; - arrays[attr].Size = node->attrsz[attr]; + arrays[attr].Size = node->attrsz[src]; arrays[attr].StrideB = node->vertex_size * sizeof(GLfloat); arrays[attr].Stride = node->vertex_size * sizeof(GLfloat); arrays[attr].Type = GL_FLOAT; diff --git a/reactos/dll/3rdparty/mesa32/src/vbo/vbo_split_copy.c b/reactos/dll/3rdparty/mesa32/src/vbo/vbo_split_copy.c index e142dde6803..b71a93546aa 100644 --- a/reactos/dll/3rdparty/mesa32/src/vbo/vbo_split_copy.c +++ b/reactos/dll/3rdparty/mesa32/src/vbo/vbo_split_copy.c @@ -129,6 +129,13 @@ static GLuint attr_size( const struct gl_client_array *array ) */ static GLboolean check_flush( struct copy_context *copy ) { + GLenum mode = copy->dstprim[copy->dstprim_nr].mode; + + if (GL_TRIANGLE_STRIP == mode && + copy->dstelt_nr & 1) { /* see bug9962 */ + return GL_FALSE; + } + if (copy->dstbuf_nr + 4 > copy->dstbuf_size) return GL_TRUE; @@ -458,7 +465,7 @@ static void replay_init( struct copy_context *copy ) dst->StrideB = copy->vertex_size; dst->Ptr = copy->dstbuf + offset; dst->Enabled = GL_TRUE; - dst->Normalized = GL_TRUE; + dst->Normalized = src->Normalized; dst->BufferObj = ctx->Array.NullBufferObj; dst->_MaxElement = copy->dstbuf_size; /* may be less! */ diff --git a/reactos/dll/3rdparty/mesa32/src/x86-64/glapi_x86-64.S b/reactos/dll/3rdparty/mesa32/src/x86-64/glapi_x86-64.S index 75366e4d305..e58f8f1bc0b 100644 --- a/reactos/dll/3rdparty/mesa32/src/x86-64/glapi_x86-64.S +++ b/reactos/dll/3rdparty/mesa32/src/x86-64/glapi_x86-64.S @@ -29175,7 +29175,11 @@ GL_PREFIX(_dispatch_stub_770): pushq %rdi pushq %rsi pushq %rdx + pushq %rcx + pushq %rbp call _x86_64_get_dispatch@PLT + popq %rbp + popq %rcx popq %rdx popq %rsi popq %rdi @@ -29191,7 +29195,11 @@ GL_PREFIX(_dispatch_stub_770): pushq %rdi pushq %rsi pushq %rdx + pushq %rcx + pushq %rbp call _glapi_get_dispatch + popq %rbp + popq %rcx popq %rdx popq %rsi popq %rdi @@ -29238,6 +29246,44 @@ GL_PREFIX(_dispatch_stub_771): #endif /* defined(GLX_USE_TLS) */ .size GL_PREFIX(_dispatch_stub_771), .-GL_PREFIX(_dispatch_stub_771) + .p2align 4,,15 + .globl GL_PREFIX(_dispatch_stub_772) + .type GL_PREFIX(_dispatch_stub_772), @function + HIDDEN(GL_PREFIX(_dispatch_stub_772)) +GL_PREFIX(_dispatch_stub_772): +#if defined(GLX_USE_TLS) + call _x86_64_get_dispatch@PLT + movq 6176(%rax), %r11 + jmp *%r11 +#elif defined(PTHREADS) + pushq %rdi + pushq %rsi + pushq %rdx + call _x86_64_get_dispatch@PLT + popq %rdx + popq %rsi + popq %rdi + movq 6176(%rax), %r11 + jmp *%r11 +#else + movq _glapi_Dispatch(%rip), %rax + testq %rax, %rax + je 1f + movq 6176(%rax), %r11 + jmp *%r11 +1: + pushq %rdi + pushq %rsi + pushq %rdx + call _glapi_get_dispatch + popq %rdx + popq %rsi + popq %rdi + movq 6176(%rax), %r11 + jmp *%r11 +#endif /* defined(GLX_USE_TLS) */ + .size GL_PREFIX(_dispatch_stub_772), .-GL_PREFIX(_dispatch_stub_772) + .globl GL_PREFIX(ArrayElementEXT) ; .set GL_PREFIX(ArrayElementEXT), GL_PREFIX(ArrayElement) .globl GL_PREFIX(BindTextureEXT) ; .set GL_PREFIX(BindTextureEXT), GL_PREFIX(BindTexture) .globl GL_PREFIX(DrawArraysEXT) ; .set GL_PREFIX(DrawArraysEXT), GL_PREFIX(DrawArrays) diff --git a/reactos/dll/3rdparty/mesa32/src/x86-64/xform4.S b/reactos/dll/3rdparty/mesa32/src/x86-64/xform4.S index 65328f6666e..f512b3ac6d4 100644 --- a/reactos/dll/3rdparty/mesa32/src/x86-64/xform4.S +++ b/reactos/dll/3rdparty/mesa32/src/x86-64/xform4.S @@ -1,10 +1,8 @@ -/* $Id: xform4.S,v 1.2 2006/04/17 18:58:24 krh Exp $ */ - /* * Mesa 3-D graphics library - * Version: 3.5 + * Version: 7.0.1 * - * Copyright (C) 1999-2001 Brian Paul All Rights Reserved. + * Copyright (C) 1999-2007 Brian Paul All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -64,7 +62,7 @@ _mesa_x86_64_transform_points4_general: p4_general_loop: - movaps (%rdx), %xmm8 /* ox | oy | oz | ow */ + movups (%rdx), %xmm8 /* ox | oy | oz | ow */ prefetchw 16(%rdi) pshufd $0x00, %xmm8, %xmm0 /* ox | ox | ox | ox */ @@ -149,7 +147,7 @@ _mesa_x86_64_transform_points4_3d: p4_3d_loop: - movaps (%rdx), %xmm8 /* ox | oy | oz | ow */ + movups (%rdx), %xmm8 /* ox | oy | oz | ow */ prefetchw 16(%rdi) pshufd $0x00, %xmm8, %xmm0 /* ox | ox | ox | ox */ diff --git a/reactos/dll/3rdparty/mesa32/src/x86/glapi_x86.S b/reactos/dll/3rdparty/mesa32/src/x86/glapi_x86.S index 9e19e38697c..ef2d64a0cec 100644 --- a/reactos/dll/3rdparty/mesa32/src/x86/glapi_x86.S +++ b/reactos/dll/3rdparty/mesa32/src/x86/glapi_x86.S @@ -947,14 +947,16 @@ GLNAME(gl_dispatch_functions_start): GL_STUB(RenderbufferStorageEXT, _gloffset_RenderbufferStorageEXT, RenderbufferStorageEXT@16) GL_STUB(_dispatch_stub_767, _gloffset_BlitFramebufferEXT, _dispatch_stub_767@40) HIDDEN(GL_PREFIX(_dispatch_stub_767, _dispatch_stub_767@40)) - GL_STUB(_dispatch_stub_768, _gloffset_ProgramEnvParameters4fvEXT, _dispatch_stub_768@16) + GL_STUB(_dispatch_stub_768, _gloffset_StencilFuncSeparateATI, _dispatch_stub_768@16) HIDDEN(GL_PREFIX(_dispatch_stub_768, _dispatch_stub_768@16)) - GL_STUB(_dispatch_stub_769, _gloffset_ProgramLocalParameters4fvEXT, _dispatch_stub_769@16) + GL_STUB(_dispatch_stub_769, _gloffset_ProgramEnvParameters4fvEXT, _dispatch_stub_769@16) HIDDEN(GL_PREFIX(_dispatch_stub_769, _dispatch_stub_769@16)) - GL_STUB(_dispatch_stub_770, _gloffset_GetQueryObjecti64vEXT, _dispatch_stub_770@12) - HIDDEN(GL_PREFIX(_dispatch_stub_770, _dispatch_stub_770@12)) - GL_STUB(_dispatch_stub_771, _gloffset_GetQueryObjectui64vEXT, _dispatch_stub_771@12) + GL_STUB(_dispatch_stub_770, _gloffset_ProgramLocalParameters4fvEXT, _dispatch_stub_770@16) + HIDDEN(GL_PREFIX(_dispatch_stub_770, _dispatch_stub_770@16)) + GL_STUB(_dispatch_stub_771, _gloffset_GetQueryObjecti64vEXT, _dispatch_stub_771@12) HIDDEN(GL_PREFIX(_dispatch_stub_771, _dispatch_stub_771@12)) + GL_STUB(_dispatch_stub_772, _gloffset_GetQueryObjectui64vEXT, _dispatch_stub_772@12) + HIDDEN(GL_PREFIX(_dispatch_stub_772, _dispatch_stub_772@12)) GL_STUB_ALIAS(ArrayElementEXT, _gloffset_ArrayElement, ArrayElementEXT@4, ArrayElement, ArrayElement@4) GL_STUB_ALIAS(BindTextureEXT, _gloffset_BindTexture, BindTextureEXT@8, BindTexture, BindTexture@8) GL_STUB_ALIAS(DrawArraysEXT, _gloffset_DrawArrays, DrawArraysEXT@12, DrawArrays, DrawArrays@12) @@ -1086,6 +1088,7 @@ GLNAME(gl_dispatch_functions_start): GL_STUB_ALIAS(MultiTexCoord4iv, _gloffset_MultiTexCoord4ivARB, MultiTexCoord4iv@8, MultiTexCoord4ivARB, MultiTexCoord4ivARB@8) GL_STUB_ALIAS(MultiTexCoord4s, _gloffset_MultiTexCoord4sARB, MultiTexCoord4s@20, MultiTexCoord4sARB, MultiTexCoord4sARB@20) GL_STUB_ALIAS(MultiTexCoord4sv, _gloffset_MultiTexCoord4svARB, MultiTexCoord4sv@8, MultiTexCoord4svARB, MultiTexCoord4svARB@8) + GL_STUB_ALIAS(StencilOpSeparateATI, _gloffset_StencilOpSeparate, StencilOpSeparateATI@16, StencilOpSeparate, StencilOpSeparate@16) GL_STUB_ALIAS(LoadTransposeMatrixd, _gloffset_LoadTransposeMatrixdARB, LoadTransposeMatrixd@4, LoadTransposeMatrixdARB, LoadTransposeMatrixdARB@4) GL_STUB_ALIAS(LoadTransposeMatrixf, _gloffset_LoadTransposeMatrixfARB, LoadTransposeMatrixf@4, LoadTransposeMatrixfARB, LoadTransposeMatrixfARB@4) GL_STUB_ALIAS(MultTransposeMatrixd, _gloffset_MultTransposeMatrixdARB, MultTransposeMatrixd@4, MultTransposeMatrixdARB, MultTransposeMatrixdARB@4) diff --git a/reactos/dll/3rdparty/mesa32/src/x86/matypes.h b/reactos/dll/3rdparty/mesa32/src/x86/matypes.h index 375f882e81f..3ce781d495b 100644 --- a/reactos/dll/3rdparty/mesa32/src/x86/matypes.h +++ b/reactos/dll/3rdparty/mesa32/src/x86/matypes.h @@ -15,16 +15,16 @@ #define CTX_DRIVER_CTX 952 -#define CTX_LIGHT_ENABLED 39312 -#define CTX_LIGHT_SHADE_MODEL 39316 -#define CTX_LIGHT_COLOR_MAT_FACE 39320 -#define CTX_LIGHT_COLOR_MAT_MODE 39324 -#define CTX_LIGHT_COLOR_MAT_MASK 39328 -#define CTX_LIGHT_COLOR_MAT_ENABLED 39332 -#define CTX_LIGHT_ENABLED_LIST 39340 -#define CTX_LIGHT_NEED_VERTS 43701 -#define CTX_LIGHT_FLAGS 43704 -#define CTX_LIGHT_BASE_COLOR 43708 +#define CTX_LIGHT_ENABLED 39056 +#define CTX_LIGHT_SHADE_MODEL 39060 +#define CTX_LIGHT_COLOR_MAT_FACE 39064 +#define CTX_LIGHT_COLOR_MAT_MODE 39068 +#define CTX_LIGHT_COLOR_MAT_MASK 39072 +#define CTX_LIGHT_COLOR_MAT_ENABLED 39076 +#define CTX_LIGHT_ENABLED_LIST 39084 +#define CTX_LIGHT_NEED_VERTS 43445 +#define CTX_LIGHT_FLAGS 43448 +#define CTX_LIGHT_BASE_COLOR 43452 /* ============================================================= diff --git a/reactos/dll/3rdparty/mesa32/src/x86/read_rgba_span_x86.S b/reactos/dll/3rdparty/mesa32/src/x86/read_rgba_span_x86.S index 3cbcd719960..2e5c3be83fe 100644 --- a/reactos/dll/3rdparty/mesa32/src/x86/read_rgba_span_x86.S +++ b/reactos/dll/3rdparty/mesa32/src/x86/read_rgba_span_x86.S @@ -33,20 +33,7 @@ .file "read_rgba_span_x86.S" #if !defined(__DJGPP__) && !defined(__MINGW32__) /* this one cries for assyntax.h */ /* Kevin F. Quinn 2nd July 2006 - * Replace data segment constants with text-segment instructions - .section .rodata - .align 16 - .type mask, @object - .size mask, 32 -mask: - .long 0xff00ff00 - .long 0xff00ff00 - .long 0xff00ff00 - .long 0xff00ff00 - .long 0x00ff0000 - .long 0x00ff0000 - .long 0x00ff0000 - .long 0x00ff0000 + * Replaced data segment constants with text-segment instructions. */ #define LOAD_MASK(mvins,m1,m2) \ pushl $0xff00ff00 ;\ @@ -61,8 +48,7 @@ mask: mvins (%esp), m2 ;\ addl $32, %esp - -/* I implemented these as macros because the appear in quite a few places, +/* I implemented these as macros because they appear in several places, * and I've tweaked them a number of times. I got tired of changing every * place they appear. :) */ @@ -99,11 +85,6 @@ _generic_read_RGBA_span_BGRA8888_REV_MMX: #ifdef USE_INNER_EMMS emms #endif -/* Kevin F. Quinn 2nd July 2006 - * Replace data segment constants with text-segment instructions - movq mask, %mm1 - movq mask+16, %mm2 - */ LOAD_MASK(movq,%mm1,%mm2) movl 8(%esp), %ebx /* source pointer */ @@ -201,11 +182,7 @@ _generic_read_RGBA_span_BGRA8888_REV_SSE: #ifdef USE_INNER_EMMS emms #endif -/* Kevin F. Quinn 2nd July 2006 - * Replace data segment constants with text-segment instructions - movq mask, %mm1 - movq mask+16, %mm2 - */ + LOAD_MASK(movq,%mm1,%mm2) movl 16(%esp), %ebx /* source pointer */ @@ -364,11 +341,6 @@ _generic_read_RGBA_span_BGRA8888_REV_SSE2: pushl %esi pushl %ebx -/* Kevin F. Quinn 2nd July 2006 - * Replace data segment constants with text-segment instructions - movdqa mask, %xmm1 - movdqa mask+16, %xmm2 - */ LOAD_MASK(movdqu,%xmm1,%xmm2) movl 12(%esp), %ebx /* source pointer */ @@ -491,60 +463,12 @@ _generic_read_RGBA_span_BGRA8888_REV_SSE2: -/* Kevin F. Quinn 2nd July 2006 - * Replace data segment constants with text-segment instructions - */ -#if 0 - .section .rodata - - .align 16 -mask_565: - .word 0xf800 - .word 0x07e0 - .word 0x001f - .word 0x0000 - -/* Setting SCALE_ADJUST to 5 gives a perfect match with the classic C - * implementation in Mesa. Setting SCALE_ADJUST to 0 is slightly faster but - * at a small cost to accuracy. - */ - -#define SCALE_ADJUST 5 -#if SCALE_ADJUST == 5 -prescale: - .word 0x0001 - .word 0x0010 - .word 0x0200 - .word 0x0000 - -scale: - .word 0x20e8 /* (0x00ff0000 / 0x000007c0) + 1 */ - .word 0x40c5 /* (0x00ff0000 / 0x000003f0) + 1 */ - .word 0x839d /* (0x00ff0000 / 0x000001f0) + 1 */ - .word 0x0000 -#elif SCALE_ADJUST == 0 -prescale: - .word 0x0001 - .word 0x0020 - .word 0x0800 - .word 0x0000 - -scale: - .word 0x0108 /* (0x00ff0000 / 0x0000f800) + 1 */ - .word 0x0104 /* (0x00ff0000 / 0x0000fc00) + 1 */ - .word 0x0108 /* (0x00ff0000 / 0x0000f800) + 1 */ - .word 0x0000 -#else -#error SCALE_ADJUST must either be 5 or 0. -#endif - - -alpha: .long 0x00000000 - .long 0x00ff0000 -#endif - #define MASK_565_L 0x07e0f800 #define MASK_565_H 0x0000001f +/* Setting SCALE_ADJUST to 5 gives a perfect match with the + * classic C implementation in Mesa. Setting SCALE_ADJUST + * to 0 is slightly faster but at a small cost to accuracy. + */ #define SCALE_ADJUST 5 #if SCALE_ADJUST == 5 #define PRESCALE_L 0x00100001 @@ -581,23 +505,17 @@ _generic_read_RGBA_span_RGB565_MMX: movl 8(%esp), %edx /* destination pointer */ movl 12(%esp), %ecx /* number of pixels to copy */ -/* Kevin F. Quinn 2nd July 2006 - * Replace data segment constants with text-segment instructions - movq mask_565, %mm5 - movq prescale, %mm6 - movq scale, %mm7 - */ - pushl MASK_565_H - pushl MASK_565_L + pushl $MASK_565_H + pushl $MASK_565_L movq (%esp), %mm5 - pushl PRESCALE_H - pushl PRESCALE_L + pushl $PRESCALE_H + pushl $PRESCALE_L movq (%esp), %mm6 - pushl SCALE_H - pushl SCALE_L + pushl $SCALE_H + pushl $SCALE_L movq (%esp), %mm7 - pushl ALPHA_H - pushl ALPHA_L + pushl $ALPHA_H + pushl $ALPHA_L movq (%esp), %mm3 addl $32,%esp @@ -648,11 +566,6 @@ _generic_read_RGBA_span_RGB565_MMX: /* Always set the alpha value to 0xff. */ -/* Kevin F. Quinn 2nd July 2006 - * Replace data segment constants with text-segment instructions - por alpha, %mm0 - por alpha, %mm2 - */ por %mm3, %mm0 por %mm3, %mm2 @@ -665,8 +578,6 @@ _generic_read_RGBA_span_RGB565_MMX: movq %mm0, (%edx) addl $8, %edx - - pshufw $0xaa, %mm4, %mm0 pshufw $0xff, %mm4, %mm2 @@ -681,11 +592,6 @@ _generic_read_RGBA_span_RGB565_MMX: pmulhuw %mm7, %mm0 pmulhuw %mm7, %mm2 -/* Kevin F. Quinn 2nd July 2006 - * Replace data segment constants with text-segment instructions - por alpha, %mm0 - por alpha, %mm2 - */ por %mm3, %mm0 por %mm3, %mm2 @@ -724,11 +630,6 @@ _generic_read_RGBA_span_RGB565_MMX: pmulhuw %mm7, %mm0 pmulhuw %mm7, %mm2 -/* Kevin F. Quinn 2nd July 2006 - * Replace data segment constants with text-segment instructions - por alpha, %mm0 - por alpha, %mm2 - */ por %mm3, %mm0 por %mm3, %mm2 @@ -757,10 +658,6 @@ _generic_read_RGBA_span_RGB565_MMX: #endif pmulhuw %mm7, %mm0 -/* Kevin F. Quinn 2nd July 2006 - * Replace data segment constants with text-segment instructions - por alpha, %mm0 - */ por %mm3, %mm0 packuswb %mm0, %mm0 diff --git a/reactos/dll/3rdparty/mesa32/src/x86/rtasm/x86sse.c b/reactos/dll/3rdparty/mesa32/src/x86/rtasm/x86sse.c index 3ea37bb5e76..612cd51a6ee 100644 --- a/reactos/dll/3rdparty/mesa32/src/x86/rtasm/x86sse.c +++ b/reactos/dll/3rdparty/mesa32/src/x86/rtasm/x86sse.c @@ -1063,20 +1063,29 @@ struct x86_reg x86_fn_arg( struct x86_function *p, } -void x86_init_func( struct x86_function *p ) -{ - x86_init_func_size(p, 1024); -} - -void x86_init_func_size( struct x86_function *p, GLuint code_size ) +/** + * Initialize an x86_function object, allocating space for up to + * 'code_size' bytes of code. + */ +GLboolean x86_init_func( struct x86_function *p, GLuint code_size ) { + assert(!p->store); p->store = _mesa_exec_malloc(code_size); - p->csr = p->store; + if (p->store) { + p->csr = p->store; + return GL_TRUE; + } + else { + p->csr = NULL; + return GL_FALSE; + } } void x86_release_func( struct x86_function *p ) { - _mesa_exec_free(p->store); + if (p->store) + _mesa_exec_free(p->store); + p->store = p->csr = NULL; } diff --git a/reactos/dll/3rdparty/mesa32/src/x86/rtasm/x86sse.h b/reactos/dll/3rdparty/mesa32/src/x86/rtasm/x86sse.h index 66fb852ac98..42b09937bca 100644 --- a/reactos/dll/3rdparty/mesa32/src/x86/rtasm/x86sse.h +++ b/reactos/dll/3rdparty/mesa32/src/x86/rtasm/x86sse.h @@ -80,8 +80,7 @@ enum sse_cc { */ -void x86_init_func( struct x86_function *p ); -void x86_init_func_size( struct x86_function *p, GLuint code_size ); +GLboolean x86_init_func( struct x86_function *p, GLuint code_size ); void x86_release_func( struct x86_function *p ); void (*x86_get_func( struct x86_function *p ))( void );